Fixed generate that instantiated 4*4 histogram modules (including disables), tried with single histogram per channel - added 8% of all slices

implemented optional skipping/fast forward of the data blocks when buffer is over/underrun during memory access

started modification of the i2c sequencer to support SMIA registers (2 bytes address, >=2 bytes of data) and register read

Finished simulation/testing of a single-channel acquisition/processing/compression, fixed problems with Xilinx tools to pass sythesis/implementation