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Commit cbed019c authored by Andrey Filippov's avatar Andrey Filippov
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continue hardware debugging

parent 3bff174e
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.project
View file @ cbed019c
......@@ -62,42 +62,42 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150904164653967.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150905181423920.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150904164653967.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150905181423920.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150904164653967.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150905181423920.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150904164653967.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150905181423920.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150904164653967.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150905181423920.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150904164653967.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150905181423920.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150904164653967.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150905180655479.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150904164653967.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150905181423920.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
......@@ -112,7 +112,7 @@
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150904164653967.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150905102847882.log</location>
</link>
<link>
<name>vivado_state/x393-opt-phys.dcp</name>
......@@ -132,7 +132,7 @@
<link>
<name>vivado_state/x393-synth.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20150904164653967.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20150905102847882.dcp</location>
</link>
</linkedResources>
</projectDescription>
.settings/com.elphel.vdt.VivadoBitstream.prefs
View file @ cbed019c
VivadoBitstream_103_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
VivadoBitstream_105_force=true
VivadoBitstream_122_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->
VivadoBitstream_123_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->
VivadoBitstream_124_force=true
com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_122_PreBitstreamTCL<-@\#\#@->
com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_122_PreBitstreamTCL<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoOpt.prefs 0 → 100644
View file @ cbed019c
VivadoOpt_123_SkipSnapshotOpt=true
VivadoOpt_124_SkipSnapshotOpt=true
com.elphel.store.context.VivadoOpt=VivadoOpt_123_SkipSnapshotOpt<-@\#\#@->VivadoOpt_124_SkipSnapshotOpt<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoOptPhys.prefs 0 → 100644
View file @ cbed019c
VivadoOptPhys_123_SkipSnapshotOptPhys=true
VivadoOptPhys_124_SkipSnapshotOptPhys=true
com.elphel.store.context.VivadoOptPhys=VivadoOptPhys_123_SkipSnapshotOptPhys<-@\#\#@->VivadoOptPhys_124_SkipSnapshotOptPhys<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoOptPower.prefs 0 → 100644
View file @ cbed019c
VivadoOptPower_124_SkipSnapshotOptPower=true
VivadoOptPower_125_SkipSnapshotOptPower=true
com.elphel.store.context.VivadoOptPower=VivadoOptPower_124_SkipSnapshotOptPower<-@\#\#@->VivadoOptPower_125_SkipSnapshotOptPower<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoPlace.prefs
View file @ cbed019c
VivadoPlace_111_verbose_place=true
com.elphel.store.context.VivadoPlace=VivadoPlace_111_verbose_place<-@\#\#@->
VivadoPlace_123_SkipSnapshotPlace=true
VivadoPlace_124_SkipSnapshotPlace=true
com.elphel.store.context.VivadoPlace=VivadoPlace_111_verbose_place<-@\#\#@->VivadoPlace_123_SkipSnapshotPlace<-@\#\#@->VivadoPlace_124_SkipSnapshotPlace<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoRoute.prefs 0 → 100644
View file @ cbed019c
VivadoRoute_122_SkipSnapshotRoute=true
VivadoRoute_123_SkipSnapshotRoute=true
com.elphel.store.context.VivadoRoute=VivadoRoute_122_SkipSnapshotRoute<-@\#\#@->VivadoRoute_123_SkipSnapshotRoute<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoSynthesis.prefs
View file @ cbed019c
......@@ -2,9 +2,13 @@ VivadoSynthesis_101_MaxMsg=10000
VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_115_flatten_hierarchy=none
VivadoSynthesis_121_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_122_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_122_SkipSnapshotSynth=true
VivadoSynthesis_123_ResetProject=true
VivadoSynthesis_123_SkipSnapshotSynth=true
VivadoSynthesis_127_verbose=true
VivadoSynthesis_81_parser_mode=1
VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->Synth 8-638<-@\#\#@->Synth 8-256<-@\#\#@->
VivadoSynthesis_95_ShowInfo=true
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->VivadoSynthesis_121_ConstraintsFiles<-@\#\#@->
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->VivadoSynthesis_121_ConstraintsFiles<-@\#\#@->VivadoSynthesis_122_SkipSnapshotSynth<-@\#\#@->VivadoSynthesis_123_ResetProject<-@\#\#@->VivadoSynthesis_123_SkipSnapshotSynth<-@\#\#@->VivadoSynthesis_122_ConstraintsFiles<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoTimimgSummaryReportSynthesis.prefs
View file @ cbed019c
VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary=true
VivadoTimimgSummaryReportSynthesis_121_DisableVivadoTimingSummary=true
com.elphel.store.context.VivadoTimimgSummaryReportSynthesis=VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary<-@\#\#@->VivadoTimimgSummaryReportSynthesis_121_DisableVivadoTimingSummary<-@\#\#@->
VivadoTimimgSummaryReportSynthesis_122_DisableVivadoTimingSummary=true
com.elphel.store.context.VivadoTimimgSummaryReportSynthesis=VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary<-@\#\#@->VivadoTimimgSummaryReportSynthesis_121_DisableVivadoTimingSummary<-@\#\#@->VivadoTimimgSummaryReportSynthesis_122_DisableVivadoTimingSummary<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoTimingReportImplemented.prefs
View file @ cbed019c
com.elphel.store.context.VivadoTimingReportImplemented=VivadoTimingReportImplemented_132_rawfile<-@\#\#@->
VivadoTimingReportImplemented_121_DisableVivadoTiming=true
VivadoTimingReportImplemented_122_DisableVivadoTiming=true
com.elphel.store.context.VivadoTimingReportImplemented=VivadoTimingReportImplemented_132_rawfile<-@\#\#@->VivadoTimingReportImplemented_121_DisableVivadoTiming<-@\#\#@->VivadoTimingReportImplemented_122_DisableVivadoTiming<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoTimingReportSynthesis.prefs
View file @ cbed019c
VivadoTimingReportSynthesis_102_DisableVivadoTiming=true
com.elphel.store.context.VivadoTimingReportSynthesis=VivadoTimingReportSynthesis_102_DisableVivadoTiming<-@\#\#@->
VivadoTimingReportSynthesis_121_DisableVivadoTiming=true
VivadoTimingReportSynthesis_122_DisableVivadoTiming=true
com.elphel.store.context.VivadoTimingReportSynthesis=VivadoTimingReportSynthesis_102_DisableVivadoTiming<-@\#\#@->VivadoTimingReportSynthesis_121_DisableVivadoTiming<-@\#\#@->VivadoTimingReportSynthesis_122_DisableVivadoTiming<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.iverilog.prefs
View file @ cbed019c
com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_98_GTKWaveSavFile<-@\#\#@->iverilog_100_TopModulesOther<-@\#\#@->iverilog_102_ExtraFiles<-@\#\#@->iverilog_103_IncludeDir<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->iverilog_113_SaveLogsSimulator<-@\#\#@->iverilog_109_ShowNoProblem<-@\#\#@->iverilog_110_ShowWarnings<-@\#\#@->
com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_98_GTKWaveSavFile<-@\#\#@->iverilog_100_TopModulesOther<-@\#\#@->iverilog_102_ExtraFiles<-@\#\#@->iverilog_103_IncludeDir<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->iverilog_113_SaveLogsSimulator<-@\#\#@->iverilog_109_ShowNoProblem<-@\#\#@->iverilog_110_ShowWarnings<-@\#\#@->iverilog_102_TopModulesOther<-@\#\#@->iverilog_104_ExtraFiles<-@\#\#@->iverilog_105_IncludeDir<-@\#\#@->iverilog_110_ShowNoProblem<-@\#\#@->iverilog_113_SaveLogsPreprocessor<-@\#\#@->iverilog_121_GrepFindErrWarn<-@\#\#@->
eclipse.preferences.version=1
iverilog_100_TopModulesOther=glbl<-@\#\#@->
iverilog_101_TopModulesOther=glbl<-@\#\#@->
iverilog_102_ExtraFiles=glbl.v<-@\#\#@->
iverilog_102_TopModulesOther=glbl<-@\#\#@->
iverilog_103_ExtraFiles=glbl.v<-@\#\#@->
iverilog_103_IncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->
iverilog_104_ExtraFiles=glbl.v<-@\#\#@->
iverilog_104_IncludeDir=${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->
iverilog_105_IncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->
iverilog_109_ShowNoProblem=true
iverilog_110_ShowNoProblem=true
iverilog_110_ShowWarnings=false
iverilog_113_SaveLogsPreprocessor=true
iverilog_113_SaveLogsSimulator=true
iverilog_121_GrepFindErrWarn=error|warning|sorry
iverilog_77_Param_Exe=/usr/local/bin/iverilog
iverilog_78_VVP_Exe=/usr/local/bin/vvp
iverilog_79_GtkWave_Exe=/usr/local/bin/gtkwave
......
.settings/org.eclipse.core.resources.prefs 0 → 100644
View file @ cbed019c
eclipse.preferences.version=1
encoding//helpers/convert_data_to_params.py=utf-8
encoding//helpers/convert_pass_init_params.py=utf-8
encoding//helpers/convert_zigzag_rom.py=utf-8
fpga_version.vh
View file @ cbed019c
parameter FPGA_VERSION = 32'h03930011;
\ No newline at end of file
parameter FPGA_VERSION = 32'h03930015;
\ No newline at end of file
py393/x393_sens_cmprs.py
View file @ cbed019c
......@@ -704,9 +704,9 @@ class X393SensCmprs(object):
result = []
# load all shift registers from sources
self.x393_axi_tasks.write_control_register(vrlg.DEBUG_ADDR + vrlg.DEBUG_LOAD, 0);
for _ in range (num32):
for i in range (num32):
seq_num = (self.x393_axi_tasks.read_status(vrlg.DEBUG_STATUS_REG_ADDR) >> vrlg.STATUS_SEQ_SHFT) & 0x3f;
self.x393_axi_tasks.write_control_register(vrlg.DEBUG_ADDR + vrlg.DEBUG_SHIFT_DATA, 0);
self.x393_axi_tasks.write_control_register(vrlg.DEBUG_ADDR + vrlg.DEBUG_SHIFT_DATA, (0,0xffffffff)[i==0]);
while seq_num == (self.x393_axi_tasks.read_status(vrlg.DEBUG_STATUS_REG_ADDR) >> vrlg.STATUS_SEQ_SHFT) & 0x3f:
if time.time() > endTime:
return None
......
sensor/sens_histogram.v
View file @ cbed019c
......@@ -139,6 +139,9 @@ module sens_histogram #(
reg debug_vert_woi_r;
reg [15:0] debug_line_cntr;
reg [15:0] debug_lines;
assign set_left_top_w = pio_stb && (pio_addr == HISTOGRAM_LEFT_TOP );
assign set_width_height_w = pio_stb && (pio_addr == HISTOGRAM_WIDTH_HEIGHT );
......@@ -175,6 +178,14 @@ module sens_histogram #(
// assign debug_mclk = hist_done_mclk;
// assign debug_mclk = set_width_height_w;
always @ (posedge pclk) begin
if (sof) debug_line_cntr <= 0;
else if (line_start_w) debug_line_cntr <= debug_line_cntr + 1;
if (sof) debug_lines <= debug_line_cntr;
end
always @ (posedge pclk) begin
if (!hact) pxd_wa <= 0;
......@@ -372,7 +383,9 @@ module sens_histogram #(
.debug_di (debug_di), // input
.debug_sl (debug_sl), // input
.debug_do (debug_do), // output
.rd_data ({height_m1[15:0], vcntr[15:0], width_m1[15:0], hcntr[15:0]}), // input[31:0]
// .rd_data ({height_m1[15:0], vcntr[15:0], width_m1[15:0], hcntr[15:0]}), // input[31:0]
.rd_data ({debug_lines[15:0], debug_line_cntr[15:0], width_m1[15:0], hcntr[15:0]}), // input[31:0]
//debug_lines <= debug_line_cntr
.wr_data (), // output[31:0] - not used
.stb () // output - not used
);
......
sensor/sens_parallel12.v
View file @ cbed019c
......@@ -277,7 +277,7 @@ module sens_parallel12 #(
else if (set_width_r[1]) line_width_m1 <= data_r[LINE_WIDTH_BITS-1:0] -1;
if (mclk_rst) line_width_internal <= 0;
else if (set_width_r[1]) line_width_internal <= ~ (|data_r[LINE_WIDTH_BITS:0]);
else if (set_width_r[1]) line_width_internal <= ~ (|data_r[LINE_WIDTH_BITS:0]); // line width is 0
end
always @(posedge ipclk) begin
......@@ -292,11 +292,11 @@ module sens_parallel12 #(
if (irst) hact_r <= 0;
else if (hact_ext && !hact_ext_r) hact_r <= 1;
else if (line_width_internal_ipclk?(hact_cntr == 0):(hact_ext ==0)) hact_r <= 0;
else if (line_width_internal_ipclk?(hact_ext ==0):(hact_cntr == 0)) hact_r <= 0;
if (irst) hact_cntr <= 0;
else if (hact_ext && !hact_ext_r) hact_cntr <= line_width_m1_ipclk; // from mclk
else if (hact_r) hact_cntr <= hact_cntr - 1;
if (irst) hact_cntr <= 0;
else if (hact_ext && !hact_ext_r) hact_cntr <= line_width_m1_ipclk; // from mclk
else if (hact_r && !line_width_internal_ipclk) hact_cntr <= hact_cntr - 1;
pxd_out <= pxd_out_pre;
vact_out <= vact_out_pre;
......
sensor/sensor_channel.v
View file @ cbed019c
......@@ -250,7 +250,7 @@ module sensor_channel#(
);
`ifdef DEBUG_RING
localparam DEBUG_RING_LENGTH = 4; // for now - just connect the histogram(s) module(s)
localparam DEBUG_RING_LENGTH = 5; // for now - just connect the histogram(s) module(s)
wire [DEBUG_RING_LENGTH:0] debug_ring; // TODO: adjust number of bits
assign debug_do = debug_ring[0];
assign debug_ring[DEBUG_RING_LENGTH] = debug_di;
......@@ -369,6 +369,50 @@ module sensor_channel#(
assign bit16 = mode[SENSOR_16BIT_BIT];
`ifdef DEBUG_RING
reg vact_to_fifo_r;
reg hact_to_fifo_r;
reg [15:0] debug_line_cntr;
reg [15:0] debug_lines;
reg [15:0] hact_cntr;
reg [15:0] vact_cntr;
always @(posedge ipclk) begin
vact_to_fifo_r <= vact_to_fifo;
hact_to_fifo_r <= hact_to_fifo;
if (vact_to_fifo && !vact_to_fifo_r) debug_line_cntr <= 0;
else if (hact_to_fifo && !hact_to_fifo_r) debug_line_cntr <= debug_line_cntr + 1;
if (vact_to_fifo && !vact_to_fifo_r) debug_lines <= debug_line_cntr;
if (irst) hact_cntr <= 0;
else if (hact_to_fifo && !hact_to_fifo_r) hact_cntr <= hact_cntr + 1;
if (irst) vact_cntr <= 0;
else if (vact_to_fifo && !vact_to_fifo_r) vact_cntr <= vact_cntr + 1;
end
debug_slave #(
.SHIFT_WIDTH (64),
.READ_WIDTH (64),
.WRITE_WIDTH (32),
.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
) debug_slave_i (
.mclk (mclk), // input
.mrst (mrst), // input
.debug_di (debug_ring[5]), // input
.debug_sl (debug_sl), // input
.debug_do (debug_ring[4]), // output
// .rd_data ({height_m1[15:0], vcntr[15:0], width_m1[15:0], hcntr[15:0]}), // input[31:0]
.rd_data ({vact_cntr[15:0], hact_cntr[15:0], debug_lines[15:0], debug_line_cntr[15:0]}), // input[31:0]
//debug_lines <= debug_line_cntr
.wr_data (), // output[31:0] - not used
.stb () // output - not used
);
`endif
always @ (posedge mclk) begin
cmd_ad <= cmd_ad_in;
cmd_stb <= cmd_stb_in;
......
x393_testbench02.tf
View file @ cbed019c
......@@ -2376,7 +2376,7 @@ task setup_sensor_channel;
$display("===================== TEST_%s =========================",TEST_TITLE);
set_sensor_io_width(
num_sensor, // input [1:0] num_sensor;
FULL_WIDTH); // Or use 0 for sensor-generated HACT input [15:0] width; // 0 - use HACT, >0 - generate HACT from start to specified width
0); // FULL_WIDTH); // Or use 0 for sensor-generated HACT input [15:0] width; // 0 - use HACT, >0 - generate HACT from start to specified width
set_sensor_io_ctl (
num_sensor, // input [1:0] num_sensor;
......
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