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Commit 500cf616 authored by Andrey Filippov's avatar Andrey Filippov
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fixed axi simulation modules, added IRQ support

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.project
View file @ 500cf616
......@@ -62,52 +62,52 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160313162251081.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160316003619053.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160313162251081.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160316003619053.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160313162251081.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160316003619053.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160313162251081.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160316003619053.log</location>
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<link>
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<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160313162251081.log</location>
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<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160313162251081.log</location>
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</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160313161825094.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160316003135844.log</location>
</link>
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<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160313162251081.log</location>
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<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160313161825094.log</location>
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</link>
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<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
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<link>
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......@@ -127,7 +127,7 @@
<link>
<name>vivado_state/x393-synth.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20160313161825094.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20160316003135844.dcp</location>
</link>
</linkedResources>
</projectDescription>
axi/cmprs_afi_mux_ptr_wresp.v
View file @ 500cf616
......@@ -67,7 +67,6 @@ module cmprs_afi_mux_ptr_wresp(
reg [26:0] len_ram[0:3]; // start chunk/num cunks in a buffer (write port @mclk)
reg [26:0] chunk_ptr_inc; // incremented by 1..4 chunk pointer
reg [27:0] chunk_ptr_rovr; // incremented chunk pointer, decremented by length (MSB - sign)
/// reg [ 3:0] busy; // one-hot busy stages (usually end with [3]
reg [ 4:0] busy; // one-hot busy stages (usually end with [4]
reg [ 4:0] id_r; // registered ID data - MSB is unused
......@@ -88,14 +87,9 @@ module cmprs_afi_mux_ptr_wresp(
assign ptr_wa = {eof,chn}; // valid @busy[2]
assign afi_bready = afi_bready_r;
/// assign pre_we= resetting[0] || // a pair of cycles to reset chunk pointer and frame chunk pointer
/// busy[2] || // always update chunk pointer
/// (busy[3] && last_burst_in_frame); // optionally update frame chunk pointer (same value)
assign pre_we= resetting[0] || // a pair of cycles to reset chunk pointer and frame chunk pointer
busy[3] || // always update chunk pointer
(busy[4] && last_burst_in_frame); // optionally update frame chunk pointer (same value)
/// assign pre_busy= afi_bvalid_r && en && !(|busy[1:0]) && !pre_we;
/// assign start_resetting_w = !afi_bvalid_r && en && !(|busy[1:0]) && !pre_we && (|reset_rq);
assign pre_busy= afi_bvalid_r && en && !(|busy[2:0]) && !pre_we;
assign start_resetting_w = !afi_bvalid_r && en && !(|busy[2:0]) && !pre_we && (|reset_rq);
......@@ -108,11 +102,10 @@ module cmprs_afi_mux_ptr_wresp(
afi_bvalid_r <= afi_bvalid;
afi_bready_r <= !en || pre_busy; // (!busy[0] && !pre_busy && !resetting[0] && !start_resetting_w);
// busy <= {busy[2:0], pre_busy}; // adjust bits
busy <= {busy[3:0], pre_busy}; // adjust bits
// id_r <= afi_bid[4:0]; // id_r[5] is never used - revoved
if (afi_bready && afi_bvalid) id_r <= afi_bid[4:0]; // id_r[5] is never used - revoved
// if (afi_bready && afi_bvalid) id_r <= afi_bid[4:0]; // id_r[5] is never used - revoved
if (afi_bvalid && pre_busy) id_r <= afi_bid[4:0]; // id_r[5] is never used - revoved
if (start_resetting_w) reset_rq_pri <= {reset_rq[3] & ~(|reset_rq[2:0]),
reset_rq[2] & ~(|reset_rq[1:0]),
......@@ -126,10 +119,8 @@ module cmprs_afi_mux_ptr_wresp(
else resetting <= {resetting[0], start_resetting_w | (resetting[0] & ~resetting[1])};
if (resetting == 2'b01) chn <= reset_rq_enc;
/// else if (busy[0]) chn <= id_r[0 +: 2];
else if (busy[1]) chn <= id_r[0 +: 2];
/// if (busy[0]) begin // first busy cycle
if (busy[1]) begin // first busy cycle
last_burst_in_frame <= id_r[2];
chunk_inc <= {1'b0,id_r[3 +:2]} + 1;
......@@ -140,9 +131,6 @@ module cmprs_afi_mux_ptr_wresp(
if ((resetting == 2'b01) || busy[0]) eof <= 0;
else if (ptr_we) eof <= 1; // always second write cycle
// @@@ delay by 1 clk
/// if (busy[1]) chunk_ptr_inc <= ptr_ram[ptr_wa] + chunk_inc; // second clock of busy
/// if (busy[2]) chunk_ptr_rovr <={1'b0,chunk_ptr_inc} - {1'b0,len_ram[chn]}; // third clock of busy
if (busy[2]) chunk_ptr_inc <= ptr_ram[ptr_wa] + chunk_inc; // second clock of busy
if (busy[3]) chunk_ptr_rovr <={1'b0,chunk_ptr_inc} - {1'b0,len_ram[chn]}; // third clock of busy
......
compressor_jp/cmprs_status.v
View file @ 500cf616
......@@ -34,25 +34,42 @@
`timescale 1ns/1ps
module cmprs_status(
input mrst,
input mclk, // system clock
input eof_written,
input stuffer_running,
input reading_frame,
output [2:0] status
input set_interrupts,
input [1:0] data_in,
output [4:0] status,
output irq
);
reg stuffer_running_r;
reg flushing_fifo;
reg is_r; // interrupt status (not masked)
reg im_r; // interrupt mask
assign status = {flushing_fifo, stuffer_running_r, reading_frame};
assign status = {flushing_fifo,
stuffer_running_r,
reading_frame,
im_r, is_r};
assign irq = is_r && im_r;
always @(posedge mclk) begin
if (mrst) im_r <= 0;
else if (set_interrupts && data_in[1]) im_r <= data_in[0];
if (mrst) is_r <= 0;
else if (eof_written) is_r <= 1;
else if (set_interrupts && (data_in == 1)) is_r <= 0;
stuffer_running_r <= stuffer_running;
if (stuffer_running_r && !stuffer_running) flushing_fifo <= 1;
else if (eof_written) flushing_fifo <= 0;
end
endmodule
compressor_jp/compressor393.v
View file @ 500cf616
......@@ -54,6 +54,7 @@ module compressor393 # (
parameter CMPRS_FORMAT= 2,
parameter CMPRS_COLOR_SATURATION= 3,
parameter CMPRS_CORING_MODE= 4,
parameter CMPRS_INTERRUPTS= 5,
parameter CMPRS_TABLES= 6, // 6..7
parameter TABLE_QUANTIZATION_INDEX = 0,
parameter TABLE_CORING_INDEX = 1,
......@@ -141,12 +142,13 @@ module compressor393 # (
input hrst, // @posedge hclk, sync reset
// programming interface
input mclk, // global system/memory clock
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
output status_rq, // input request to send status downstream
input status_start, // Acknowledge of the first status packet byte (address)
input mclk, // global system/memory clock
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
output status_rq, // input request to send status downstream
input status_start, // Acknowledge of the first status packet byte (address)
output [3:0] cmprs_irq, // Compressor done interruupt
// Buffer interfaces, combined for 4 channels
input [3:0] xfer_reset_page_rd, // from mcntrl_tiled_rw (
......@@ -280,7 +282,6 @@ module compressor393 # (
wire [3:0] flush_hclk; // before last data was written
wire [31:0] fifo_count;
/* Instance template for module status_router8 */
status_router8 status_router8_i (
.rst (1'b0), //rst), // input
.clk (mclk), // input
......@@ -339,6 +340,7 @@ module compressor393 # (
.CMPRS_FORMAT (CMPRS_FORMAT),
.CMPRS_COLOR_SATURATION (CMPRS_COLOR_SATURATION),
.CMPRS_CORING_MODE (CMPRS_CORING_MODE),
.CMPRS_INTERRUPTS (CMPRS_INTERRUPTS),
.CMPRS_TABLES (CMPRS_TABLES),
.TABLE_QUANTIZATION_INDEX (TABLE_QUANTIZATION_INDEX),
.TABLE_CORING_INDEX (TABLE_CORING_INDEX),
......@@ -414,6 +416,7 @@ module compressor393 # (
.status_ad (status_ad_mux[8 * i +: 8]), // output[7:0]
.status_rq (status_rq_mux[i]), // output
.status_start (status_start_mux[i]), // input
.irq (cmprs_irq[i]), // output
.xfer_reset_page_rd (xfer_reset_page_rd[i]), // input
.buf_wpage_nxt (buf_wpage_nxt[i]), // input
.buf_we (buf_we[i]), // input
......
compressor_jp/jp_channel.v
View file @ 500cf616
......@@ -47,6 +47,7 @@ module jp_channel#(
parameter CMPRS_FORMAT= 2,
parameter CMPRS_COLOR_SATURATION= 3,
parameter CMPRS_CORING_MODE= 4,
parameter CMPRS_INTERRUPTS= 5,
parameter CMPRS_TABLES= 6, // 6(data)..7(address)
parameter TABLE_QUANTIZATION_INDEX = 0,
parameter TABLE_CORING_INDEX = 1,
......@@ -116,34 +117,30 @@ module jp_channel#(
`endif
)(
// input rst, // global reset
input xclk, // global clock input, compressor single clock rate
input xclk, // global clock input, compressor single clock rate
`ifdef USE_XCLK2X
input xclk2x, // global clock input, compressor double clock rate, nominally rising edge aligned
input xclk2x, // global clock input, compressor double clock rate, nominally rising edge aligned
`endif
input mrst, // @posedge mclk, sync reset
input xrst, // @posedge xclk, sync reset
input hrst, // @posedge xclk, sync reset
input mrst, // @posedge mclk, sync reset
input xrst, // @posedge xclk, sync reset
input hrst, // @posedge xclk, sync reset
// programming interface
input mclk, // global system/memory clock
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
output status_rq, // input request to send status downstream
input status_start, // Acknowledge of the first status packet byte (address)
input mclk, // global system/memory clock
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
output status_rq, // input request to send status downstream
input status_start, // Acknowledge of the first status packet byte (address)
output irq, // processor interrupt
// Buffer interface (buffer to be a part of the memory controller - it is connected there by a 64-bit data, here - by an 9-bit one
input xfer_reset_page_rd, // from mcntrl_tiled_rw (
input buf_wpage_nxt, // advance to next page memory interface writes to
input buf_we, // @!mclk write buffer from memory, increment write
input [63:0] buf_din, // data out
input buf_we, // @!mclk write buffer from memory, increment write
input [63:0] buf_din, // data out
// output [11:0] buf_ra,
// output buf_ren,
// output buf_regen,
// input [ 7:0] buf_di,
input page_ready_chn, // single mclk (posedge)
output next_page_chn, // single mclk (posedge): Done with the page in the buffer, memory controller may read more data
......@@ -186,8 +183,8 @@ module jp_channel#(
input fifo_rst, // reset FIFO (set read address to write, reset count)
input fifo_ren,
output [63:0] fifo_rdata,
output fifo_eof, // single rclk pulse signalling EOF
input eof_written, // confirm frame written ofer AFI to the system memory (single rclk pulse)
output fifo_eof, // single rclk pulse signaling EOF
input eof_written, // confirm frame written over AFI to the system memory (single rclk pulse)
output fifo_flush, // EOF, need to output all what is in FIFO (Stays active until enough data chunks are read)
output flush_hclk, // output before writing last chunk - use it to suspend AFI to have
// last burst marked as the last one (otherwise last may be empty if frame had %4==0 chunks)
......@@ -313,16 +310,9 @@ module jp_channel#(
wire enc_dv;
//TODO: use next signals for status
// wire eof_written_mclk;
// wire stuffer_done_mclk;
wire stuffer_running_mclk;
wire reading_frame;
/// wire last_block; //huffman393
/// wire test_lbw;
`ifdef USE_XCLK2X
wire [15:0] huff_do; // output[15:0] reg
wire [3:0] huff_dl; // output[3:0] reg
......@@ -342,6 +332,7 @@ module jp_channel#(
wire set_format_w;
wire set_color_saturation_w;
wire set_coring_w;
wire set_interrupts_w;
wire set_tables_w;
wire stuffer_running; // @negedge xclk2x from registering timestamp until done
......@@ -352,6 +343,7 @@ module jp_channel#(
wire [ 2:0] cmprs_qpage;
wire [ 2:0] coring_num;
reg dcc_en;
wire [15:0] dccdata; // was not used in late nc353
wire dccvld; // was not used in late nc353
......@@ -361,8 +353,10 @@ module jp_channel#(
assign set_format_w = cmd_we && (cmd_a== CMPRS_FORMAT);
assign set_color_saturation_w = cmd_we && (cmd_a== CMPRS_COLOR_SATURATION);
assign set_coring_w = cmd_we && (cmd_a== CMPRS_CORING_MODE);
assign set_interrupts_w = cmd_we && (cmd_a== CMPRS_INTERRUPTS);
assign set_tables_w = cmd_we && ((cmd_a & 6)== CMPRS_TABLES);
`ifdef USE_XCLK2X
// re-sync to posedge xclk2x
reg xrst2xn;
......@@ -586,31 +580,36 @@ module jp_channel#(
.data (cmd_data), // output[31:0]
.we (cmd_we) // output
);
wire [2:0] status_data;
wire [4:0] status_data;
cmprs_status cmprs_status_i (
.mclk (mclk), // input
.eof_written (eof_written_mclk), // input
.stuffer_running (stuffer_running_mclk), // input
.reading_frame (reading_frame), // input
.status (status_data) // output[2:0]
.mrst (mrst), // input
.mclk (mclk), // input
.eof_written (eof_written_mclk), // input
.stuffer_running (stuffer_running_mclk), // input
.reading_frame (reading_frame), // input
.set_interrupts (set_interrupts_w), // input
.data_in (cmd_data[1:0]), // input[1:0]
.status (status_data), // output[2:0]
.irq (irq) // output
);
status_generate #(
.STATUS_REG_ADDR (CMPRS_STATUS_REG_ADDR),
.PAYLOAD_BITS (3),
.PAYLOAD_BITS (7),
.EXTRA_WORDS (1),
.EXTRA_REG_ADDR (CMPRS_HIFREQ_REG_ADDR)
) status_generate_i (
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (set_status_w), // input
.wd (cmd_data[7:0]), // input[7:0]
.status ({hifreq,status_data}), // input[2:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (set_status_w), // input
.wd (cmd_data[7:0]), // input[7:0]
.status ({hifreq,status_data,2'b0}), // input[2:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
);
//hifreq
// Not needed?
......
fpga_version.vh
View file @ 500cf616
......@@ -31,7 +31,9 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
parameter FPGA_VERSION = 32'h03930071; // Fixing AXI HP multiplexer xclk -0.083 -1.968 44 / 15163 (77.17%)
parameter FPGA_VERSION = 32'h03930073; // Adding interrupts support
// parameter FPGA_VERSION = 32'h03930072; // Adding hact monitor bit 77.9%, failed timing
// parameter FPGA_VERSION = 32'h03930071; // Fixing AXI HP multiplexer xclk -0.083 -1.968 44 / 15163 (77.17%)
// parameter FPGA_VERSION = 32'h03930070; // Fixing HiSPi xclk -0.049 -0.291 17, utilization 15139 (77.04%)
// parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xcl -0.002 -0.004 2, utilization 15144 (77.07 %)
// parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xclk -0.209/-2.744/23, utilization 15127 (76.98%)
......
includes/x393_parameters.vh
View file @ 500cf616
......@@ -633,6 +633,7 @@
parameter CMPRS_FORMAT= 2,
parameter CMPRS_COLOR_SATURATION= 3,
parameter CMPRS_CORING_MODE= 4,
parameter CMPRS_INTERRUPTS= 5,
parameter CMPRS_TABLES= 6, // 6..7
parameter TABLE_QUANTIZATION_INDEX = 0,
parameter TABLE_CORING_INDEX = 1,
......@@ -762,6 +763,7 @@
parameter CMDFRAMESEQ_CTRL = 31,
parameter CMDFRAMESEQ_RST_BIT = 14,
parameter CMDFRAMESEQ_RUN_BIT = 13,
parameter CMDFRAMESEQ_IRQ_BIT = 0,
parameter CMDSEQMUX_ADDR = 'h702, // only status control
parameter CMDSEQMUX_MASK = 'h7ff,
......
py393/dbg/x393_mcntrl.pickle
View file @ 500cf616
This diff is collapsed.
py393/x393_jpeg.py
View file @ 500cf616
......@@ -965,12 +965,89 @@ class X393Jpeg(object):
ff d9
"""
"""
cd /usr/local/verilog/; test_mcntrl.py @hargs
measure_all "*DI"
setup_all_sensors True None 0xf
#write_sensor_i2c 0 1 0 0x30700101
compressor_control all None None None None None 2
program_gamma all 0 0.57 0.04
write_sensor_i2c 0 1 0 0x030600b4
write_sensor_i2c 0 1 0 0x31c68400
write_sensor_i2c 0 1 0 0x306e9280
#write_sensor_i2c 0 1 0 0x30700002
write_sensor_i2c 0 1 0 0x301a001c
print_sensor_i2c 0 0x31c6 0xff 0x10 0
compressor_control 0 2
jpeg_write "img.jpeg" 0
jpeg_acquire_write
write_sensor_i2c 0 1 0 0x30700000
-------
setup_all_sensors True None 0xf
write_sensor_i2c 0 1 0 0x30700101
compressor_control all None None None None None 2
program_gamma all 0 0.57 0.04
write_sensor_i2c 0 1 0 0x030600b4
print_sensor_i2c 0 0x306 0xff 0x10 0
print_sensor_i2c 0 0x303a 0xff 0x10 0
print_sensor_i2c 0 0x301a 0xff 0x10 0
print_sensor_i2c 0 0x31c6 0xff 0x10 0
write_sensor_i2c 0 1 0 0x31c68400
print_sensor_i2c 0 0x31c6 0xff 0x10 0
print_sensor_i2c 0 0x306e 0xff 0x10 0
write_sensor_i2c 0 1 0 0x306e9280
write_sensor_i2c 0 1 0 0x30700002
write_sensor_i2c 0 1 0 0x301a001c
print_sensor_i2c 0 0x31c6 0xff 0x10 0
compressor_control 0 2
x393 +0.001s--> jpeg_write "img.jpeg" 0
http://192.168.0.7/imgsrv.py?y_quality=85&gamma=0.5&verbose=0&cmode=jpeg&bayer=2&expos=3000&flip_x=1&flip_y=1
JP46: demuxing...
Corrupt JPEG data: bad Huffman code
Corrupt JPEG data: bad Huffman code
Corrupt JPEG data: bad Huffman code
def jpeg_acquire_write(self,
file_path = "img.jpeg",
channel = 0,
cmode = None, # vrlg.CMPRS_CBIT_CMODE_JPEG18, # read it from the saved
bayer = None,
y_quality = None,
c_quality = None,
portrait = None,
gamma = None, # 0.57,
black = None, # 0.04,
colorsat_blue = None, # 2.0, colorsat_blue, #0x180 # 0x90 for 1x
colorsat_red = None, # 2.0, colorsat_red, #0x16c, # 0xb6 for x1
server_root = "/www/pages/",
verbose = 1):
def print_sensor_i2c (self,
num_sensor,
reg_addr,
indx = 1,
sa7 = 0x48,
verbose = 1):
Read sequence of bytes available and print the result as a single hex number
@param num_sensor - sensor port number (0..3), or "all" - same to all sensors
@param reg_addr - register to read address 1/2 bytes (defined by previously set format)
@param indx - i2c command index in 1 256-entry table (defines here i2c delay, number of address bytes and number of data bytes)
@param sa7 - 7-bit i2c slave address
@param verbose - verbose level
print_sensor_i2c 0 0x306 0xff 0x10 0
#should be no MSB first (0x31c68400)
cd /usr/local/verilog/; test_mcntrl.py @hargs
......
py393/x393_sensor.py
View file @ 500cf616
......@@ -128,7 +128,8 @@ class X393Sensor(object):
"""
status= self.get_status_sensor_io(num_sensor)
print ("print_status_sensor_io(%d):"%(num_sensor))
#last_in_line_1cyc_mclk, dout_valid_1cyc_mclk
#last_in_line_1cyc_mclk, dout_valid_1cyc_mclk
"""
print (" last_in_line_1cyc_mclk = %d"%((status>>23) & 1))
print (" dout_valid_1cyc_mclk = %d"%((status>>22) & 1))
print (" alive_hist0_gr = %d"%((status>>21) & 1))
......@@ -140,10 +141,13 @@ class X393Sensor(object):
print (" vact_alive = %d"%((status>>15) & 1))
print (" hact_ext_alive = %d"%((status>>14) & 1))
print (" hact_alive = %d"%((status>>13) & 1))
"""
print (" hact_run = %d"%((status>>13) & 1))
print (" locked_pxd_mmcm = %d"%((status>>12) & 1))
print (" clkin_pxd_stopped_mmcm = %d"%((status>>11) & 1))
print (" clkfb_pxd_stopped_mmcm = %d"%((status>>10) & 1))
print (" ps_rdy = %d"%((status>> 9) & 1))
print (" xfpgadone = %d"%((status>> 9) & 1))
print (" ps_rdy = %d"%((status>> 8) & 1))
print (" ps_out = %d"%((status>> 0) & 0xff))
print (" xfpgatdo = %d"%((status>>25) & 1))
print (" senspgmin = %d"%((status>>24) & 1))
......@@ -787,6 +791,43 @@ class X393Sensor(object):
self.x393_axi_tasks.write_control_register(reg_addr + 3, dlys[3]) # {mmcm_phase, bpf, vact, hact}
self.set_sensor_io_ctl (num_sensor = num_sensor,
set_delays = True)
def set_sensor_io_dly_hispi (self,
num_sensor,
mmcm_phase = None,
lane0_dly = None,
lane1_dly = None,
lane2_dly = None,
lane3_dly = None):
"""
Set sensor port input delays and mmcm phase
@param num_sensor - sensor port number (0..3) or all, 'A'
@param mmcm_phase - MMCM clock phase
@param lane0_dly - delay in the lane0 (3 LSB are not used) // All 4 lane delays should be set simultaneously
@param lane1_dly - delay in the lane1 (3 LSB are not used)
@param lane2_dly - delay in the lane2 (3 LSB are not used)
@param lane3_dly - delay in the lane3 (3 LSB are not used))
"""
try:
if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
for num_sensor in range(4):
self.set_sensor_io_dly_hispi (num_sensor = num_sensor,
mmcm_phase = mmcm_phase,
lane0_dly = lane0_dly,
lane1_dly = lane1_dly,
lane2_dly = lane2_dly,
lane3_dly = lane3_dly)
return
except:
pass
reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + vrlg.SENSIO_RADDR + vrlg.SENSIO_DELAYS
try: # if any delay is None - do not set
dlys=(lane0_dly & 0xff) | ((lane1_dly & 0xff) << 8) | ((lane2_dly & 0xff) << 16) | ((lane3_dly & 0xff) << 24)
self.x393_axi_tasks.write_control_register(reg_addr + 2, dlys)
except:
pass
if not mmcm_phase is None:
self.x393_axi_tasks.write_control_register(reg_addr + 3, mmcm_phase & 0xff)
def set_sensor_hispi_lanes(self,
num_sensor,
......
sensor/sens_10398.v
View file @ 500cf616
......@@ -204,6 +204,9 @@ module sens_10398 #(
reg [ PXD_CLK_DIV_BITS-1:0] pxd_clk_cntr;
reg [1:0] prst_with_sens_mrst = 2'h3; // prst extended to include sensor reset and rst_mmcm
wire async_prst_with_sens_mrst = ~imrst | rst_mmcm; // mclk domain
reg hact_r;
wire hact_mclk;
reg hact_alive;
assign status = { locked_pxd_mmcm,
clkin_pxd_stopped_mmcm, clkfb_pxd_stopped_mmcm, xfpgadone,
......@@ -277,6 +280,10 @@ module sens_10398 #(
if (mrst) gp_r[1] <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_GP1 + 1]) gp_r[1] <= data_r[SENS_CTRL_GP1];
if (mrst || set_iclk_phase || set_idelays) hact_alive <= 0;
else if (hact_mclk) hact_alive <= 1;
end
......@@ -294,6 +301,8 @@ module sens_10398 #(
if (async_prst_with_sens_mrst) prst_with_sens_mrst <= 2'h3;
else if (prst) prst_with_sens_mrst <= 2'h3;
else prst_with_sens_mrst <= prst_with_sens_mrst >> 1;
hact_r <= hact;
end
cmd_deser #(
......@@ -315,7 +324,7 @@ module sens_10398 #(
status_generate #(
.STATUS_REG_ADDR(SENSIO_STATUS_REG),
.PAYLOAD_BITS(15) // +3) // +STATUS_ALIVE_WIDTH) // STATUS_PAYLOAD_BITS)
.PAYLOAD_BITS(15+1) // +3) // +STATUS_ALIVE_WIDTH) // STATUS_PAYLOAD_BITS)
) status_generate_sens_io_i (
.rst (1'b0), // rst), // input
.clk (mclk), // input
......@@ -323,7 +332,7 @@ module sens_10398 #(
.we (set_status_r), // input
.wd (data_r[7:0]), // input[7:0]
// .status ({status_alive,status}), // input[25:0]
.status (status), // input[25:0]
.status ({hact_alive,status}), // input[15:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
......@@ -534,6 +543,17 @@ module sens_10398 #(
.O(xfpgadone), // output
.I(sns_shutter_done) // input
);
// just to verify hact is active
pulse_cross_clock hact_mclk_i (
.rst (1'b0), // input
.src_clk (pclk), // input
.dst_clk (mclk), // input
.in_pulse (hact && !hact_r), // input
.out_pulse (hact_mclk), // output
.busy() // output
);
endmodule
simulation_modules/simul_axi_hp_rd.v
View file @ 500cf616
......@@ -271,38 +271,40 @@ module simul_axi_hp_rd #(
fifo_same_clock_fill #( .DATA_WIDTH(50),.DATA_DEPTH(2)) // read - 4, write - 32?
raddr_i (
.rst (rst),
.clk (aclk),
.sync_rst (1'b0),
.we (arvalid && arready),
.re (start_read_burst_w),
.data_in ({arid[5:0], arburst[1:0], arsize[1:0], arlen[3:0], araddr[31:0], rd_qos_in[3:0]}),
.data_out ({arid_out[5:0], arburst_out[1:0],arsize_out[1:0],arlen_out[3:0],araddr_out[31:0], rd_qos_out[3:0]}),
.nempty (ar_nempty),
.half_full (), //aw_half_full),
.under (), //waddr_under), // output reg
.over (), //waddr_over), // output reg
.wcount (), //waddr_wcount), // output[3:0] reg
.rcount (), //waddr_rcount), // output[3:0] reg
.num_in_fifo(racount) // output[3:0]
.rst (rst),
.clk (aclk),
.sync_rst (1'b0),
.we (arvalid && arready),
.re (start_read_burst_w),
.data_in ({arid[5:0], arburst[1:0], arsize[1:0], arlen[3:0], araddr[31:0], rd_qos_in[3:0]}),
.data_out ({arid_out[5:0], arburst_out[1:0],arsize_out[1:0],arlen_out[3:0],araddr_out[31:0], rd_qos_out[3:0]}),
.nempty (ar_nempty),
.half_full (), //aw_half_full),
.under (), //waddr_under), // output reg
.over (), //waddr_over), // output reg
.wcount (), //waddr_wcount), // output[3:0] reg
.rcount (), //waddr_rcount), // output[3:0] reg
.wnum_in_fifo (racount), // output[3:0]
.rnum_in_fifo () // output[3:0]
);
fifo_same_clock_fill #( .DATA_WIDTH(73),.DATA_DEPTH(7)) // read - 4, write - 32?
rdata_i (
.rst (rst),
.clk (aclk),
.sync_rst (1'b0),
.we (sim_rd_valid && sim_rd_ready),
.re (rvalid && rready),
.data_in ({last_read, arid_out[5:0], sim_rd_resp[1:0], sim_rd_data[63:0]}),
.data_out ({rlast, rid[5:0], rresp[1:0], rdata[63:0]}),
.nempty (r_nempty), //r_nempty),
.half_full (), //aw_half_full),
.under (), //waddr_under),
.over (), //waddr_over),
.wcount (), //waddr_wcount),
.rcount (), //waddr_rcount),
.num_in_fifo(rcount)
.rst (rst),
.clk (aclk),
.sync_rst (1'b0),
.we (sim_rd_valid && sim_rd_ready),
.re (rvalid && rready),
.data_in ({last_read, arid_out[5:0], sim_rd_resp[1:0], sim_rd_data[63:0]}),
.data_out ({rlast, rid[5:0], rresp[1:0], rdata[63:0]}),
.nempty (r_nempty), //r_nempty),
.half_full (), //aw_half_full),
.under (), //waddr_under),
.over (), //waddr_over),
.wcount (), //waddr_wcount),
.rcount (), //waddr_rcount),
.wnum_in_fifo (),
.rnum_in_fifo (rcount)
);
......
simulation_modules/simul_axi_hp_wr.v
View file @ 500cf616
......@@ -104,6 +104,8 @@ Solved it!
To make it work, I set the (AR/AW)CACHE=0x11 and (AR/AW)PROT=0x00. In the CDMA datasheet, these were the recommended values, which I confirmed with ChipScope, when attached to CDMA's master port.
The default values set by VHLS were 0x00 and 0x10 respectively, which is also the case in the last post.
Alex
UPDATE: Xilinx docs say that (AR/AW)CACHE is ignored
*/
reg [3:0] WrDataThreshold = 'hf;
......@@ -302,37 +304,39 @@ Alex
fifo_same_clock_fill #( .DATA_WIDTH(50),.DATA_DEPTH(5)) // read - 4, write - 32?
waddr_i (
.rst (rst),
.clk (aclk),
.sync_rst (1'b0),
.we (awvalid && awready),
.re (start_write_burst_w),
.data_in ({awid[5:0], awburst[1:0], awsize[1:0], awlen[3:0], awaddr[31:0], wr_qos_in[3:0]}),
.data_out ({awid_out[5:0], awburst_out[1:0],awsize_out[1:0],awlen_out[3:0],awaddr_out[31:0], wr_qos_out[3:0]}),
.nempty (aw_nempty),
.half_full (), //aw_half_full),
.under (), //waddr_under), // output reg
.over (), //waddr_over), // output reg
.wcount (), //waddr_wcount), // output[3:0] reg
.rcount (), //waddr_rcount), // output[3:0] reg
.num_in_fifo(wacount) // output[3:0]
.rst (rst),
.clk (aclk),
.sync_rst (1'b0),
.we (awvalid && awready),
.re (start_write_burst_w),
.data_in ({awid[5:0], awburst[1:0], awsize[1:0], awlen[3:0], awaddr[31:0], wr_qos_in[3:0]}),
.data_out ({awid_out[5:0], awburst_out[1:0],awsize_out[1:0],awlen_out[3:0],awaddr_out[31:0], wr_qos_out[3:0]}),
.nempty (aw_nempty),
.half_full (), //aw_half_full),
.under (), //waddr_under), // output reg
.over (), //waddr_over), // output reg
.wcount (), //waddr_wcount), // output[3:0] reg
.rcount (), //waddr_rcount), // output[3:0] reg
.wnum_in_fifo (wacount), // output[3:0]
.rnum_in_fifo () // output[3:0]
);
fifo_same_clock_fill #( .DATA_WIDTH(79),.DATA_DEPTH(7))
wdata_i (
.rst(rst),
.clk(aclk),
.sync_rst (1'b0),
.we(wvalid && wready),
.re(fifo_wd_rd), //start_write_burst_w), // wrong
.data_in({wlast, wid[5:0], wstrb[7:0], wdata[63:0]}),
.data_out({wlast_out,wid_out[5:0], wstrb_out[7:0], wdata_out[63:0]}),
.nempty(w_nempty),
.half_full(), //w_half_full),
.under (), //wdata_under), // output reg
.over (), //wdata_over), // output reg
.wcount (), //wdata_wcount), // output[3:0] reg
.rcount (), //wdata_rcount), // output[3:0] reg
.num_in_fifo(wcount) // output[3:0]
.rst (rst),
.clk (aclk),
.sync_rst (1'b0),
.we (wvalid && wready),
.re (fifo_wd_rd), //start_write_burst_w), // wrong
.data_in ({wlast, wid[5:0], wstrb[7:0], wdata[63:0]}),
.data_out ({wlast_out,wid_out[5:0], wstrb_out[7:0], wdata_out[63:0]}),
.nempty (w_nempty),
.half_full (), //w_half_full),
.under (), //wdata_under), // output reg
.over (), //wdata_over), // output reg
.wcount (), //wdata_wcount), // output[3:0] reg
.rcount (), //wdata_rcount), // output[3:0] reg
.wnum_in_fifo (wcount), // output[3:0]
.rnum_in_fifo () // output[3:0]
);
// **** Write response channel ****
wire [ 1:0] bresp_value=2'b0;
......@@ -346,31 +350,32 @@ fifo_same_clock_fill #( .DATA_WIDTH(79),.DATA_DEPTH(7))
dly_16 #(
.WIDTH(1)
) bresp_dly_16_i (
.clk(aclk), // input
.rst(rst), // input
.dly(sim_bresp_latency[3:0]), // input[3:0]
.din(last_confirmed_write), //fifo_wd_rd), // input[0:0]
.dout(fifo_wd_rd_dly) // output[0:0]
.clk (aclk), // input
.rst (rst), // input
.dly (sim_bresp_latency[3:0]), // input[3:0]
.din (last_confirmed_write), //fifo_wd_rd), // input[0:0]
.dout (fifo_wd_rd_dly) // output[0:0]
);
// first FIFO for bresp - latency outside of the module
// wresp per burst, not per item !
fifo_same_clock_fill #( .DATA_WIDTH(8),.DATA_DEPTH(5))
wresp_ext_i (
.rst(rst),
.clk(aclk),
.sync_rst (1'b0),
.we(last_confirmed_write), // fifo_wd_rd),
.re(fifo_wd_rd_dly), // not allowing RE next cycle after bvalid
.data_in({wid_out[5:0],bresp_value[1:0]}),
.data_out({bid_in[5:0],bresp_in[1:0]}),
.nempty(),
.half_full(), //),
.under (), //wresp_under), // output reg
.over (), //wresp_over), // output reg
.wcount (), //wresp_wcount), // output[3:0] reg
.rcount (), //wresp_rcount), // output[3:0] reg
.num_in_fifo() // wresp_num_in_fifo) // output[3:0]
.rst (rst),
.clk (aclk),
.sync_rst (1'b0),
.we (last_confirmed_write), // fifo_wd_rd),
.re (fifo_wd_rd_dly), // not allowing RE next cycle after bvalid
.data_in ({wid_out[5:0],bresp_value[1:0]}),
.data_out ({bid_in[5:0],bresp_in[1:0]}),
.nempty (),
.half_full (), //),
.under (), //wresp_under), // output reg
.over (), //wresp_over), // output reg
.wcount (), //wresp_wcount), // output[3:0] reg
.rcount (), //wresp_rcount), // output[3:0] reg
.wnum_in_fifo (), // wresp_num_in_fifo) // output[3:0]
.rnum_in_fifo () // wresp_num_in_fifo) // output[3:0]
);
assign wresp_re=bready && bvalid; // && !was_wresp_re;
......@@ -382,20 +387,21 @@ fifo_same_clock_fill #( .DATA_WIDTH(8),.DATA_DEPTH(5))
// second wresp FIFO (does it exist in the actual module)?
fifo_same_clock_fill #( .DATA_WIDTH(8),.DATA_DEPTH(5))
wresp_i (
.rst(rst),
.clk(aclk),
.sync_rst (1'b0),
.we(fifo_wd_rd_dly),
.re(wresp_re), // not allowing RE next cycle after bvalid
.data_in({bid_in[5:0],bresp_in[1:0]}),
.data_out({bid[5:0],bresp[1:0]}),
.nempty(), //bvalid),
.half_full(), //),
.under (), //wresp_under), // output reg
.over (), //wresp_over), // output reg
.wcount (), //wresp_wcount), // output[3:0] reg
.rcount (), //wresp_rcount), // output[3:0] reg
.num_in_fifo(wresp_num_in_fifo) // wresp_num_in_fifo) // output[3:0]
.rst (rst),
.clk (aclk),
.sync_rst (1'b0),
.we (fifo_wd_rd_dly),
.re (wresp_re), // not allowing RE next cycle after bvalid
.data_in ({bid_in[5:0],bresp_in[1:0]}),
.data_out ({bid[5:0],bresp[1:0]}),
.nempty (), //bvalid),
.half_full (), //),
.under (), //wresp_under), // output reg
.over (), //wresp_over), // output reg
.wcount (), //wresp_wcount), // output[3:0] reg
.rcount (), //wresp_rcount), // output[3:0] reg
.wnum_in_fifo (), // wresp_num_in_fifo) // output[3:0]
.rnum_in_fifo (wresp_num_in_fifo) // wresp_num_in_fifo) // output[3:0]
);
endmodule
......
simulation_modules/simul_saxi_gp_wr.v
View file @ 500cf616
......@@ -256,37 +256,39 @@ Alex
fifo_same_clock_fill #( .DATA_WIDTH(50),.DATA_DEPTH(AW_FIFO_DEPTH)) // read - 4, write - 32?
waddr_i (
.rst (rst),
.clk (aclk),
.sync_rst (1'b0),
.we (awvalid && awready),
.re (start_write_burst_w),
.data_in ({awid[5:0], awburst[1:0], awsize[1:0], awlen[3:0], awaddr[31:0], awqos[3:0]}),
.data_out ({awid_out[5:0], awburst_out[1:0],awsize_out[1:0],awlen_out[3:0],awaddr_out[31:0], sim_wr_qos[3:0]}),
.nempty (aw_nempty),
.half_full (), //aw_half_full),
.under (), //waddr_under), // output reg
.over (), //waddr_over), // output reg
.wcount (), //waddr_wcount), // output[3:0] reg
.rcount (), //waddr_rcount), // output[3:0] reg
.num_in_fifo(wacount) // output[3:0]
.rst (rst),
.clk (aclk),
.sync_rst (1'b0),
.we (awvalid && awready),
.re (start_write_burst_w),
.data_in ({awid[5:0], awburst[1:0], awsize[1:0], awlen[3:0], awaddr[31:0], awqos[3:0]}),
.data_out ({awid_out[5:0], awburst_out[1:0],awsize_out[1:0],awlen_out[3:0],awaddr_out[31:0], sim_wr_qos[3:0]}),
.nempty (aw_nempty),
.half_full (), // aw_half_full),
.under (), // waddr_under), // output reg
.over (), // waddr_over), // output reg
.wcount (), // waddr_wcount), // output[3:0] reg
.rcount (), // waddr_rcount), // output[3:0] reg
.wnum_in_fifo (wacount), // output[3:0]
.rnum_in_fifo () // output[3:0]
);
fifo_same_clock_fill #( .DATA_WIDTH(43),.DATA_DEPTH(W_FIFO_DEPTH))
fifo_same_clock_fill #( .DATA_WIDTH(43), .DATA_DEPTH(W_FIFO_DEPTH))
wdata_i (
.rst(rst),
.clk(aclk),
.sync_rst (1'b0),
.we(wvalid && wready),
.re(fifo_wd_rd), //start_write_burst_w), // wrong
.data_in({wlast, wid[5:0], wstrb[3:0], wdata[31:0]}),
.data_out({wlast_out,wid_out[5:0], wstrb_out[3:0], wdata_out[31:0]}),
.nempty(w_nempty),
.half_full(), //w_half_full),
.under (), //wdata_under), // output reg
.over (), //wdata_over), // output reg
.wcount (), //wdata_wcount), // output[3:0] reg
.rcount (), //wdata_rcount), // output[3:0] reg
.num_in_fifo(wcount) // output[3:0]
.rst (rst),
.clk (aclk),
.sync_rst (1'b0),
.we (wvalid && wready),
.re (fifo_wd_rd), //start_write_burst_w), // wrong
.data_in ({wlast, wid[5:0], wstrb[3:0], wdata[31:0]}),
.data_out ({wlast_out,wid_out[5:0], wstrb_out[3:0], wdata_out[31:0]}),
.nempty (w_nempty),
.half_full (), //w_half_full),
.under (), //wdata_under), // output reg
.over (), //wdata_over), // output reg
.wcount (), //wdata_wcount), // output[3:0] reg
.rcount (), //wdata_rcount), // output[3:0] reg
.wnum_in_fifo (wcount), // output[3:0]
.rnum_in_fifo () // output[3:0]
);
// **** Write response channel ****
wire [ 1:0] bresp_value=2'b0;
......@@ -300,31 +302,32 @@ fifo_same_clock_fill #( .DATA_WIDTH(43),.DATA_DEPTH(W_FIFO_DEPTH))
dly_16 #(
.WIDTH(1)
) bresp_dly_16_i (
.clk(aclk), // input
.rst(rst), // input
.dly(sim_bresp_latency[3:0]), // input[3:0]
.clk(aclk), // input
.rst(rst), // input
.dly(sim_bresp_latency[3:0]), // input[3:0]
.din(last_confirmed_write), //fifo_wd_rd), // input[0:0]
.dout(fifo_wd_rd_dly) // output[0:0]
.dout(fifo_wd_rd_dly) // output[0:0]
);
// first FIFO for bresp - latency outside of the module
// wresp per burst, not per item !
fifo_same_clock_fill #( .DATA_WIDTH(8),.DATA_DEPTH(5))
wresp_ext_i (
.rst(rst),
.clk(aclk),
.sync_rst (1'b0),
.we(last_confirmed_write), // fifo_wd_rd),
.re(fifo_wd_rd_dly), // not allowing RE next cycle after bvalid
.data_in({wid_out[5:0],bresp_value[1:0]}),
.data_out({bid_in[5:0],bresp_in[1:0]}),
.nempty(),
.half_full(), //),
.under (), //wresp_under), // output reg
.over (), //wresp_over), // output reg
.wcount (), //wresp_wcount), // output[3:0] reg
.rcount (), //wresp_rcount), // output[3:0] reg
.num_in_fifo() // wresp_num_in_fifo) // output[3:0]
.rst (rst),
.clk (aclk),
.sync_rst (1'b0),
.we (last_confirmed_write), // fifo_wd_rd),
.re (fifo_wd_rd_dly), // not allowing RE next cycle after bvalid
.data_in ({wid_out[5:0],bresp_value[1:0]}),
.data_out ({bid_in[5:0],bresp_in[1:0]}),
.nempty (),
.half_full (), //),
.under (), //wresp_under), // output reg
.over (), //wresp_over), // output reg
.wcount (), //wresp_wcount), // output[3:0] reg
.rcount (), //wresp_rcount), // output[3:0] reg
.wnum_in_fifo (), // wresp_num_in_fifo) // output[3:0]
.rnum_in_fifo () // wresp_num_in_fifo) // output[3:0]
);
assign wresp_re=bready && bvalid; // && !was_wresp_re;
......@@ -336,20 +339,21 @@ fifo_same_clock_fill #( .DATA_WIDTH(8),.DATA_DEPTH(5))
// second wresp FIFO (does it exist in the actual module)?
fifo_same_clock_fill #( .DATA_WIDTH(8),.DATA_DEPTH(5))
wresp_i (
.rst(rst),
.clk(aclk),
.sync_rst (1'b0),
.we(fifo_wd_rd_dly),
.re(wresp_re), // not allowing RE next cycle after bvalid
.data_in({bid_in[5:0],bresp_in[1:0]}),
.data_out({bid[5:0],bresp[1:0]}),
.nempty(), //bvalid),
.half_full(), //),
.under (), //wresp_under), // output reg
.over (), //wresp_over), // output reg
.wcount (), //wresp_wcount), // output[3:0] reg
.rcount (), //wresp_rcount), // output[3:0] reg
.num_in_fifo(wresp_num_in_fifo) // wresp_num_in_fifo) // output[3:0]
.rst (rst),
.clk (aclk),
.sync_rst (1'b0),
.we (fifo_wd_rd_dly),
.re (wresp_re), // not allowing RE next cycle after bvalid
.data_in ({bid_in[5:0],bresp_in[1:0]}),
.data_out ({bid[5:0],bresp[1:0]}),
.nempty (), //bvalid),
.half_full (), //),
.under (), //wresp_under), // output reg
.over (), //wresp_over), // output reg
.wcount (), //wresp_wcount), // output[3:0] reg
.rcount (), //wresp_rcount), // output[3:0] reg
.wnum_in_fifo (), // wresp_num_in_fifo) // output[3:0]
.rnum_in_fifo (wresp_num_in_fifo) // wresp_num_in_fifo) // output[3:0]
);
endmodule
......
util_modules/cmd_frame_sequencer.v
View file @ 500cf616
......@@ -54,6 +54,8 @@
// [14] - reset all FIFO (takes 32 clock pulses), also - stops seq until run command
// [13:12] - 3 - run seq, 2 - stop seq , 1,0 - no change to run state
// New - [1:0] - 0: NOP, 1: clear IRQ, 2 - Clear IE, 3: set IE
module cmd_frame_sequencer#(
parameter CMDFRAMESEQ_ADDR= 'h780,
parameter CMDFRAMESEQ_MASK= 'h7e0,
......@@ -63,21 +65,25 @@ module cmd_frame_sequencer#(
parameter CMDFRAMESEQ_REL = 16,
parameter CMDFRAMESEQ_CTRL = 31,
parameter CMDFRAMESEQ_RST_BIT = 14,
parameter CMDFRAMESEQ_RUN_BIT = 13
parameter CMDFRAMESEQ_RUN_BIT = 13,
parameter CMDFRAMESEQ_IRQ_BIT = 0 // [1:0] used
)(
input mrst,
input mclk, // for command/status
// programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
// frame syn and frame number
// frame sync and frame number
input frame_sync, // @posedge mclk
output [ 3:0] frame_no, // @posedge mclk
// command mux interface
output [AXI_WR_ADDR_BITS-1:0] waddr, // write address, valid with wr_en_out
output valid, // output data valid
output [31:0] wdata, // write data, valid with waddr_out and wr_en_out
input ackn // command sequencer address/data accepted
input ackn, // command sequencer address/data accepted
// Interrupt mask, status, request
output is, // interrupt status (not masked)
output im // interrupt mask
);
localparam PNTR_WIDH = (CMDFRAMESEQ_DEPTH > 32) ?((CMDFRAMESEQ_DEPTH > 64) ? 7 : 6) : 5;
wire [4:0] cmd_a; // 3 cycles before data
......@@ -133,6 +139,16 @@ module cmd_frame_sequencer#(
reg valid_r;
wire [63:0] cmdseq_do; // output data from the sequence
wire [1:0] irq_bits = cmd_data[CMDFRAMESEQ_IRQ_BIT +: 2];
reg is_r; // interrupt status (not masked)
reg im_r; // interrtupt mask
wire irq_ctrl;
assign is = is_r; // interrupt status (not masked)
assign im = im_r; // interrtupt mask
assign irq_ctrl = cmd_we_ctl_r[2] && (|irq_bits);
assign waddr = cmdseq_do[32 +:AXI_WR_ADDR_BITS];
assign wdata = cmdseq_do[31:0];
assign seq_cmd_ra = {page_r,rpointer};
......@@ -152,6 +168,18 @@ module cmd_frame_sequencer#(
assign commands_pending = rpointer != fifo_wr_pointers_outr_r; // only look at the current page different pages will trigger page increment first
assign pre_cmd_seq_w = commands_pending & ~(|page_r_inc) & seq_enrun;
assign valid = valid_r;
// parameter CMDFRAMESEQ_IRQ_BIT = 0,
// parameter CMDFRAMESEQ_IRQ_BITS = 2
always @ (posedge mclk) begin
if (mrst) is_r <= 0;
else if (frame_sync) is_r <= 1;
else if (irq_ctrl && (irq_bits == 2'b01)) is_r <= 0;
if (mrst) im_r <= 0;
else if (irq_ctrl && irq_bits[1]) im_r <= irq_bits[0];
end
always @ (posedge mclk) begin
if (mrst) por <= 0;
else por <= {por[1:0], 1'b1};
......
util_modules/cmd_seq_mux.v
View file @ 500cf616
......@@ -55,24 +55,32 @@ module cmd_seq_mux#(
input wr_en0, // write enable
input [31:0] wdata0, // write data, valid with waddr_out and wr_en_out
output ackn0, // command sequencer address/data accepted
input is0, // interrupt status (not masked)
input im0, // interrupt mask
// Sensor channel 1
input [ 3:0] frame_num1, // @posedge mclk
input [AXI_WR_ADDR_BITS-1:0] waddr1, // write address, valid with wr_en_out
input wr_en1, // write enable
input [31:0] wdata1, // write data, valid with waddr_out and wr_en_out
output ackn1, // command sequencer address/data accepted
input is1, // interrupt status (not masked)
input im1, // interrupt mask
// Sensor channel 2
input [ 3:0] frame_num2, // @posedge mclk
input [AXI_WR_ADDR_BITS-1:0] waddr2, // write address, valid with wr_en_out
input wr_en2, // write enable
input [31:0] wdata2, // write data, valid with waddr_out and wr_en_out
output ackn2, // command sequencer address/data accepted
input is2, // interrupt status (not masked)
input im2, // interrupt mask
// Sensor channel 3
input [ 3:0] frame_num3, // @posedge mclk
input [AXI_WR_ADDR_BITS-1:0] waddr3, // write address, valid with wr_en_out
input wr_en3, // write enable
input [31:0] wdata3, // write data, valid with waddr_out and wr_en_out
output ackn3, // command sequencer address/data accepted
input is3, // interrupt status (not masked)
input im3, // interrupt mask
// mux output
output reg [AXI_WR_ADDR_BITS-1:0] waddr_out, // write address, valid with wr_en_out
output wr_en_out, // write enable
......@@ -89,6 +97,9 @@ module cmd_seq_mux#(
wire ackn_w; //pre-acknowledge of one of the channels
reg [3:0] ackn_r;
wire [3:0] is = {is[3], is[2], is[1], is[0]};
wire [3:0] im = {im[3], im[2], im[1], im[0]};
assign pri_one_rr = {wr_en[3] & ~(|wr_en[2:0]), wr_en[2]&~(|wr_en[1:0]), wr_en[1] & wr_en[0], wr_en[0],
wr_en[3], wr_en[2]&~(|wr_en[1:0])&wr_en[3], wr_en[1] & ~ wr_en[3] & wr_en[0], wr_en[0] & ~ wr_en[3],
wr_en[3] & ~ wr_en[2], wr_en[2], wr_en[1] & ~(|wr_en[3:2]) & wr_en[0], wr_en[0] & ~(|wr_en[3:2]),
......@@ -164,7 +175,7 @@ module cmd_seq_mux#(
status_generate #(
.STATUS_REG_ADDR (CMDSEQMUX_STATUS),
.PAYLOAD_BITS (18),
.PAYLOAD_BITS (26),
.REGISTER_STATUS (1)
) status_generate_cmd_seq_mux_i (
.rst (1'b0), //rst), // input
......@@ -172,7 +183,7 @@ module cmd_seq_mux#(
.srst (mrst), // input
.we (cmd_status), // input
.wd (cmd_data[7:0]), // input[7:0]
.status ({frame_num3, frame_num2, frame_num1, frame_num0, 2'b0}), // input[18:0] // 2 LSBs - may add "real" status
.status ({im, is, frame_num3, frame_num2, frame_num1, frame_num0, 2'b0}), // input[18:0] // 2 LSBs - may add "real" status
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
......
util_modules/fifo_same_clock_fill.v
View file @ 500cf616
......@@ -53,7 +53,8 @@ module fifo_same_clock_fill
output reg over, // overwritten
output reg [DATA_DEPTH-1:0] wcount,
output reg [DATA_DEPTH-1:0] rcount,
output [DATA_DEPTH: 0] num_in_fifo
output [DATA_DEPTH: 0] wnum_in_fifo, // number of items in FIFO on write side
output [DATA_DEPTH: 0] rnum_in_fifo // number of items in FIFO on read side
);
localparam integer DATA_2DEPTH=(1<<DATA_DEPTH)-1;
//ISExst: FF/Latch ddrc_test01.axibram_write_i.waddr_i.fill[4] has a constant value of 0 in block <ddrc_test01>. This FF/Latch will be trimmed during the optimization process.
......@@ -61,38 +62,45 @@ module fifo_same_clock_fill
//ISExst: FF/Latch ddrc_test01.axibram_write_i.wdata_i.fill[4] has a constant value of 0 in block <ddrc_test01>. This FF/Latch will be trimmed during the optimization process.
// Do not understand - why?
reg [DATA_DEPTH: 0] fill=0; // RAM fill
reg [DATA_DEPTH: 0] fifo_fill=0; // FIFO (RAM+reg) fill
reg [DATA_DEPTH: 0] wfifo_fill=0; // FIFO (RAM+reg) fill - total number in FIFO
reg [DATA_DEPTH: 0] rfifo_fill=0; // number in FIFO, ready to be read out
reg [DATA_WIDTH-1:0] inreg;
reg [DATA_WIDTH-1:0] outreg;
reg [DATA_DEPTH-1:0] ra;
reg [DATA_DEPTH-1:0] wa;
wire [DATA_DEPTH:0] next_fill;
reg wem;
wire [DATA_DEPTH:0] next_fill;
reg [1:0] wem;
wire rem;
reg out_full=0; //output register full
reg [DATA_WIDTH-1:0] ram [0:DATA_2DEPTH];
reg ram_nempty;
assign next_fill = fill[DATA_DEPTH:0]+((wem && ~rem)?1:((~wem && rem && ram_nempty)?-1:0));
assign next_fill = fill[DATA_DEPTH:0]+((wem[0] && ~rem)?1:((~wem[0] && rem && ram_nempty)?-1:0));
assign rem= ram_nempty && (re || !out_full);
assign data_out=outreg;
assign nempty=out_full;
// assign num_in_fifo=fill[DATA_DEPTH:0];
assign num_in_fifo=fifo_fill[DATA_DEPTH:0];
assign wnum_in_fifo=wfifo_fill[DATA_DEPTH:0];
assign rnum_in_fifo=rfifo_fill[DATA_DEPTH:0];
always @ (posedge clk or posedge rst) begin
if (rst) fill <= 0;
else if (sync_rst) fill <= 0;
else fill <= next_fill;
if (rst) fill <= 0;
else if (sync_rst) fill <= 0;
else fill <= next_fill;
if (rst) fifo_fill <= 0;
else if (sync_rst) fifo_fill <= 0;
else if ( we && !re) fifo_fill <= fifo_fill+1;
else if (!we && re) fifo_fill <= fifo_fill-1;
if (rst) wfifo_fill <= 0;
else if (sync_rst) wfifo_fill <= 0;
else if ( we && !re) wfifo_fill <= wfifo_fill+1;
else if (!we && re) wfifo_fill <= wfifo_fill-1;
if (rst) rfifo_fill <= 0; // pessimistic, all writes are delayed by 2
else if (sync_rst) rfifo_fill <= 0;
else if ( wem[1] && !re) rfifo_fill <= rfifo_fill+1;
else if (!wem[1] && re) rfifo_fill <= rfifo_fill-1;
if (rst) wem <= 0;
else if (sync_rst) wem <= 0;
else wem <= we;
else wem <= {wem[0], we};
if (rst) ram_nempty <= 0;
else if (sync_rst) ram_nempty <= 0;
......@@ -100,7 +108,7 @@ module fifo_same_clock_fill
if (rst) wa <= 0;
else if (sync_rst) wa <= 0;
else if (wem) wa <= wa+1;
else if (wem[0]) wa <= wa+1;
if (rst) ra <= 0;
else if (sync_rst) ra <= 0;
......@@ -123,12 +131,13 @@ module fifo_same_clock_fill
// no reset elements
always @ (posedge clk) begin
half_full <=(fill & (1<<(DATA_DEPTH-1)))!=0;
if (wem) ram[wa] <= inreg;
if (we) inreg <= data_in;
if (rem) outreg <= ram[ra];
// under <= ~we & re & ~nempty; // underrun error
// over <= we & ~re & (fill == (1<< (DATA_DEPTH-1))); // overrun error
if (wem[0]) ram[wa] <= inreg;
if (we) inreg <= data_in;
if (rem) outreg <= ram[ra];
under <= re & ~nempty; // underrun error
over <= wem & ~rem & fill[DATA_DEPTH] & ~fill[DATA_DEPTH-1]; // overrun error
over <= wem[0] & ~rem & fill[DATA_DEPTH] & ~fill[DATA_DEPTH-1]; // overrun error
end
endmodule
x393.v
View file @ 500cf616
......@@ -299,7 +299,9 @@ module x393 #(
wire [3:0] frseq_valid;
wire [127:0] frseq_wdata;
wire [3:0] frseq_ackn;
wire [3:0] frseq_is;
wire [3:0] frseq_im;
wire [3:0] frseq_irq = frseq_is & frseq_im; // frame interrupts
// parallel address/data - where higher bandwidth (single-cycle) is needed
wire [AXI_WR_ADDR_BITS-1:0] par_waddr;
......@@ -521,6 +523,9 @@ module x393 #(
// Compressor signals for interrupts generation
wire [3:0] eof_written_mclk; // output // SuppressThisWarning VEditor - (yet) unused
wire [3:0] stuffer_done_mclk; // output// SuppressThisWarning VEditor - (yet) unused
wire [3:0] cmprs_irq; // compressor done, data confirmed written to memory)
// Compressor frame synchronization
// GPIO internal signals (for camera GPIOs, not Zynq PS GPIO)
......@@ -813,7 +818,8 @@ assign axi_grst = axi_rst_pre;
.CMDFRAMESEQ_REL (CMDFRAMESEQ_REL),
.CMDFRAMESEQ_CTRL (CMDFRAMESEQ_CTRL),
.CMDFRAMESEQ_RST_BIT (CMDFRAMESEQ_RST_BIT),
.CMDFRAMESEQ_RUN_BIT (CMDFRAMESEQ_RUN_BIT)
.CMDFRAMESEQ_RUN_BIT (CMDFRAMESEQ_RUN_BIT),
.CMDFRAMESEQ_IRQ_BIT (CMDFRAMESEQ_IRQ_BIT)
) cmd_frame_sequencer_i (
.mrst (mrst), // input
.mclk (mclk), // input
......@@ -824,7 +830,10 @@ assign axi_grst = axi_rst_pre;
.waddr (frseq_waddr[i * AXI_WR_ADDR_BITS +: AXI_WR_ADDR_BITS]), // output[13:0]
.valid (frseq_valid[i]), // output
.wdata (frseq_wdata[i * 32 +: 32]), // output[31:0]
.ackn (frseq_ackn[i]) // input
.ackn (frseq_ackn[i]), // input
.is (frseq_is[i]), // output
.im (frseq_im[i]) // output
);
end
endgenerate
......@@ -848,24 +857,33 @@ assign axi_grst = axi_rst_pre;
.wr_en0 (frseq_valid[0]), // input
.wdata0 (frseq_wdata[0 * 32 +: 32]), // input[31:0]
.ackn0 (frseq_ackn[0]), // output
.is0 (frseq_is[0]), // input
.im0 (frseq_im[0]), // input
.frame_num1 (frame_num[1 * NUM_FRAME_BITS +: 4]), // input[3:0] Use 4 bits even if NUM_FRAME_BITS > 4
.waddr1 (frseq_waddr[1 * AXI_WR_ADDR_BITS +: AXI_WR_ADDR_BITS]), // input[13:0]
.wr_en1 (frseq_valid[1]), // input
.wdata1 (frseq_wdata[1 * 32 +: 32]), // input[31:0]
.ackn1 (frseq_ackn[1]), // output
.is1 (frseq_is[1]), // input
.im1 (frseq_im[1]), // input
.frame_num2 (frame_num[2 * NUM_FRAME_BITS +: 4]), // input[3:0] Use 4 bits even if NUM_FRAME_BITS > 4
.waddr2 (frseq_waddr[2 * AXI_WR_ADDR_BITS +: AXI_WR_ADDR_BITS]), // input[13:0]
.wr_en2 (frseq_valid[2]), // input
.wdata2 (frseq_wdata[2 * 32 +: 32]), // input[31:0]
.ackn2 (frseq_ackn[2]), // output
.is2 (frseq_is[2]), // input
.im2 (frseq_im[2]), // input
.frame_num3 (frame_num[3 * NUM_FRAME_BITS +: 4]), // input[3:0] Use 4 bits even if NUM_FRAME_BITS > 4
.waddr3 (frseq_waddr[3 * AXI_WR_ADDR_BITS +: AXI_WR_ADDR_BITS]), // input[13:0]
.wr_en3 (frseq_valid[3]), // input
.wdata3 (frseq_wdata[3 * 32 +: 32]), // input[31:0]
.ackn3 (frseq_ackn[3]), // output
.is3 (frseq_is[3]), // input
.im3 (frseq_im[3]), // input
.waddr_out (cseq_waddr), // output[13:0] reg
.wr_en_out (cseq_wr_en), // output
.wdata_out (cseq_wdata), // output[31:0] reg
......@@ -1905,6 +1923,7 @@ assign axi_grst = axi_rst_pre;
.status_ad (status_compressor_ad), // output[7:0]
.status_rq (status_compressor_rq), // output
.status_start (status_compressor_start), // input
.cmprs_irq (cmprs_irq[3:0]), // output[3:0]
.xfer_reset_page_rd (cmprs_xfer_reset_page_rd), // input[3:0]
.buf_wpage_nxt (cmprs_buf_wpage_nxt), // input[3:0]
......@@ -2662,7 +2681,12 @@ assign axi_grst = axi_rst_pre;
.DMA3DATYPE(), // DMAC 3 DMA Ackbowledge TYpe (completed single AXI, completed burst AXI, flush request), output
.DMA3RSTN(), // DMAC 3 RESET output (reserved, do not use), output
// Interrupt signals
.IRQF2P(), // Interrupts, OL to PS [19:0], input
.IRQF2P({4'b0,
cmprs_irq[3:0], // [15:12] Compressor done interrupts
frseq_irq[3:0], // [11: 8] Frame sync interrupts
7'b0,
1'b0 // Put SATA here
}), // Interrupts, OL to PS [19:0], input
.IRQP2F(), // Interrupts, OL to PS [28:0], output
// Event Signals
.EVENTEVENTI(), // EVENT Wake up one or both CPU from WFE state, input
......
x393_testbench03.tf
View file @ 500cf616
......@@ -1852,14 +1852,14 @@ simul_axi_master_rdaddr
.arid_in(ARID_IN[11:0]),
.araddr_in(ARADDR_IN[31:0]),
.arlen_in(ARLEN_IN[3:0]),
.arsize_in(ARSIZE_IN[2:0]),
.arsize_in(ARSIZE_IN[1:0]),
.arburst_in(ARBURST_IN[1:0]),
.arcache_in(4'b0),
.arprot_in(3'b0), // .arprot_in(2'b0),
.arid(arid[11:0]),
.araddr(araddr[31:0]),
.arlen(arlen[3:0]),
.arsize(arsize[2:0]),
.arsize(arsize[1:0]),
.arburst(arburst[1:0]),
.arcache(arcache[3:0]),
.arprot(arprot[2:0]),
......
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