- 19 Aug, 2015 1 commit
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Andrey Filippov authoredFinished simulation/testing of a single-channel acquisition/processing/compression, fixed problems with Xilinx tools to pass sythesis/implementation
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- 12 Aug, 2015 1 commit
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Andrey Filippov authored
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- 06 Aug, 2015 1 commit
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Andrey Filippov authored
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- 02 Aug, 2015 1 commit
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Andrey Filippov authored
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- 01 Aug, 2015 1 commit
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Andrey Filippov authored
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- 25 Jul, 2015 1 commit
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Andrey Filippov authored
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- 24 Jul, 2015 2 commits
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Andrey Filippov authored
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Andrey Filippov authored
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- 23 Jul, 2015 1 commit
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Andrey Filippov authored
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- 22 Jul, 2015 1 commit
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Andrey Filippov authored
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- 19 Jul, 2015 1 commit
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Andrey Filippov authored
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- 18 Mar, 2015 1 commit
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Andrey Filippov authored
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- 28 Feb, 2015 1 commit
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Andrey Filippov authored
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- 17 Feb, 2015 1 commit
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Andrey Filippov authored
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- 09 Feb, 2015 1 commit
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Andrey Filippov authored
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- 08 Feb, 2015 1 commit
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Andrey Filippov authored
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- 11 Jan, 2015 1 commit
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Andrey Filippov authored
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- 07 Jun, 2014 1 commit
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Andrey Filippov authored
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- 01 Jun, 2014 2 commits
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Andrey Filippov authored
bug fixes, implemented read pattern test, so all major DDR3 modes are tested: write and read leveling, write and read
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Andrey Filippov authored
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- 30 May, 2014 1 commit
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Andrey Filippov authored
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- 22 May, 2014 2 commits
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Andrey Filippov authored
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Andrey Filippov authored
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- 15 May, 2014 1 commit
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Andrey Filippov authored
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- 29 Apr, 2014 1 commit
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Andrey Filippov authored
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- 26 Apr, 2014 1 commit
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Andrey Filippov authored
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