Commit 25997816 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

removed empty parameter block

parent 12915a58

.project

+4 −4
Original line number Original line Diff line number Diff line
@@ -92,7 +92,7 @@ 
		<link>

		<link>

			<name>vivado_logs/VivadoSynthesis.log</name>

			<name>vivado_logs/VivadoSynthesis.log</name>

			<type>1</type>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150723191338631.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150725144518149.log</location>

		</link>

		</link>

		<link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>

			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
@@ -102,7 +102,7 @@ 
		<link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

			<type>1</type>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150723191338631.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150725144907208.log</location>

		</link>

		</link>

		<link>

		<link>

			<name>vivado_logs/VivadoTimingReportImplemented.log</name>

			<name>vivado_logs/VivadoTimingReportImplemented.log</name>
@@ -112,7 +112,7 @@ 
		<link>

		<link>

			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>

			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>

			<type>1</type>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150723191338631.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150725144518149.log</location>

		</link>

		</link>

		<link>

		<link>

			<name>vivado_state/x393-opt-phys.dcp</name>

			<name>vivado_state/x393-opt-phys.dcp</name>
@@ -132,7 +132,7 @@ 
		<link>

		<link>

			<name>vivado_state/x393-synth.dcp</name>

			<name>vivado_state/x393-synth.dcp</name>

			<type>1</type>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150723191338631.dcp</location>

			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150725144518149.dcp</location>

		</link>

		</link>

	</linkedResources>

	</linkedResources>

</projectDescription>
 
</projectDescription>

.settings/com.elphel.vdt.VivadoTimimgSummaryReportSynthesis.prefs

+2 −1
Original line number Original line Diff line number Diff line 
VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary=true

VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary=true

com.elphel.store.context.VivadoTimimgSummaryReportSynthesis=VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary<-@\#\#@->

VivadoTimimgSummaryReportSynthesis_121_DisableVivadoTimingSummary=true

com.elphel.store.context.VivadoTimimgSummaryReportSynthesis=VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary<-@\#\#@->VivadoTimimgSummaryReportSynthesis_121_DisableVivadoTimingSummary<-@\#\#@->

eclipse.preferences.version=1
 
eclipse.preferences.version=1

.settings/com.elphel.vdt.iverilog.prefs

+3 −2
Original line number Original line Diff line number Diff line 
com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->

com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_98_GTKWaveSavFile<-@\#\#@->

eclipse.preferences.version=1

eclipse.preferences.version=1

iverilog_77_Param_Exe=/usr/local/bin/iverilog

iverilog_77_Param_Exe=/usr/local/bin/iverilog

iverilog_78_VVP_Exe=/usr/local/bin/vvp

iverilog_78_VVP_Exe=/usr/local/bin/vvp

iverilog_79_GtkWave_Exe=/usr/local/bin/gtkwave

iverilog_79_GtkWave_Exe=/usr/local/bin/gtkwave

iverilog_81_TopModulesOther=glbl<-@\#\#@->

iverilog_81_TopModulesOther=glbl<-@\#\#@->

iverilog_83_ExtraFiles=glbl.v<-@\#\#@->

iverilog_83_ExtraFiles=glbl.v<-@\#\#@->

iverilog_84_IncludeDir=/home/andrey/git/x393/ddr3<-@\#\#@->/home/andrey/git/x393/includes<-@\#\#@->

iverilog_84_IncludeDir=${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->

iverilog_88_ShowNoProblem=true

iverilog_88_ShowNoProblem=true

iverilog_89_ShowNoProblem=true

iverilog_89_ShowNoProblem=true

iverilog_98_GTKWaveSavFile=393_testbench01.sav

iverilog_99_GrepFindErrWarn=error|warning|sorry
 
iverilog_99_GrepFindErrWarn=error|warning|sorry

compressor_jp/cmprs_macroblock_buf_iface.v

+1 −3
Original line number Original line Diff line number Diff line
@@ -22,9 +22,7 @@ 
 *******************************************************************************/

 *******************************************************************************/

`timescale 1ns/1ps

`timescale 1ns/1ps





module  cmprs_macroblock_buf_iface #(

module  cmprs_macroblock_buf_iface (



    )(

//    input         rst,

//    input         rst,

    input         xclk,               // global clock input, compressor single clock rate

    input         xclk,               // global clock input, compressor single clock rate