Loading .settings/com.elphel.vdt.FPGA_project.prefs +2 −2 Original line number Original line Diff line number Diff line FPGA_project_0_SimulationTopFile=x393_testbench01.tf FPGA_project_0_SimulationTopFile=x393_testbench02.tf FPGA_project_1_SimulationTopModule=x393_testbench01 FPGA_project_1_SimulationTopModule=x393_testbench02 FPGA_project_2_ImplementationTopFile=x393.v FPGA_project_2_ImplementationTopFile=x393.v FPGA_project_4_part=xc7z030fbg484-1 FPGA_project_4_part=xc7z030fbg484-1 com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@-> com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@-> Loading includes/x393_localparams.vh +6 −1 Original line number Original line Diff line number Diff line Loading @@ -118,6 +118,10 @@ localparam STATUS_PSHIFTER_RDY_MASK = 1<<STATUS_2LSB_SHFT; localparam STATUS_PSHIFTER_RDY_MASK = 1<<STATUS_2LSB_SHFT; localparam FRAME_START_ADDRESS= 'h1000; // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0) localparam FRAME_START_ADDRESS= 'h1000; // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0) localparam FRAME_START_ADDRESS_INC= 'h800; localparam FRAME_START_ADDRESS_INC= 'h800; localparam LAST_BUF_FRAME = 1; localparam CAMSYNC_DELAY = 200; localparam FRAME_FULL_WIDTH= 'h0c0; // Padded line length (8-row increment), in 8-bursts (16 bytes) localparam FRAME_FULL_WIDTH= 'h0c0; // Padded line length (8-row increment), in 8-bursts (16 bytes) // localparam AFI_LO_ADDR64= 'h4000; // start of the system memory range in 64-bit words // localparam AFI_LO_ADDR64= 'h4000; // start of the system memory range in 64-bit words Loading Loading @@ -157,3 +161,4 @@ localparam TEST_INITIAL_BURST= 4; // 3; localparam TEST_INITIAL_BURST= 4; // 3; No newline at end of file includes/x393_parameters.vh +8 −6 Original line number Original line Diff line number Diff line Loading @@ -431,7 +431,7 @@ //sensor_fifo parameters //sensor_fifo parameters parameter SENSOR_DATA_WIDTH = 12, parameter SENSOR_DATA_WIDTH = 12, parameter SENSOR_FIFO_2DEPTH = 4, parameter SENSOR_FIFO_2DEPTH = 4, parameter SENSOR_FIFO_DELAY = 4'd7, parameter SENSOR_FIFO_DELAY = 4'd5, // 7, // other parameters for histogram_saxi module // other parameters for histogram_saxi module parameter HIST_SAXI_ADDR_MASK = 'h7f0, parameter HIST_SAXI_ADDR_MASK = 'h7f0, parameter HIST_SAXI_MODE_WIDTH = 8, parameter HIST_SAXI_MODE_WIDTH = 8, Loading Loading @@ -615,11 +615,13 @@ parameter CAMSYNC_TRIG_DELAY1 = 'h5, // setup input trigger delay parameter CAMSYNC_TRIG_DELAY1 = 'h5, // setup input trigger delay parameter CAMSYNC_TRIG_DELAY2 = 'h6, // setup input trigger delay parameter CAMSYNC_TRIG_DELAY2 = 'h6, // setup input trigger delay parameter CAMSYNC_TRIG_DELAY3 = 'h7, // setup input trigger delay parameter CAMSYNC_TRIG_DELAY3 = 'h7, // setup input trigger delay parameter CAMSYNC_SNDEN_BIT = 'h1, // enable writing ts_snd_en parameter CAMSYNC_EXTERNAL_BIT = 'h3, // enable writing ts_external (0 - local timestamp in the frame header) parameter CAMSYNC_EN_BIT = 'h0, // enable module (0 - reset) parameter CAMSYNC_TRIGGERED_BIT = 'h5, // triggered mode ( 0- async) parameter CAMSYNC_SNDEN_BIT = 'h2, // enable writing ts_snd_en parameter CAMSYNC_MASTER_BIT = 'h8, // select a 2-bit master channel (master delay may be used as a flash delay) parameter CAMSYNC_EXTERNAL_BIT = 'h4, // enable writing ts_external (0 - local timestamp in the frame header) parameter CAMSYNC_CHN_EN_BIT = 'hd, // per-channel enable timestamp generation parameter CAMSYNC_TRIGGERED_BIT = 'h6, // triggered mode ( 0- async) parameter CAMSYNC_MASTER_BIT = 'h9, // select a 2-bit master channel (master delay may be used as a flash delay) parameter CAMSYNC_CHN_EN_BIT = 'he, // per-channel enable timestamp generation parameter CAMSYNC_PRE_MAGIC = 6'b110100, parameter CAMSYNC_PRE_MAGIC = 6'b110100, parameter CAMSYNC_POST_MAGIC = 6'b001101, parameter CAMSYNC_POST_MAGIC = 6'b001101, Loading includes/x393_simulation_parameters.vh +12 −10 Original line number Original line Diff line number Diff line Loading @@ -28,16 +28,16 @@ parameter SIMUL_AXI_READ_WIDTH=16, parameter SIMUL_AXI_READ_WIDTH=16, parameter MEMCLK_PERIOD = 5.0, parameter MEMCLK_PERIOD = 5.0, parameter FCLK0_PERIOD = 10.417, parameter FCLK0_PERIOD = 41.667, // 10.417, 24MHz parameter FCLK1_PERIOD = 0.0, parameter FCLK1_PERIOD = 0.0, parameter SENSOR12BITS_LLINE = 192, // 1664;// line duration in clocks // parameter SENSOR12BITS_LLINE = 192, // 1664;// line duration in clocks parameter SENSOR12BITS_NCOLS = 66, //58; //56; // 129; //128; //1288; // parameter SENSOR12BITS_NCOLS = 66, //58; //56; // 129; //128; //1288; parameter SENSOR12BITS_NROWS = 18, // 16; // 1032; // parameter SENSOR12BITS_NROWS = 18, // 16; // 1032; parameter SENSOR12BITS_NROWB = 1, // number of "blank rows" from vact to 1-st hact // parameter SENSOR12BITS_NROWB = 1, // number of "blank rows" from vact to 1-st hact parameter SENSOR12BITS_NROWA = 1, // number of "blank rows" from last hact to end of vact // parameter SENSOR12BITS_NROWA = 1, // number of "blank rows" from last hact to end of vact // parameter nAV = 24, //240; // clocks from ARO to VACT (actually from en_dclkd) // parameter nAV = 24, //240; // clocks from ARO to VACT (actually from en_dclkd) parameter SENSOR12BITS_NBPF = 20, //16; // bpf length // parameter SENSOR12BITS_NBPF = 20, //16; // bpf length parameter SENSOR12BITS_NGPL = 8, // bpf to hact parameter SENSOR12BITS_NGPL = 8, // bpf to hact parameter SENSOR12BITS_NVLO = 1, // VACT=0 in video mode (clocks) parameter SENSOR12BITS_NVLO = 1, // VACT=0 in video mode (clocks) //parameter tMD = 14; // //parameter tMD = 14; // Loading @@ -45,15 +45,17 @@ parameter SENSOR12BITS_TMD = 4, // parameter SENSOR12BITS_TMD = 4, // parameter SENSOR12BITS_TDDO = 2, // some confusion here - let's assume that it is from DCLK to Data out parameter SENSOR12BITS_TDDO = 2, // some confusion here - let's assume that it is from DCLK to Data out parameter SENSOR12BITS_TDDO1 = 5, // parameter SENSOR12BITS_TDDO1 = 5, // parameter SENSOR12BITS_TRIGDLY = 8, // delay between trigger input and start of output (VACT) in lines // parameter SENSOR12BITS_TRIGDLY = 8, // delay between trigger input and start of output (VACT) in lines parameter SENSOR12BITS_RAMP = 1, // 1 - ramp, 0 - random (now - sensor.dat) // parameter SENSOR12BITS_RAMP = 1, // 1 - ramp, 0 - random (now - sensor.dat) parameter SENSOR12BITS_NEW_BAYER = 0, // 0 - "old" tiles (16x16, 1 - new - (18x18) // parameter SENSOR12BITS_NEW_BAYER = 0, // 0 - "old" tiles (16x16, 1 - new - (18x18) parameter HISTOGRAM_LEFT = 0, //2; // left parameter HISTOGRAM_LEFT = 0, //2; // left parameter HISTOGRAM_TOP = 2, // top parameter HISTOGRAM_TOP = 2, // top parameter HISTOGRAM_WIDTH = 6, // width parameter HISTOGRAM_WIDTH = 6, // width parameter HISTOGRAM_HEIGHT = 6, // height parameter HISTOGRAM_HEIGHT = 6, // height parameter HISTOGRAM_STRAT_PAGE = 20'h12345, parameter HISTOGRAM_STRAT_PAGE = 20'h12345, parameter FRAME_WIDTH_ROUND_BITS = 9, // multiple of 512 pixels (32 16-byte bursts) (11 - ful SDRAM page) parameter WOI_WIDTH= 64 parameter WOI_WIDTH= 64 No newline at end of file sensor/sens_parallel12.v +2 −3 Original line number Original line Diff line number Diff line Loading @@ -181,7 +181,6 @@ module sens_parallel12 #( wire hact_ext; // received hact signal wire hact_ext; // received hact signal reg hact_ext_r; // received hact signal, delayed by 1 clock reg hact_ext_r; // received hact signal, delayed by 1 clock reg hact_r; // received or regenerated hact reg hact_r; // received or regenerated hact assign set_pxd_delay = set_idelay[2:0]; assign set_pxd_delay = set_idelay[2:0]; assign set_other_delay = set_idelay[3]; assign set_other_delay = set_idelay[3]; assign status = {locked_pxd_mmcm,clkin_pxd_stopped_mmcm,clkfb_pxd_stopped_mmcm,xfpgadone,ps_rdy, ps_out,xfpgatdo,senspgmin}; assign status = {locked_pxd_mmcm,clkin_pxd_stopped_mmcm,clkfb_pxd_stopped_mmcm,xfpgadone,ps_rdy, ps_out,xfpgatdo,senspgmin}; Loading Loading @@ -602,8 +601,8 @@ module sens_parallel12 #( // .CLKOUT4_USE_FINE_PS("FALSE"), // .CLKOUT4_USE_FINE_PS("FALSE"), // .CLKOUT5_USE_FINE_PS("FALSE"), // .CLKOUT5_USE_FINE_PS("FALSE"), // .CLKOUT6_USE_FINE_PS("FALSE"), // .CLKOUT6_USE_FINE_PS("FALSE"), .CLKOUT0_DIVIDE_F (4.000), .CLKOUT0_DIVIDE_F (8.000), .CLKOUT1_DIVIDE (8), .CLKOUT1_DIVIDE (4), // .CLKOUT2_DIVIDE (1), // .CLKOUT2_DIVIDE (1), // .CLKOUT3_DIVIDE (1), // .CLKOUT3_DIVIDE (1), // .CLKOUT4_DIVIDE(1), // .CLKOUT4_DIVIDE(1), Loading Loading
.settings/com.elphel.vdt.FPGA_project.prefs +2 −2 Original line number Original line Diff line number Diff line FPGA_project_0_SimulationTopFile=x393_testbench01.tf FPGA_project_0_SimulationTopFile=x393_testbench02.tf FPGA_project_1_SimulationTopModule=x393_testbench01 FPGA_project_1_SimulationTopModule=x393_testbench02 FPGA_project_2_ImplementationTopFile=x393.v FPGA_project_2_ImplementationTopFile=x393.v FPGA_project_4_part=xc7z030fbg484-1 FPGA_project_4_part=xc7z030fbg484-1 com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@-> com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@-> Loading
includes/x393_localparams.vh +6 −1 Original line number Original line Diff line number Diff line Loading @@ -118,6 +118,10 @@ localparam STATUS_PSHIFTER_RDY_MASK = 1<<STATUS_2LSB_SHFT; localparam STATUS_PSHIFTER_RDY_MASK = 1<<STATUS_2LSB_SHFT; localparam FRAME_START_ADDRESS= 'h1000; // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0) localparam FRAME_START_ADDRESS= 'h1000; // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0) localparam FRAME_START_ADDRESS_INC= 'h800; localparam FRAME_START_ADDRESS_INC= 'h800; localparam LAST_BUF_FRAME = 1; localparam CAMSYNC_DELAY = 200; localparam FRAME_FULL_WIDTH= 'h0c0; // Padded line length (8-row increment), in 8-bursts (16 bytes) localparam FRAME_FULL_WIDTH= 'h0c0; // Padded line length (8-row increment), in 8-bursts (16 bytes) // localparam AFI_LO_ADDR64= 'h4000; // start of the system memory range in 64-bit words // localparam AFI_LO_ADDR64= 'h4000; // start of the system memory range in 64-bit words Loading Loading @@ -157,3 +161,4 @@ localparam TEST_INITIAL_BURST= 4; // 3; localparam TEST_INITIAL_BURST= 4; // 3; No newline at end of file
includes/x393_parameters.vh +8 −6 Original line number Original line Diff line number Diff line Loading @@ -431,7 +431,7 @@ //sensor_fifo parameters //sensor_fifo parameters parameter SENSOR_DATA_WIDTH = 12, parameter SENSOR_DATA_WIDTH = 12, parameter SENSOR_FIFO_2DEPTH = 4, parameter SENSOR_FIFO_2DEPTH = 4, parameter SENSOR_FIFO_DELAY = 4'd7, parameter SENSOR_FIFO_DELAY = 4'd5, // 7, // other parameters for histogram_saxi module // other parameters for histogram_saxi module parameter HIST_SAXI_ADDR_MASK = 'h7f0, parameter HIST_SAXI_ADDR_MASK = 'h7f0, parameter HIST_SAXI_MODE_WIDTH = 8, parameter HIST_SAXI_MODE_WIDTH = 8, Loading Loading @@ -615,11 +615,13 @@ parameter CAMSYNC_TRIG_DELAY1 = 'h5, // setup input trigger delay parameter CAMSYNC_TRIG_DELAY1 = 'h5, // setup input trigger delay parameter CAMSYNC_TRIG_DELAY2 = 'h6, // setup input trigger delay parameter CAMSYNC_TRIG_DELAY2 = 'h6, // setup input trigger delay parameter CAMSYNC_TRIG_DELAY3 = 'h7, // setup input trigger delay parameter CAMSYNC_TRIG_DELAY3 = 'h7, // setup input trigger delay parameter CAMSYNC_SNDEN_BIT = 'h1, // enable writing ts_snd_en parameter CAMSYNC_EXTERNAL_BIT = 'h3, // enable writing ts_external (0 - local timestamp in the frame header) parameter CAMSYNC_EN_BIT = 'h0, // enable module (0 - reset) parameter CAMSYNC_TRIGGERED_BIT = 'h5, // triggered mode ( 0- async) parameter CAMSYNC_SNDEN_BIT = 'h2, // enable writing ts_snd_en parameter CAMSYNC_MASTER_BIT = 'h8, // select a 2-bit master channel (master delay may be used as a flash delay) parameter CAMSYNC_EXTERNAL_BIT = 'h4, // enable writing ts_external (0 - local timestamp in the frame header) parameter CAMSYNC_CHN_EN_BIT = 'hd, // per-channel enable timestamp generation parameter CAMSYNC_TRIGGERED_BIT = 'h6, // triggered mode ( 0- async) parameter CAMSYNC_MASTER_BIT = 'h9, // select a 2-bit master channel (master delay may be used as a flash delay) parameter CAMSYNC_CHN_EN_BIT = 'he, // per-channel enable timestamp generation parameter CAMSYNC_PRE_MAGIC = 6'b110100, parameter CAMSYNC_PRE_MAGIC = 6'b110100, parameter CAMSYNC_POST_MAGIC = 6'b001101, parameter CAMSYNC_POST_MAGIC = 6'b001101, Loading
includes/x393_simulation_parameters.vh +12 −10 Original line number Original line Diff line number Diff line Loading @@ -28,16 +28,16 @@ parameter SIMUL_AXI_READ_WIDTH=16, parameter SIMUL_AXI_READ_WIDTH=16, parameter MEMCLK_PERIOD = 5.0, parameter MEMCLK_PERIOD = 5.0, parameter FCLK0_PERIOD = 10.417, parameter FCLK0_PERIOD = 41.667, // 10.417, 24MHz parameter FCLK1_PERIOD = 0.0, parameter FCLK1_PERIOD = 0.0, parameter SENSOR12BITS_LLINE = 192, // 1664;// line duration in clocks // parameter SENSOR12BITS_LLINE = 192, // 1664;// line duration in clocks parameter SENSOR12BITS_NCOLS = 66, //58; //56; // 129; //128; //1288; // parameter SENSOR12BITS_NCOLS = 66, //58; //56; // 129; //128; //1288; parameter SENSOR12BITS_NROWS = 18, // 16; // 1032; // parameter SENSOR12BITS_NROWS = 18, // 16; // 1032; parameter SENSOR12BITS_NROWB = 1, // number of "blank rows" from vact to 1-st hact // parameter SENSOR12BITS_NROWB = 1, // number of "blank rows" from vact to 1-st hact parameter SENSOR12BITS_NROWA = 1, // number of "blank rows" from last hact to end of vact // parameter SENSOR12BITS_NROWA = 1, // number of "blank rows" from last hact to end of vact // parameter nAV = 24, //240; // clocks from ARO to VACT (actually from en_dclkd) // parameter nAV = 24, //240; // clocks from ARO to VACT (actually from en_dclkd) parameter SENSOR12BITS_NBPF = 20, //16; // bpf length // parameter SENSOR12BITS_NBPF = 20, //16; // bpf length parameter SENSOR12BITS_NGPL = 8, // bpf to hact parameter SENSOR12BITS_NGPL = 8, // bpf to hact parameter SENSOR12BITS_NVLO = 1, // VACT=0 in video mode (clocks) parameter SENSOR12BITS_NVLO = 1, // VACT=0 in video mode (clocks) //parameter tMD = 14; // //parameter tMD = 14; // Loading @@ -45,15 +45,17 @@ parameter SENSOR12BITS_TMD = 4, // parameter SENSOR12BITS_TMD = 4, // parameter SENSOR12BITS_TDDO = 2, // some confusion here - let's assume that it is from DCLK to Data out parameter SENSOR12BITS_TDDO = 2, // some confusion here - let's assume that it is from DCLK to Data out parameter SENSOR12BITS_TDDO1 = 5, // parameter SENSOR12BITS_TDDO1 = 5, // parameter SENSOR12BITS_TRIGDLY = 8, // delay between trigger input and start of output (VACT) in lines // parameter SENSOR12BITS_TRIGDLY = 8, // delay between trigger input and start of output (VACT) in lines parameter SENSOR12BITS_RAMP = 1, // 1 - ramp, 0 - random (now - sensor.dat) // parameter SENSOR12BITS_RAMP = 1, // 1 - ramp, 0 - random (now - sensor.dat) parameter SENSOR12BITS_NEW_BAYER = 0, // 0 - "old" tiles (16x16, 1 - new - (18x18) // parameter SENSOR12BITS_NEW_BAYER = 0, // 0 - "old" tiles (16x16, 1 - new - (18x18) parameter HISTOGRAM_LEFT = 0, //2; // left parameter HISTOGRAM_LEFT = 0, //2; // left parameter HISTOGRAM_TOP = 2, // top parameter HISTOGRAM_TOP = 2, // top parameter HISTOGRAM_WIDTH = 6, // width parameter HISTOGRAM_WIDTH = 6, // width parameter HISTOGRAM_HEIGHT = 6, // height parameter HISTOGRAM_HEIGHT = 6, // height parameter HISTOGRAM_STRAT_PAGE = 20'h12345, parameter HISTOGRAM_STRAT_PAGE = 20'h12345, parameter FRAME_WIDTH_ROUND_BITS = 9, // multiple of 512 pixels (32 16-byte bursts) (11 - ful SDRAM page) parameter WOI_WIDTH= 64 parameter WOI_WIDTH= 64 No newline at end of file
sensor/sens_parallel12.v +2 −3 Original line number Original line Diff line number Diff line Loading @@ -181,7 +181,6 @@ module sens_parallel12 #( wire hact_ext; // received hact signal wire hact_ext; // received hact signal reg hact_ext_r; // received hact signal, delayed by 1 clock reg hact_ext_r; // received hact signal, delayed by 1 clock reg hact_r; // received or regenerated hact reg hact_r; // received or regenerated hact assign set_pxd_delay = set_idelay[2:0]; assign set_pxd_delay = set_idelay[2:0]; assign set_other_delay = set_idelay[3]; assign set_other_delay = set_idelay[3]; assign status = {locked_pxd_mmcm,clkin_pxd_stopped_mmcm,clkfb_pxd_stopped_mmcm,xfpgadone,ps_rdy, ps_out,xfpgatdo,senspgmin}; assign status = {locked_pxd_mmcm,clkin_pxd_stopped_mmcm,clkfb_pxd_stopped_mmcm,xfpgadone,ps_rdy, ps_out,xfpgatdo,senspgmin}; Loading Loading @@ -602,8 +601,8 @@ module sens_parallel12 #( // .CLKOUT4_USE_FINE_PS("FALSE"), // .CLKOUT4_USE_FINE_PS("FALSE"), // .CLKOUT5_USE_FINE_PS("FALSE"), // .CLKOUT5_USE_FINE_PS("FALSE"), // .CLKOUT6_USE_FINE_PS("FALSE"), // .CLKOUT6_USE_FINE_PS("FALSE"), .CLKOUT0_DIVIDE_F (4.000), .CLKOUT0_DIVIDE_F (8.000), .CLKOUT1_DIVIDE (8), .CLKOUT1_DIVIDE (4), // .CLKOUT2_DIVIDE (1), // .CLKOUT2_DIVIDE (1), // .CLKOUT3_DIVIDE (1), // .CLKOUT3_DIVIDE (1), // .CLKOUT4_DIVIDE(1), // .CLKOUT4_DIVIDE(1), Loading
