Commit 4a49c160 authored by Andrey Filippov's avatar Andrey Filippov

added missing files

parent 023b0015
/unisims
unisims
glbl.v
vivado_*
FPGA_project_2_ImplementationTopFile=phy/test_dqs07.v
FPGA_project_4_part=xc7z030fbg484-2
com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->
eclipse.preferences.version=1
VivadoBitstream_105_force=true
com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->
eclipse.preferences.version=1
VivadoSynthesis_102_ConstraintsFiles=phy/test_dqs07_placement.xdc<-@\#\#@->
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->
eclipse.preferences.version=1
/*******************************************************************************
* Module: byte_lane
* Date:2014-04-26
* Author: Andrey Filippov
* Description: DDR3 byte lane, ingluding DQS I/O, 8xDQ I/O and DM output
*
* Copyright (c) 2014 Elphel, Inc.
* byte_lane.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* byte_lane.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module byte_lane #(
parameter IODELAY_GRP ="IODELAY_MEMORY",
parameter IBUF_LOW_PWR ="TRUE",
parameter IOSTANDARD_DQ = "SSTL15_T_DCI",
parameter IOSTANDARD_DQS = "DIFF_SSTL15_T_DCI",
parameter SLEW = "SLOW",
parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE"
)(
inout [7:0] dq, // DQ I/O pads
inout dm, // DM I/O pad (actually only output)
inout dqs, // DQS I/O pad
inout ndqs, // ~DQS I/O pad
input clk, // free-running system clock, same frequency as iclk (shared for R/W)
input clk_div, // free-running half clk frequency, front aligned to clk (shared for R/W)
input inv_clk_div, // invert clk_div for R channels (clk_div is shared between R and W)
input rst,
input dci_disable_dqs, // disable DCI termination during writes and idle for dqs
input dci_disable_dq, // disable DCI termination during writes and idle for dq and dm signals
input [31:0] din, // parallel data to be sent out (4 bits per DG I/))
input [3:0] din_dm, // parallel data to be sent out over DM
input [3:0] tin_dq, // tristate for data out (sent out earlier than data!) and dm
input [3:0] din_dqs, // parallel data to be sent out over DQS
input [3:0] tin_dqs, // tristate for DQS out (sent out earlier than data!)
output [31:0] dout, // parallel data received from DDR3 memory, 4 bits per DG I/O
input [7:0] dly_data, // delay value (3 LSB - fine delay)
input [4:0] dly_addr, // select which delay to program
input ld_delay, // load delay data to selected iodelayl (clk_iv synchronous)
input set // clk_div synchronous set all delays from previously loaded values
);
//(* CLOCK_DEDICATED_ROUTE = "FALSE" *) // does not seem to work
wire dqs_read;
wire iclk; // source-synchronous clock (BUFR from DQS)
reg [31:0] din_r=0;
reg [3:0] din_dm_r=0, din_dqs_r=0, tin_dq_r=4'hf, tin_dqs_r=4'hf;
reg [7:0] dly_data_r=0;
reg set_r=0;
reg [7:0] ld_odly=8'b0, ld_idly=8'b0;
reg ld_odly_dqs,ld_idly_dqs,ld_odly_dm;
reg dci_disable_dqs_r, dci_disable_dq_r;
BUFR iclk_i (.O(iclk),.I(dqs_read), .CLR(1'b0),.CE(1'b1)); // OK, works with constraint? Seems now work w/o
wire [9:0] decode_sel={
(dly_addr[3:0]==9)?1'b1:1'b0,
(dly_addr[3:0]==8)?1'b1:1'b0,
(dly_addr[3:0]==7)?1'b1:1'b0,
(dly_addr[3:0]==6)?1'b1:1'b0,
(dly_addr[3:0]==5)?1'b1:1'b0,
(dly_addr[3:0]==4)?1'b1:1'b0,
(dly_addr[3:0]==3)?1'b1:1'b0,
(dly_addr[3:0]==2)?1'b1:1'b0,
(dly_addr[3:0]==1)?1'b1:1'b0,
(dly_addr[3:0]==0)?1'b1:1'b0};
always @ (posedge clk_div or posedge rst) begin
if (rst) begin
din_r <= 32'b0; din_dm_r<=0; din_dqs_r<=0; tin_dq_r<=4'hf; tin_dqs_r<=4'hf;
dly_data_r<=8'b0;set_r<=1'b0;
dci_disable_dqs_r <= 1'b1; dci_disable_dq_r <=1'b1;
ld_odly<=8'b0; ld_idly<=8'b0; ld_odly_dqs<=1'b0; ld_idly_dqs<=1'b0; ld_odly_dm<=1'b0;
end else begin
din_r<=din[31:0]; din_dm_r<=din_dm; din_dqs_r<=din_dqs; tin_dq_r<=tin_dq; tin_dqs_r<=tin_dqs;
dly_data_r<=dly_data; set_r<=set;
dci_disable_dqs_r <= dci_disable_dqs; dci_disable_dq_r <= dci_disable_dq;
{ld_odly_dm,ld_odly_dqs,ld_odly[7:0]} <= {10{(~dly_addr[4]) & ld_delay}} & decode_sel;
{ ld_idly_dqs,ld_idly[7:0]} <= {9 {( dly_addr[4]) & ld_delay}} & decode_sel[8:0];
end
end
generate
genvar i;
for (i=0; i<7; i=i+1) begin: dq_block
dq_single #(
.IODELAY_GRP(IODELAY_GRP),
.IBUF_LOW_PWR(IBUF_LOW_PWR),
.IOSTANDARD(IOSTANDARD_DQ),
.SLEW(SLEW),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dq_i(
.dq(dq[i]), // I/O pad
.iclk(iclk), // source-synchronous clock (BUFR from DQS)
.clk(clk), // free-running system clock, same frequency as iclk (shared for R/W)
.clk_div(clk_div), // free-running half clk frequency, front aligned to clk (shared for R/W)
.inv_clk_div(inv_clk_div), // invert clk_div for R channel (clk_div is shared between R and W)
.rst(rst),
.dci_disable(dci_disable_dq_r), // disable DCI termination during writes and idle
.dly_data(dly_data_r), // delay value (3 LSB - fine delay)
.din(din_r[4*i+3:4*i]) , // parallel data to be sent out
.tin(tin_dq_r), // tristate for data out (sent out earlier than data!)
.dout(dout[4*i+3:4*i]), // parallel data received from DDR3 memory
.set_odelay(set_r), // clk_div synchronous load odelay value from dly_data
.ld_odelay(ld_odly[i]), // clk_div synchronous set odealy value from loaded
.set_idelay(set_r), // clk_div synchronous load idelay value from dly_data
.ld_idelay(ld_idly[i]) // clk_div synchronous set idealy value from loaded
);
end
endgenerate
dq_single #(
.IODELAY_GRP(IODELAY_GRP),
.IBUF_LOW_PWR(IBUF_LOW_PWR),
.IOSTANDARD(IOSTANDARD_DQ),
.SLEW(SLEW),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dm_i(
.dq(dm), // DM output pad
.iclk(iclk), // source-synchronous clock (BUFR from DQS)
.clk(clk), // free-running system clock, same frequency as iclk (shared for R/W)
.clk_div(clk_div), // free-running half clk frequency, front aligned to clk (shared for R/W)
.inv_clk_div(inv_clk_div), // invert clk_div for R channel (clk_div is shared between R and W)
.rst(rst),
.dci_disable(dci_disable_dq_r), // disable DCI termination during writes and idle
.dly_data(dly_data_r), // delay value (3 LSB - fine delay)
.din(din_dm_r[3:0]) , // parallel data to be sent out
.tin(tin_dq_r), // tristate for data out (sent out earlier than data!)
.dout(), // parallel data received from DDR3 memory
.set_odelay(set_r), // clk_div synchronous load odelay value from dly_data
.ld_odelay(ld_odly_dm), // clk_div synchronous set odealy value from loaded
.set_idelay(1'b0), // clk_div synchronous load idelay value from dly_data
.ld_idelay(1'b0) // clk_div synchronous set idealy value from loaded
);
dqs_single #(
.IODELAY_GRP(IODELAY_GRP),
.IBUF_LOW_PWR(IBUF_LOW_PWR),
.IOSTANDARD(IOSTANDARD_DQS),
.SLEW(SLEW),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dqs_i (
.dqs(dqs),
.ndqs(ndqs),
.clk(clk),
.clk_div(clk_div),
.rst(rst),
.dqs_received_dly(dqs_read),
.dci_disable(dci_disable_dqs_r), // disable DCI termination during writes and idle
.dly_data(dly_data_r[7:0]),
.din(din_dqs_r[3:0]),
.tin(tin_dqs_r[3:0]),
.set_odelay(set_r),
.ld_odelay(ld_odly_dqs),
.set_idelay(set_r),
.ld_idelay(ld_idly_dqs)
);
endmodule
/*******************************************************************************
* Module: cmda_single
* Date:2014-04-26
* Author: Andrey Filippov
* Description: Single-bit CMD/address output
*
* Copyright (c) 2014 Elphel, Inc.
* cmda_single.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* cmda_single.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module cmda_single #(
parameter IODELAY_GRP ="IODELAY_MEMORY",
parameter IBUF_LOW_PWR ="TRUE",
parameter IOSTANDARD = "SSTL15",
parameter SLEW = "SLOW",
parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE"
)(
inout dq, // I/O pad
input iclk, // source-synchronous clock (BUFR from DQS)
input clk, // free-running system clock, same frequency as iclk (shared for R/W)
input clk_div, // free-running half clk frequency, front aligned to clk (shared for R/W)
input inv_clk_div, // invert clk_div for R channel (clk_div is shared between R and W)
input rst,
input dci_disable, // disable DCI termination during writes and idle
input [7:0] dly_data, // delay value (3 LSB - fine delay)
input [3:0] din, // parallel data to be sent out
input [3:0] tin, // tristate for data out (sent out earlier than data!)
output [3:0] dout, // parallel data received from DDR3 memory
input set_odelay, // clk_div synchronous load odelay value from dly_data
input ld_odelay, // clk_div synchronous set odealy value from loaded
input set_idelay, // clk_div synchronous load idelay value from dly_data
input ld_idelay // clk_div synchronous set idealy value from loaded
);
wire d_ser;
wire dq_tri;
wire dq_data_dly;
wire dq_dly;
// keep IOBUF_DCIEN.O to user as output only (UDM/LDM), so the rest of tyhe read channel will be optimized out, but I/O will stay the same
(* keep = "true" *)
wire dq_di;
oserdes_mem#(
.MODE_DDR("FALSE")
) oserdes_i (
.clk(clk), // serial output clock
.clk_div(clk_div), // oclk divided by 2, front aligned
.rst(rst), // reset
.din(din[3:0]), // parallel data in
.tin(tin[3:0]), // parallel tri-state in
.dout_dly(d_ser), // data out to be connected to odelay input
.dout_iob(), // data out to be connected directly to the output buffer
.tout_dly(), // tristate out to be connected to odelay input
.tout_iob(dq_tri) // tristate out to be connected directly to the tristate control of the output buffer
);
odelay_fine_pipe # (
.IODELAY_GRP(IODELAY_GRP),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dqs_out_dly_i(
.clk(clk_div),
.rst(rst),
.set(set_odelay),
.ld(ld_odelay),
.delay(dly_data[7:0]),
.data_in(d_ser),
.data_out(dq_data_dly)
);
IOBUF_DCIEN #(
.IBUF_LOW_PWR(IBUF_LOW_PWR), //
.IOSTANDARD(IOSTANDARD),
.SLEW(SLEW),
.USE_IBUFDISABLE("FALSE")
) iobufs_dqs_i (
.O(dq_di),
.IO(dq),
.DCITERMDISABLE(dci_disable),
.IBUFDISABLE(1'b0),
.I(dq_data_dly), //dqs_data),
.T(dq_tri));
idelay_fine_pipe # (
.IODELAY_GRP(IODELAY_GRP),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dqs_in_dly_i(
.clk(clk_div),
.rst(rst),
.set(set_idelay),
.ld(ld_idelay),
.delay(dly_data[7:0]),
.data_in(dq_di),
.data_out(dq_dly)
);
iserdes_mem #(
.DYN_CLKDIV_INV_EN("FALSE")
) iserdes_mem_i (
.iclk(iclk), // source-synchronous clock
.oclk(clk), // system clock, phase should allow iclk-to-oclk jitter with setup/hold margin
.oclk_div(clk_div), // oclk divided by 2, front aligned
.inv_clk_div(inv_clk_div), // invert oclk_div (this clock is shared between iserdes and oserdes. Works only in MEMORY_DDR3 mode?
.rst(rst), // reset
.d_direct(1'b0), // direct input from IOB, normally not used, controlled by IOBDELAY parameter (set to "NONE")
.ddly(dq_dly), // serial input from idelay
.dout(dout[3:0]) // parallel data out
);
endmodule
/*******************************************************************************
* Module: dq_single
* Date:2014-04-26
* Author: Andrey Filippov
* Description: Single-bit DDR3 DQ I/O, same used for DM
*
* Copyright (c) 2014 Elphel, Inc.
* dq_single.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* dq_single.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module dq_single #(
parameter IODELAY_GRP ="IODELAY_MEMORY",
parameter IBUF_LOW_PWR ="TRUE",
parameter IOSTANDARD = "SSTL15_T_DCI",
parameter SLEW = "SLOW",
parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE"
)(
inout dq, // I/O pad
input iclk, // source-synchronous clock (BUFR from DQS)
input clk, // free-running system clock, same frequency as iclk (shared for R/W)
input clk_div, // free-running half clk frequency, front aligned to clk (shared for R/W)
input inv_clk_div, // invert clk_div for R channel (clk_div is shared between R and W)
input rst,
input dci_disable, // disable DCI termination during writes and idle
input [7:0] dly_data, // delay value (3 LSB - fine delay)
input [3:0] din, // parallel data to be sent out
input [3:0] tin, // tristate for data out (sent out earlier than data!)
output [3:0] dout, // parallel data received from DDR3 memory
input set_odelay, // clk_div synchronous load odelay value from dly_data
input ld_odelay, // clk_div synchronous set odealy value from loaded
input set_idelay, // clk_div synchronous load idelay value from dly_data
input ld_idelay // clk_div synchronous set idealy value from loaded
);
wire d_ser;
wire dq_tri;
wire dq_data_dly;
wire dq_dly;
// keep IOBUF_DCIEN.O to user as output only (UDM/LDM), so the rest of tyhe read channel will be optimized out, but I/O will stay the same
(* keep = "true" *)
wire dq_di;
oserdes_mem#(
.MODE_DDR("TRUE")
) oserdes_i (
.clk(clk), // serial output clock
.clk_div(clk_div), // oclk divided by 2, front aligned
.rst(rst), // reset
.din(din[3:0]), // parallel data in
.tin(tin[3:0]), // parallel tri-state in
.dout_dly(d_ser), // data out to be connected to odelay input
.dout_iob(), // data out to be connected directly to the output buffer
.tout_dly(), // tristate out to be connected to odelay input
.tout_iob(dq_tri) // tristate out to be connected directly to the tristate control of the output buffer
);
odelay_fine_pipe # (
.IODELAY_GRP(IODELAY_GRP),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dqs_out_dly_i(
.clk(clk_div),
.rst(rst),
.set(set_odelay),
.ld(ld_odelay),
.delay(dly_data[7:0]),
.data_in(d_ser),
.data_out(dq_data_dly)
);
IOBUF_DCIEN #(
.IBUF_LOW_PWR(IBUF_LOW_PWR), //
.IOSTANDARD(IOSTANDARD),
.SLEW(SLEW),
.USE_IBUFDISABLE("FALSE")
) iobufs_dqs_i (
.O(dq_di),
.IO(dq),
.DCITERMDISABLE(dci_disable),
.IBUFDISABLE(1'b0),
.I(dq_data_dly), //dqs_data),
.T(dq_tri));
idelay_fine_pipe # (
.IODELAY_GRP(IODELAY_GRP),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dqs_in_dly_i(
.clk(clk_div),
.rst(rst),
.set(set_idelay),
.ld(ld_idelay),
.delay(dly_data[7:0]),
.data_in(dq_di),
.data_out(dq_dly)
);
iserdes_mem #(
.DYN_CLKDIV_INV_EN("FALSE")
) iserdes_mem_i (
.iclk(iclk), // source-synchronous clock
.oclk(clk), // system clock, phase should allow iclk-to-oclk jitter with setup/hold margin
.oclk_div(clk_div), // oclk divided by 2, front aligned
.inv_clk_div(inv_clk_div), // invert oclk_div (this clock is shared between iserdes and oserdes. Works only in MEMORY_DDR3 mode?
.rst(rst), // reset
.d_direct(1'b0), // direct input from IOB, normally not used, controlled by IOBDELAY parameter (set to "NONE")
.ddly(dq_dly), // serial input from idelay
.dout(dout[3:0]) // parallel data out
);
endmodule
/*******************************************************************************
* Module: dqs_single
* Date:2014-04-26
* Author: Andrey Filippov
* Description: Single-bit DDR3 DQS I/O
*
* Copyright (c) 2014 Elphel, Inc.
* dqs_single.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* dqs_single.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module dqs_single #(
parameter IODELAY_GRP ="IODELAY_MEMORY",
parameter IBUF_LOW_PWR ="TRUE",
parameter IOSTANDARD = "DIFF_SSTL15_T_DCI",
parameter SLEW = "SLOW",
parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE"
)(
inout dqs,
inout ndqs,
input clk,
input clk_div,
input rst,
output dqs_received_dly,
input dci_disable, // disable DCI termination during writes and idle
input [7:0] dly_data,
input [3:0] din,
input [3:0] tin,
input set_odelay,
input ld_odelay,
input set_idelay,
input ld_idelay
);
wire d_ser;
wire dqs_tri;
wire dqs_data_dly;
wire dqs_di;
oserdes_mem oserdes_i (
.clk(clk), // serial output clock
.clk_div(clk_div), // oclk divided by 2, front aligned
.rst(rst), // reset
.din(din[3:0]), // parallel data in
.tin(tin[3:0]), // parallel tri-state in
.dout_dly(d_ser), // data out to be connected to odelay input
.dout_iob(), // data out to be connected directly to the output buffer
.tout_dly(), // tristate out to be connected to odelay input
.tout_iob(dqs_tri) // tristate out to be connected directly to the tristate control of the output buffer
);
odelay_fine_pipe # (
.IODELAY_GRP(IODELAY_GRP),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dqs_out_dly_i(
.clk(clk_div),
.rst(rst),
.set(set_odelay),
.ld(ld_odelay),
.delay(dly_data[7:0]),
.data_in(d_ser),
.data_out(dqs_data_dly)
);
IOBUFDS_DCIEN #(
.DIFF_TERM("FALSE"),
.DQS_BIAS("TRUE"), // outputs 1'b0 when IOB is floating
.IBUF_LOW_PWR(IBUF_LOW_PWR), //
.IOSTANDARD(IOSTANDARD),
.SLEW(SLEW),
.USE_IBUFDISABLE("FALSE")
) iobufs_dqs_i (
.O(dqs_di),
.IO(dqs),
.IOB(ndqs),
.DCITERMDISABLE(dci_disable),
.IBUFDISABLE(1'b0),
.I(dqs_data_dly), //dqs_data),
.T(dqs_tri));
idelay_fine_pipe # (
.IODELAY_GRP(IODELAY_GRP),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dqs_in_dly_i(
.clk(clk_div),
.rst(rst),
.set(set_idelay),
.ld(ld_idelay),
.delay(dly_data[7:0]),
.data_in(dqs_di),
.data_out(dqs_received_dly)
);
endmodule
/*******************************************************************************
* Module: test_dqs
* Date:2014-04-26
* Author: Andrey Filippov
* Description: Testing DQS implementation
*
* Copyright (c) 2014 Elphel, Inc.
* test_dqs.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* test_dqs.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module test_dqs(
input rst, // reset
input refclk, // 200MHz/300MHz for delay calibration
input clk_in,
input set,
input ld_dly_data,
input ld_dly_tri,
input [7:0] dly_data,
input [3:0] data_in,
input [3:0] tri_in,
inout dqs,
inout ndqs,
output dqs_received,
output dly_ready,
input dqs_tri_a,
output dqs_tri
);
wire refclk_b=refclk; // use buffer
wire clk, clk_div;
//wire dqs_data,dqs_tri; // after odelay
wire dqs_data; // after odelay
wire pre_dqs_data,pre_dqs_tri; // before odelay
BUFR #(.BUFR_DIVIDE("2")) clk_div_i (.I(clk_in),.O(clk_div),.CLR(rst), .CE(1'b1));
BUFR #(.BUFR_DIVIDE("BYPASS")) clk_i (.I(clk_in),.O(clk), .CLR(1'b0),.CE(1'b1));
oserdes_mem oserdes_dqs_i(
.clk(clk), // serial output clock
.clk_div(clk_div), // oclk divided by 2, front aligned
.rst(rst), // reset
.din(data_in), // parallel data in
.tin(tri_in), // parallel tri-state in
.dout_dly(), // data out to be connected to odelay input
.dout_iob(pre_dqs_data), // data out to be connected directly to the output buffer
.tout_dly(), // tristate out to be connected to odelay input
.tout_iob(pre_dqs_tri) // tristate out to be connected directly to the tristate control of the output buffer
);
idelay_ctrl# (
.IODELAY_GRP("IODELAY_MEMORY")
) idelay_ctrl_i (
.refclk(refclk_b),
.rst(rst),
.rdy(dly_ready)
);
odelay_fine_pipe # (
.IODELAY_GRP("IODELAY_MEMORY"),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(300.0),
.HIGH_PERFORMANCE_MODE("FALSE")
) dqs_data_dly_i(
.clk(clk_div),
.rst(rst),
.set(set),
.ld(ld_dly_data),
.delay(dly_data),
.data_in(pre_dqs_data),
.data_out(dqs_data)
);
odelay_fine_pipe # (
.IODELAY_GRP("IODELAY_MEMORY"),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(300.0),
.HIGH_PERFORMANCE_MODE("FALSE")
) dqs_tri_dly_i(
.clk(clk_div),
.rst(rst),
.set(set),
.ld(ld_dly_tri),
.delay(dly_data),
.data_in(pre_dqs_tri),
.data_out(dqs_tri)
);
//wire dqs_tri_a;
//(* keep = "true" *) BUF buf0_i(.O(dqs_tri_a), .I(dqs_tri));
IOBUFDS #(
.DQS_BIAS("FALSE"),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
) iobufs_dqs_i (
.O(dqs_received),
.IO(dqs),
.IOB(ndqs),
.I(dqs_data),
// .T(dqs_tri_a));
.T(1'b0));
endmodule
/*******************************************************************************
* Module: test_dqs01
* Date:2014-04-26
* Author: Andrey Filippov
* Description: Testing DQS implementation
*
* Copyright (c) 2014 Elphel, Inc.
* test_dqs01.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* test_dqs01.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module test_dqs01(
input dqs_data,
inout dqs,
inout ndqs,
output dqs_received,
input dqs_tri
);
IOBUFDS #(
.DQS_BIAS("FALSE"),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
) iobufs_dqs_i (
.O(dqs_received),
.IO(dqs),
.IOB(ndqs),
.I(dqs_data),
.T(dqs_tri));
endmodule
set_property PACKAGE_PIN N7 [get_ports {dqs}]
set_property SLEW FAST [get_ports {dqs}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {dqs}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dqs}]
set_property PACKAGE_PIN N6 [get_ports {ndqs}]
set_property SLEW FAST [get_ports {ndqs}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ndqs}]