- 08 Nov, 2015 3 commits
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Andrey Filippov authored
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Andrey Filippov authored
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Andrey Filippov authored
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- 01 Nov, 2015 1 commit
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Andrey Filippov authored
Made several modifications to fix all timing violations to run compressor @250MHz - 1.0 Gigapixel/sec in JP4 mode
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- 31 Oct, 2015 1 commit
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Andrey Filippov authored
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- 20 Oct, 2015 1 commit
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Andrey Filippov authored
implemented optional skipping/fast forward of the data blocks when buffer is over/underrun during memory access
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- 18 Oct, 2015 1 commit
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Andrey Filippov authored
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- 13 Oct, 2015 1 commit
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Andrey Filippov authored
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- 12 Oct, 2015 2 commits
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Andrey Filippov authored
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Andrey Filippov authored
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- 11 Oct, 2015 1 commit
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Andrey Filippov authored
added simuilation modules for frequency multiplication/division, fractional period delays, started parallel12 -> HiSPi packetized SP converter
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- 23 Aug, 2015 1 commit
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Andrey Filippov authored
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- 18 Aug, 2015 1 commit
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Andrey Filippov authored
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- 06 Aug, 2015 1 commit
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Andrey Filippov authored
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- 05 Aug, 2015 2 commits
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Andrey Filippov authored
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Andrey Filippov authored
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- 02 Aug, 2015 1 commit
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Andrey Filippov authored
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- 01 Aug, 2015 1 commit
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Andrey Filippov authored
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- 12 Jul, 2015 1 commit
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Andrey Filippov authored
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- 06 Jul, 2015 1 commit
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Andrey Filippov authored
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- 29 Jun, 2015 1 commit
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Andrey Filippov authored
Working on cmprs_afi_mux.v, extracted 2 sub-modules: cmprs_afi_mux_ptr.v and cmprs_afi_mux_ptr_wresp.v
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- 05 May, 2015 1 commit
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Andrey Filippov authored
Fixed handling AXI write responce channel - both in work and simulation modules. Before each word, not burst was responded
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- 30 Apr, 2015 1 commit
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Andrey Filippov authored
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- 29 Apr, 2015 1 commit
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Andrey Filippov authored
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- 27 Apr, 2015 2 commits
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Andrey Filippov authored
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Andrey Filippov authored
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- 26 Apr, 2015 2 commits
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Andrey Filippov authored
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Andrey Filippov authored
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- 12 Feb, 2015 1 commit
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Andrey Filippov authored
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- 22 May, 2014 2 commits
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Andrey Filippov authored
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Andrey Filippov authored
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