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Andrey Filippov authored
added simuilation modules for frequency multiplication/division, fractional period delays, started parallel12 -> HiSPi packetized SP converter
9ff78344
added simuilation modules for frequency multiplication/division, fractional period delays, started parallel12 -> HiSPi packetized SP converter
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par12_hispi_psp4l.v | Loading commit data... | |
sim_clk_div.v | Loading commit data... | |
sim_frac_clk_delay.v | Loading commit data... | |
simul_axi_fifo_out.v | Loading commit data... | |
simul_axi_hp_rd.v | Loading commit data... | |
simul_axi_hp_wr.v | Loading commit data... | |
simul_axi_master_rdaddr.v | Loading commit data... | |
simul_axi_master_wdata.v | Loading commit data... | |
simul_axi_master_wraddr.v | Loading commit data... | |
simul_axi_read.v | Loading commit data... | |
simul_axi_slow_ready.v | Loading commit data... | |
simul_clk.v | Loading commit data... | |
simul_clk_mult.v | Loading commit data... | |
simul_fifo.v | Loading commit data... | |
simul_saxi_gp_wr.v | Loading commit data... | |
simul_sensor12bits.v | Loading commit data... |