Commits · 8df14818b49fc8533911b2b94febb8b628f36827 · Elphel / x393

13 Mar, 2015 1 commit
- more hardware tests · 8df14818
  Andrey Filippov authored Mar 13, 2015
  
  8df14818
12 Mar, 2015 3 commits
- debugging hardware, added re filters for parameters and macros · 49288bf2
  Andrey Filippov authored Mar 12, 2015
  
  49288bf2
- debugging · 9326e242
  Andrey Filippov authored Mar 12, 2015
  
  9326e242
- working on hardware testing, added utility functions to load bitstream and use GPIO for debugging · 27a6599b
  Andrey Filippov authored Mar 12, 2015
  
  27a6599b
11 Mar, 2015 1 commit
- implemented help for task based on functions documentation · fad107cb
  Andrey Filippov authored Mar 11, 2015
  
  fad107cb
10 Mar, 2015 1 commit
- implemented @file in the test_mcntrl.py command line · e6868ded
  Andrey Filippov authored Mar 10, 2015
  
  e6868ded
08 Mar, 2015 1 commit
- more verilog tasks converted to python · f7c03985
  Andrey Filippov authored Mar 08, 2015
  
  f7c03985
07 Mar, 2015 1 commit
- next snapshot, implemented more expression types in parameter parsing · 8de61d31
  Andrey Filippov authored Mar 07, 2015
  
  8de61d31
05 Mar, 2015 2 commits
- more code converted from Verilog to Python · 21e45a99
  Andrey Filippov authored Mar 05, 2015
  
  21e45a99
- continue with python hardware test code · eba342eb
  Andrey Filippov authored Mar 05, 2015
  
  eba342eb
04 Mar, 2015 1 commit
- working on Python code for hardware testing · 63ff2819
  Andrey Filippov authored Mar 04, 2015
  
  63ff2819
03 Mar, 2015 1 commit
- creating Python program to pass Verilog parameters to Python FPGA tests · 4c3995d6
  Andrey Filippov authored Mar 03, 2015
  
  4c3995d6
01 Mar, 2015 1 commit
- working with Xilinx ISE/Vivado to synthesize and P&R the design · 0466926c
  Andrey Filippov authored Mar 01, 2015
  
  0466926c
28 Feb, 2015 1 commit
- working on synthesis with Vivado tools · 05378ee7
  Andrey Filippov authored Feb 28, 2015
  
  05378ee7
25 Feb, 2015 2 commits
- more fixes · df69d555
  Andrey Filippov authored Feb 25, 2015
  
  df69d555
- more bugs fixing with simulation · 7b13989a
  Andrey Filippov authored Feb 25, 2015
  
  7b13989a
23 Feb, 2015 1 commit
- before adding extra register layer between channel buffers outputs and memory controller · 943fc4a1
  Andrey Filippov authored Feb 23, 2015
  
  943fc4a1
22 Feb, 2015 3 commits
- more simulatin/bug fixing · d2db8c14
  Andrey Filippov authored Feb 22, 2015
  
  d2db8c14
- debugging after modifications · 7614ead5
  Andrey Filippov authored Feb 22, 2015
  
  7614ead5
- re-organized top structure · ad0351ef
  Andrey Filippov authored Feb 22, 2015
  
  ad0351ef
20 Feb, 2015 3 commits
- created and tested cmd_encod_tiled_32_wr.v - tiles with 32-byte columns · f35bb39d
  Andrey Filippov authored Feb 20, 2015
  
  f35bb39d
- added another channel for testing - tile write · a445ef42
  Andrey Filippov authored Feb 20, 2015
  
  a445ef42
- added tile write (column order) · 31a6b971
  Andrey Filippov authored Feb 20, 2015
  
  31a6b971
19 Feb, 2015 2 commits
- version of the tile read with 32-byte wide columns - easier timing with various tile heights · 22beced0
  Andrey Filippov authored Feb 19, 2015
  
  22beced0
- more debugging tile read · c8076f57
  Andrey Filippov authored Feb 19, 2015
  
  c8076f57
18 Feb, 2015 1 commit
- testing read memory as rectangular tiles · cd7cb395
  Andrey Filippov authored Feb 18, 2015
  
  cd7cb395
17 Feb, 2015 1 commit
- debugging larger frames write/read · 864a8593
  Andrey Filippov authored Feb 17, 2015
  
  864a8593
16 Feb, 2015 2 commits
- more debugging · 7c5ab53d
  Andrey Filippov authored Feb 16, 2015
  
  7c5ab53d
- modified scanline mode to work with SDRAM page crossing (by splitting in 2), debugging read mode · e3d5b404
  Andrey Filippov authored Feb 16, 2015
  
  e3d5b404
15 Feb, 2015 1 commit
- ran some tests with TEST_SCANLINE_WRITE, fixed some bugs · 547054f6
  Andrey Filippov authored Feb 15, 2015
  
  547054f6
14 Feb, 2015 1 commit
- debugging scanline read memory access · 8f79e6f7
  Andrey Filippov authored Feb 14, 2015
  
  8f79e6f7
13 Feb, 2015 3 commits
- split top level test fixture file into separate includes with tasks · cbbd4ed1
  Andrey Filippov authored Feb 13, 2015
  
  cbbd4ed1
- more debugging by simulation, bug fixing · 38d73a7b
  Andrey Filippov authored Feb 13, 2015
  
  38d73a7b
- debugging, more corrections, tested block write through PIO channel 1 · f4751492
  Andrey Filippov authored Feb 13, 2015
  
  f4751492
12 Feb, 2015 1 commit
- debugging, more corrections, tested write levelling/buffer reading · bb237119
  Andrey Filippov authored Feb 12, 2015
  
  bb237119
11 Feb, 2015 1 commit
- debugging/simulation · d899569e
  Andrey Filippov authored Feb 11, 2015
  
  d899569e
10 Feb, 2015 4 commits
- removed some old temporary files · 9acfc5c3
  Andrey Filippov authored Feb 10, 2015
  
  9acfc5c3
- moved directory phy under memcntrl (as it is a part of memory controller) · 466a4a4e
  Andrey Filippov authored Feb 10, 2015
  
  466a4a4e
- more simulation · dde1725e
  Andrey Filippov authored Feb 10, 2015
  
  dde1725e
- continue simulation, moved some code to includes after modifying VDT to... · f9e935af
  Andrey Filippov authored Feb 10, 2015
```
continue simulation, moved some code to includes after modifying VDT to support project-relative includes
```
  f9e935af