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Commit 63ff2819 authored by Andrey Filippov's avatar Andrey Filippov
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working on Python code for hardware testing

parent 4c3995d6
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Showing with 435 additions and 48 deletions
.gitignore
View file @ 63ff2819
......@@ -9,3 +9,4 @@ x393.prj
*DEBUG_VDT*
*.kate-swp
*.old
*.pyc
\ No newline at end of file
includes/x393_mcontr_encode_cmd.vh
View file @ 63ff2819
......@@ -35,7 +35,7 @@
input buf_rst; // connect to external buffer (but only if not paused)
begin
func_encode_skip= func_encode_cmd (
{{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]}, // 15-bit row/column adderss
{{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]}, // 15-bit row/column address
bank[2:0], // bank (here OK to be any)
3'b0, // RAS/CAS/WE, positive logic
odt_en, // enable ODT
......
includes/x393_tasks01.vh
View file @ 63ff2819
......@@ -21,7 +21,7 @@
// Low-level tasks
// alternative way to check for empty read queue (without a separate counter)
task write_contol_register;
task write_contol_register;
input [29:0] reg_addr;
// input integer reg_addr;
input [31:0] data;
......
py393/.settings/org.eclipse.core.resources.prefs
View file @ 63ff2819
eclipse.preferences.version=1
encoding/import_verilog_parameters.py=utf-8
encoding/test1.py=utf-8
encoding/test2.py=utf-8
py393/import_verilog_parameters.py
View file @ 63ff2819
......@@ -30,6 +30,18 @@ __status__ = "Development"
import re
import os
import string
class VerilogParameters(object): #this is Borg
__shared_state = {}
def __init__(self, parameters=None):
self.__dict__ = self.__shared_state
if (parameters):
adict={}
for parName in parameters:
adict[parName]= parameters[parName][0]
adict[parName+"__TYPE"]=parameters[parName][1]
adict[parName+"__RAW"]= parameters[parName][2]
self.__dict__.update(adict)
class ImportVerilogParameters(object):
'''
classdocs
......@@ -38,6 +50,7 @@ class ImportVerilogParameters(object):
parameters={}
conditions=[True]
rootPath=None
verbose=1
'''
parameters - dictionalry of already known parameters, defines - defined macros
'''
......@@ -47,6 +60,7 @@ class ImportVerilogParameters(object):
'''
if parameters:
self.parameters=parameters.copy()
self.parseRawParameters()
if defines:
self.defines=defines.copy()
if rootPath:
......@@ -249,7 +263,8 @@ class ImportVerilogParameters(object):
Adds parsed parameters to the dictionary
'''
def readParameterPortList(self,path,portMode=True):
print ("readParameterPortList:Processing %s"%(path))
if (self.verbose>2):
print ("readParameterPortList:Processing %s"%(path))
with open (path, "r") as myfile: #with will close file when done
text=myfile.read()
# remove /* */ comments
......@@ -339,13 +354,14 @@ class ImportVerilogParameters(object):
for line in preprocessedLines:
if line[-1] == ";":
portMode=False
print ("portMode is "+str(portMode))
if (self.verbose>2):
print ("portMode is "+str(portMode))
try:
if portMode and (preprocessedLines[0][0]==","):
preprocessedLines.insert(0,preprocessedLines.pop(0)[1:])
except:
pass
print("No preprocessed lines left")
if (self.verbose>2):
print("No preprocessed lines left")
while preprocessedLines:
# print("A: len(preprocessedLines)=%d, first is %s"%(len(preprocessedLines),preprocessedLines[0]))
line= preprocessedLines.pop(0)
......@@ -480,18 +496,30 @@ class ImportVerilogParameters(object):
# process expression here, for now - just use expression string
ev= self.parseExpression(expLine)
if ev is None:
self.parameters[parName]= (expLine,parType)
self.parameters[parName]= (expLine,parType,expLine)
else:
if not parType:
parType=ev[1]
# self.parameters[parName]= (ev[0],parType)
self.parameters[parName]= (ev[0],parType+" raw="+expLine)
self.parameters[parName]= (ev[0],parType,expLine)
# if portMode: # while True:
if portMode or (termChar == ";"): # while True:
break;
# print ("======= Parameters =======")
# for par in self.parameters:
# print (par+": "+self.parameters[par])
# print (par+": "+self.parameters[par])
def parseRawParameters(self):
for parName in self.parameters:
valTyp= self.parameters[parName]
if (not valTyp[1]) or (valTyp[1]=="RAW"):
ev= self.parseExpression(valTyp[0])
# print ("valTyp="+str(valTyp))
# print ("ev="+str(ev))
if ev:
self.parameters[parName]= (ev[0],ev[1],valTyp[0])
if parName == "VERBOSE":
self.verbose=ev[0]
'''
get parameter dictionary
'''
......
py393/test1.py
View file @ 63ff2819
......@@ -38,6 +38,7 @@ from argparse import ArgumentParser
from argparse import RawDescriptionHelpFormatter
from import_verilog_parameters import ImportVerilogParameters
from import_verilog_parameters import VerilogParameters
__all__ = []
__version__ = 0.1
__date__ = '2015-03-01'
......@@ -89,41 +90,36 @@ def main(argv=None): # IGNORE:C0111
USAGE
''' % (program_shortdesc, __author__,str(__date__))
# parser = argparse.ArgumentParser()
# parser = ArgumentParser()
'''
parser = ArgumentParser(description=program_license, formatter_class=RawDescriptionHelpFormatter)
parser.add_argument("-v", "--verbose", dest="verbose", action="count", help="set verbosity level [default: %(default)s]")
parser.add_argument('-V', '--version', action='version', version=program_version_message)
parser.add_argument(dest="paths", help="Verilog include files with parameter definitions [default: %(default)s]", metavar="path", nargs='+')
args = parser.parse_args()
#print argv
print args
print ("***1.25")
return
'''
ivp= ImportVerilogParameters (None,None)
preDefines={}
preParameters={}
try:
# Setup argument parser
parser = ArgumentParser(description=program_license, formatter_class=RawDescriptionHelpFormatter)
parser.add_argument("-v", "--verbose", dest="verbose", action="count", help="set verbosity level [default: %(default)s]")
parser.add_argument('-V', '--version', action='version', version=program_version_message)
parser.add_argument(dest="paths", help="Verilog include files with parameter definitions [default: %(default)s]", metavar="path", nargs='+')
parser.add_argument( dest="paths", help="Verilog include files with parameter definitions [default: %(default)s]", metavar="path", nargs='*')
parser.add_argument("-d", "--define", dest="defines", action="append", help="Define macro(s)" )
parser.add_argument("-p", "--parameter", dest="parameters", action="append", help="Define parameter(s) as name=value" )
# Process arguments
args = parser.parse_args()
paths = args.paths
verbose = args.verbose
if args.defines:
for predef in args.defines:
kv=predef.split("=")
if len(kv)<2:
kv.append("")
preDefines[kv[0].strip("`")]=kv[1]
if verbose > 0:
print("Verbose mode on")
# if inpat and expat and inpat == expat:
# raise CLIError("include and exclude pattern are equal! Nothing will be processed.")
# for path in paths:
# ### do something with inpath ###
# ivp.readParameterPortList(path)
# return 0
# print("Verbose mode on "+hex(verbose))
args.parameters.append('VERBOSE=%d'%verbose) # add as verilog parameter
if args.parameters:
for prePars in args.parameters:
kv=prePars.split("=")
if len(kv)>1:
preParameters[kv[0]]=(kv[1],"RAW",kv[1]) # todo - need to go through the parser
except KeyboardInterrupt:
### handle keyboard interrupt ###
return 0
......@@ -134,23 +130,34 @@ USAGE
sys.stderr.write(program_name + ": " + repr(e) + "\n")
sys.stderr.write(indent + " for help use --help")
return 2
# Take out from the try/except for debugging
# Take out from the try/except for debugging
ivp= ImportVerilogParameters(preParameters,preDefines)
for path in paths:
### do something with inpath ###
ivp.readParameterPortList(path)
defines= ivp.getDefines()
print ("======= Extracted defines =======")
for macro in defines:
print ("`"+macro+": "+defines[macro])
parameters=ivp.getParameters()
print ("======= Parameters =======")
for par in parameters:
try:
print (par+" = "+hex(parameters[par][0])+" (type = "+parameters[par][1]+")")
except:
print (par+" = "+str(parameters[par][0])+" (type = "+parameters[par][1]+")")
vpars=VerilogParameters(parameters)
if verbose > 3:
defines= ivp.getDefines()
print ("======= Extracted defines =======")
for macro in defines:
print ("`"+macro+": "+defines[macro])
print ("======= Parameters =======")
for par in parameters:
try:
print (par+" = "+hex(parameters[par][0])+" (type = "+parameters[par][1]+" raw = "+parameters[par][2]+")")
except:
print (par+" = "+str(parameters[par][0])+" (type = "+parameters[par][1]+" raw = "+parameters[par][2]+")")
print("vpars.VERBOSE="+str(vpars.VERBOSE))
print("vpars.VERBOSE__TYPE="+str(vpars.VERBOSE__TYPE))
print("vpars.VERBOSE__RAW="+str(vpars.VERBOSE__RAW))
print (VerilogParameters.__dict__)
vpars1=VerilogParameters()
print("vpars1.VERBOSE="+str(vpars1.VERBOSE))
print("vpars1.VERBOSE__TYPE="+str(vpars1.VERBOSE__TYPE))
print("vpars1.VERBOSE__RAW="+str(vpars1.VERBOSE__RAW))
return 0
......@@ -158,7 +165,6 @@ if __name__ == "__main__":
if DEBUG:
# sys.argv.append("-h")
sys.argv.append("-v")
# sys.argv.append("-r")
if TESTRUN:
import doctest
doctest.testmod()
......
py393/x393_axi_control_status.py 0 → 100644
View file @ 63ff2819
This diff is collapsed.
py393/x393_mem.py 0 → 100644
View file @ 63ff2819
'''
# Copyright (C) 2015, Elphel.inc.
# Memory read/write functions
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
@author: Andrey Filippov
@copyright: 2015 Elphel, Inc.
@license: GPLv3.0+
@contact: andrey@elphel.coml
@deffield updated: Updated
'''
__author__ = "Andrey Filippov"
__copyright__ = "Copyright 2015, Elphel, Inc."
__license__ = "GPL"
__version__ = "3.0+"
__maintainer__ = "Andrey Filippov"
__email__ = "andrey@elphel.com"
__status__ = "Development"
from __future__ import print_function
import mmap
#import sys
import struct
class X393Mem(object):
'''
classdocs
'''
DRY_MODE= False # True
PAGE_SIZE=4096
DEBUG_MODE=1
ENDIAN="<" # little, ">" for big
AXI_SLAVE0_BASE=0x40000000
def __init__(self, debug_mode=1,dry_mode=False):
self.DEBUG_MODE=debug_mode
self.DRY_MODE=dry_mode
def write_mem (self,addr, data):
if self.DRY_MODE:
print ("write_mem(0x%x,0x%x)"%(addr,data))
return
with open("/dev/mem", "r+b") as f:
page_addr=addr & (~(self.PAGE_SIZE-1))
page_offs=addr-page_addr
if (page_addr>=0x80000000):
page_addr-= (1<<32)
mm = mmap.mmap(f.fileno(), self.PAGE_SIZE, offset=page_addr)
packedData=struct.pack(self.ENDIAN+"L",data)
d=struct.unpack(self.ENDIAN+"L",packedData)[0]
mm[page_offs:page_offs+4]=packedData
if self.DEBUG_MODE > 2:
print ("0x%08x <== 0x%08x (%d)"%(addr,d,d))
mm.close()
'''
if MONITOR_EMIO and VEBOSE:
gpio0=read_mem (0xe000a068)
gpio1=read_mem (0xe000a06c)
print("GPIO: %04x %04x %04x %04x"%(gpio1>>16, gpio1 & 0xffff, gpio0>>16, gpio0 & 0xffff))
if ((gpio0 & 0xc) != 0xc) or ((gpio0 & 0xff00) != 0):
print("******** AXI STUCK ************")
exit (0)
'''
def read_mem (self,addr):
if self.DRY_MODE:
print ("read_mem(0x%x)"%(addr))
return
with open("/dev/mem", "r+b") as f:
page_addr=addr & (~(self.PAGE_SIZE-1))
page_offs=addr-page_addr
if (page_addr>=0x80000000):
page_addr-= (1<<32)
mm = mmap.mmap(f.fileno(), self.PAGE_SIZE, offset=page_addr)
data=struct.unpack(self.ENDIAN+"L",mm[page_offs:page_offs+4])
d=data[0]
if self.DEBUG_MODE > 2:
print ("0x%08x ==> 0x%08x (%d)"%(addr,d,d))
return d
# mm.close() #probably not needed with "with"
'''
Read/write slave AXI using byte addresses relative to the AXI memory reagion
'''
def axi_write_single(self,addr,data):
self.write_mem(self.AXI_SLAVE0_BASE+addr,data)
def axi_read_addr(self,addr):
return self.read_mem(self.AXI_SLAVE0_BASE+addr)
'''
Read/write slave AXI using 32-bit word addresses (same as in Verilog code)
'''
def axi_write_single_w(self,addr,data):
self.axi_write_single(addr<<2,data)
def axi_read_addr_w(self,addr):
return self.axi_read_addr(addr<<2)
\ No newline at end of file
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