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x393
Commit 9326e242 authored by Andrey Filippov's avatar Andrey Filippov
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debugging

parent 27a6599b
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Showing with 66 additions and 45 deletions
py393/test_mcntrl.py
View file @ 9326e242
......@@ -89,7 +89,7 @@ def extractTasks(obj,inst):
func_args=obj.__dict__[name].func_code.co_varnames[1:obj.__dict__[name].func_code.co_argcount]
callableTasks[name]={'func':obj.__dict__[name],'args':func_args,'inst':inst,'docs':inspect.getdoc(obj.__dict__[name])}
def execTask(commandLine):
# result=None
result=None
cmdList=commandLine #.split()
try:
funcName=cmdList[0]
......@@ -106,6 +106,7 @@ def execTask(commandLine):
result = callableTasks[funcName]['func'](callableTasks[funcName]['inst'],*funcArgs)
except Exception as e:
print ('Error while executing %s %s'%(funcName,str(funcArgs)))
print ("QUIET=%d"%QUIET)
try:
funcFArgs= callableTasks[funcName]['args']
except:
......@@ -139,7 +140,7 @@ def getFuncArgsString(name):
def main(argv=None): # IGNORE:C0111
'''Command line options.'''
global QUIET
if argv is None:
argv = sys.argv
else:
......@@ -187,7 +188,11 @@ USAGE
# Process arguments
args = parser.parse_args()
QUIET = args.exceptions == 0
if not args.exceptions:
args.exceptions=0
QUIET = (1,0)[args.exceptions]
# print ("args.exception=%d, QUIET=%d"%(args.exceptions,QUIET))
if not args.simulated:
if not os.path.exists("/dev/xdevcfg"):
args.simulated=True
......@@ -315,11 +320,13 @@ USAGE
extractTasks(x393_mcntrl_tests.X393McntrlTests,x393Tests)
#
"""
if verbose > 3:
funcName="read_mem"
funcArgs=[0x377,123]
print ('==== testing function : '+funcName+str(funcArgs)+' ====')
# execTask(commandLine)
try:
callableTasks[funcName]['func'](callableTasks[funcName]['inst'],*funcArgs)
except Exception as e:
......@@ -332,7 +339,7 @@ USAGE
sFuncArgs+=' <'+str(a)+'>'
print ("Usage:\n%s %s"%(funcName,sFuncArgs))
print ("exception message:"+str(e))
"""
for cmdLine in commands:
print ('Running task: '+str(cmdLine))
rslt= execTask(cmdLine)
......@@ -354,6 +361,8 @@ USAGE
sFuncArgs=getFuncArgsString(name)
print ("Usage: %s %s"%(name,sFuncArgs))
print ('\n"parameters" and "defines" list known defined parameters and macros')
print ("args.exception=%d, QUIET=%d"%(args.exceptions,QUIET))
elif (len(line) > len("help")) and (line[:len("help")]=='help'):
helpFilter=line[len('help'):].strip()
try:
......
py393/verilog_utils.py
View file @ 9326e242
......@@ -65,30 +65,39 @@ def getParWidthLo(bitRange):
return (32,0)
else:
try:
# print(">>bitRange=%s"%bitRange,end=" ")
if bitRange[0] != '[':
# print("\nbitRange[0]=%s"%(bitRange[0]))
return None # may also fail through except if bitRange=""
startPosHi=1
endPosHi=bitRange.index(':')
startPosLo=endPosHi+1
endPosLo=bitRange.index(']')
# print("startPosHi=%d, endPosHi=%d, startPosLo=%d, endPosLo=%d"%(startPosHi,endPosHi,startPosLo,endPosLo))
if endPosHi<0:
endPosHi=endPosLo
startPosLo=-1
except:
return None
# print("1: startPosHi=%d, endPosHi=%d, startPosLo=%d, endPosLo=%d"%(startPosHi,endPosHi,startPosLo,endPosLo))
if endPosHi <0:
return None # no ":" or terminating "]"
loBit=0
try:
if startPosLo >0:
loBit=int(bitRange[startPosLo,endPosLo])
width=int(bitRange[startPosHi,endPosHi])-loBit+1
if startPosLo > 0:
# print("2. startPosHi=%d, endPosHi=%d, startPosLo=%d, endPosLo=%d"%(startPosHi,endPosHi,startPosLo,endPosLo))
# print("bitRange[startPosLo,endPosLo]=%s"%(bitRange[startPosLo:endPosLo]))
# print("bitRange[startPosHi,endPosHi]=%s"%(bitRange[startPosHi:endPosHi]))
loBit=int(bitRange[startPosLo:endPosLo])
width=int(bitRange[startPosHi:endPosHi])-loBit+1
return (width,loBit)
except:
return None # could not parse: undefined width
def getParWidth(bitRange):
wl=getParWidthLo(bitRange)
print("\n***wl=%s, bitRange=%s"%(str(wl),str(bitRange)))
# print("bitRange=%s wl=%s"%(bitRange,str(wl)))
if not wl:
return None
......
py393/x393_mcntrl_tests.py
View file @ 9326e242
......@@ -83,13 +83,13 @@ class X393McntrlTests(object):
<chn_reset>): immediately reset all the internal circuitry
"""
return concat (
return concat ((
((0,1)[byte32], 1), # byte32,
((0,1)[keep_open],1), # keep_open,
(extra_pages, 2), # extra_pages,
((0,1)[write_mem],1), # write_mem,
((0,1)[enable], 1), #enable,
((1,0)[chn_reset],1)) # ~chn_reset};
((1,0)[chn_reset],1)))# ~chn_reset};
def func_encode_mode_scanline(self, # function [4:0]
extra_pages, # input [1:0] extra_pages; # number of extra pages that need to stay (not to be overwritten) in the buffer
......@@ -112,7 +112,7 @@ class X393McntrlTests(object):
((0,1)[enable], 1), #enable,
((1,0)[chn_reset],1)) # ~chn_reset};
def task_set_up(self,
set_per_pin_delays):
set_per_pin_delays=0):
"""
Initial setup of the memory controller, including:
tristate patterns
......@@ -545,18 +545,18 @@ class X393McntrlTests(object):
self.x393_axi_tasks.write_contol_register(start_addr + self.MCNTRL_TILED_FRAME_FULL_WIDTH,
self.FRAME_FULL_WIDTH)
self.x393_axi_tasks.write_contol_register(start_addr + self.MCNTRL_TILED_WINDOW_WH,
concat((window_height,16),
(window_width, 16))) # {window_height,window_width});
concat(((window_height,16),
(window_width, 16)))) # {window_height,window_width});
self.x393_axi_tasks.write_contol_register(start_addr + self.MCNTRL_TILED_WINDOW_X0Y0,
concat((window_top, 16),
(window_left, 16))) # {window_top,window_left});
concat(((window_top, 16),
(window_left, 16)))) # {window_top,window_left});
self.x393_axi_tasks.write_contol_register(start_addr + self.MCNTRL_TILED_WINDOW_STARTXY,
concat((self.TILED_STARTY, 16),
(self.TILED_STARTX, 16))) # TILED_STARTX+(TILED_STARTY<<16));
concat(((self.TILED_STARTY, 16),
(self.TILED_STARTX, 16)))) # TILED_STARTX+(TILED_STARTY<<16));
self.x393_axi_tasks.write_contol_register(start_addr + self.MCNTRL_TILED_TILE_WHS,
concat((tile_vstep, 8),
(tile_height, 8),
(tile_width, 8))) # {8'b0,tile_vstep,tile_height,tile_width});#tile_width+(tile_height<<8)+(tile_vstep<<16));
concat(((tile_vstep, 8),
(tile_height, 8),
(tile_width, 8)))) # {8'b0,tile_vstep,tile_height,tile_width});#tile_width+(tile_height<<8)+(tile_vstep<<16));
self.x393_axi_tasks.write_contol_register(start_addr + self.MCNTRL_TILED_MODE, mode);# set mode register: {extra_pages[1:0],enable,!reset}
self.x393_axi_tasks.configure_channel_priority(channel,0) # lowest priority channel 3
self.x393_axi_tasks.enable_memcntrl_en_dis(channel,1);
......@@ -672,18 +672,18 @@ class X393McntrlTests(object):
self.x393_axi_tasks.write_contol_register(start_addr + self.MCNTRL_TILED_FRAME_FULL_WIDTH,
self.FRAME_FULL_WIDTH)
self.x393_axi_tasks.write_contol_register(start_addr + self.MCNTRL_TILED_WINDOW_WH,
concat((window_height,16),
(window_width, 16))) # {window_height,window_width});
concat(((window_height,16),
(window_width, 16)))) # {window_height,window_width});
self.x393_axi_tasks.write_contol_register(start_addr + self.MCNTRL_TILED_WINDOW_X0Y0,
concat((window_top, 16),
(window_left, 16))) # {window_top,window_left});
concat(((window_top, 16),
(window_left, 16)))) # {window_top,window_left});
self.x393_axi_tasks.write_contol_register(start_addr + self.MCNTRL_TILED_WINDOW_STARTXY,
concat((self.TILED_STARTY, 16),
(self.TILED_STARTX, 16))) # TILED_STARTX+(TILED_STARTY<<16));
concat(((self.TILED_STARTY, 16),
(self.TILED_STARTX, 16)))) # TILED_STARTX+(TILED_STARTY<<16));
self.x393_axi_tasks.write_contol_register(start_addr + self.MCNTRL_TILED_TILE_WHS,
concat((tile_vstep, 8),
(tile_height, 8),
(tile_width, 8))) # {8'b0,tile_vstep,tile_height,tile_width});#tile_width+(tile_height<<8)+(tile_vstep<<16));
concat(((tile_vstep, 8),
(tile_height, 8),
(tile_width, 8)))) # {8'b0,tile_vstep,tile_height,tile_width});#tile_width+(tile_height<<8)+(tile_vstep<<16));
self.x393_axi_tasks.write_contol_register(start_addr + self.MCNTRL_TILED_MODE, mode);# set mode register: {extra_pages[1:0],enable,!reset}
self.x393_axi_tasks.configure_channel_priority(channel,0) # lowest priority channel 3
self.x393_axi_tasks.enable_memcntrl_en_dis(channel,1);
......
py393/x393_mcntrl_timing.py
View file @ 9326e242
......@@ -133,8 +133,8 @@ class X393McntrlTiming(object):
"""
if self.DEBUG_MODE > 1:
print("SET DQ IDELAY=0x%x"%delay)
self.x393_axi_tasks.axi_set_multiple_delays(self.LD_DLY_LANE0_IDELAY, 8, delay)
self.x393_axi_tasks.axi_set_multiple_delays(self.LD_DLY_LANE1_IDELAY, 8, delay)
self.axi_set_multiple_delays(self.LD_DLY_LANE0_IDELAY, 8, delay)
self.axi_set_multiple_delays(self.LD_DLY_LANE1_IDELAY, 8, delay)
self.x393_axi_tasks.write_contol_register (self.DLY_SET,0);# // set all delays
def axi_set_dq_odelay(self,
......@@ -145,8 +145,8 @@ class X393McntrlTiming(object):
"""
if self.DEBUG_MODE > 1:
print("SET DQ ODELAY=0x%x"%delay)
self.x393_axi_tasks.axi_set_multiple_delays(self.LD_DLY_LANE0_ODELAY, 8, delay);
self.x393_axi_tasks.axi_set_multiple_delays(self.LD_DLY_LANE1_ODELAY, 8, delay);
self.axi_set_multiple_delays(self.LD_DLY_LANE0_ODELAY, 8, delay);
self.axi_set_multiple_delays(self.LD_DLY_LANE1_ODELAY, 8, delay);
self.x393_axi_tasks.write_contol_register(self.DLY_SET,0); # set all delays
def axi_set_dqs_idelay(self,
......@@ -157,8 +157,8 @@ class X393McntrlTiming(object):
"""
if self.DEBUG_MODE > 1:
print("SET DQS IDELAY=0x%x"%delay)
self.x393_axi_tasks.axi_set_multiple_delays(self.LD_DLY_LANE0_IDELAY + 8, 1, delay)
self.x393_axi_tasks.axi_set_multiple_delays(self.LD_DLY_LANE1_IDELAY + 8, 1, delay)
self.axi_set_multiple_delays(self.LD_DLY_LANE0_IDELAY + 8, 1, delay)
self.axi_set_multiple_delays(self.LD_DLY_LANE1_IDELAY + 8, 1, delay)
self.x393_axi_tasks.write_contol_register(self.DLY_SET,0); # set all delays
def axi_set_dqs_odelay(self,
......@@ -169,8 +169,8 @@ class X393McntrlTiming(object):
"""
if self.DEBUG_MODE > 1:
print("SET DQS ODELAY=0x%x"%delay)
self.x393_axi_tasks.axi_set_multiple_delays(self.LD_DLY_LANE0_ODELAY + 8, 1, delay)
self.x393_axi_tasks.axi_set_multiple_delays(self.LD_DLY_LANE1_ODELAY + 8, 1, delay)
self.axi_set_multiple_delays(self.LD_DLY_LANE0_ODELAY + 8, 1, delay)
self.axi_set_multiple_delays(self.LD_DLY_LANE1_ODELAY + 8, 1, delay)
self.x393_axi_tasks.write_contol_register(self.DLY_SET,0); # set all delays
def axi_set_dm_odelay (self,
......@@ -181,8 +181,8 @@ class X393McntrlTiming(object):
"""
if self.DEBUG_MODE > 1:
print("SET DQM IDELAY=0x%x"%delay)
self.x393_axi_tasks.axi_set_multiple_delays(self.LD_DLY_LANE0_ODELAY + 9, 1, delay)
self.x393_axi_tasks.axi_set_multiple_delays(self.LD_DLY_LANE1_ODELAY + 9, 1, delay)
self.axi_set_multiple_delays(self.LD_DLY_LANE0_ODELAY + 9, 1, delay)
self.axi_set_multiple_delays(self.LD_DLY_LANE1_ODELAY + 9, 1, delay)
self.x393_axi_tasks.write_contol_register(self.DLY_SET,0) # set all delays
def axi_set_cmda_odelay(self,
......@@ -193,7 +193,7 @@ class X393McntrlTiming(object):
"""
if self.DEBUG_MODE > 1:
print("SET COMMAND and ADDRESS ODELAY=0x%x"%delay)
self.x393_axi_tasks.axi_set_multiple_delays(self.LD_DLY_CMDA, 32, delay);
self.axi_set_multiple_delays(self.LD_DLY_CMDA, 32, delay);
self.x393_axi_tasks.write_contol_register(self.DLY_SET,0) # set all delays
def axi_set_multiple_delays(self,
......@@ -246,13 +246,16 @@ class X393McntrlTiming(object):
Set sequencer patterns for the tristate ON/OFF (defined by parameters)
"""
# may fail if some of the parameters used have undefined width
delays=concat((0,16), # {16'h0,
(self.DQSTRI_LAST, getParWidth(self.DQSTRI_LAST__TYPE)), # DQSTRI_LAST,
(self.DQSTRI_FIRST,getParWidth(self.DQSTRI_FIRST__TYPE)), # DQSTRI_FIRST,
(self.DQTRI_LAST, getParWidth(self.DQTRI_LAST_FIRST__TYPE)), # DQTRI_LAST,
(self.DQTRI_FIRST, getParWidth(self.DQTRI_FIRST__TYPE)) # DQTRI_FIRST});
)
print("DQTRI_FIRST=%s, DQTRI_FIRST__TYPE=%s"%(str(self.DQTRI_FIRST),str(self.DQTRI_FIRST__TYPE)))
print("DQTRI_LAST=%s, DQTRI_LAST__TYPE=%s"%(str(self.DQTRI_LAST),str(self.DQTRI_LAST__TYPE)))
delays=concat(((0,16), # {16'h0,
(self.DQSTRI_LAST, getParWidth(self.DQSTRI_LAST__TYPE)), # DQSTRI_LAST,
(self.DQSTRI_FIRST,getParWidth(self.DQSTRI_FIRST__TYPE)), # DQSTRI_FIRST,
(self.DQTRI_LAST, getParWidth(self.DQTRI_LAST__TYPE)), # DQTRI_LAST,
(self.DQTRI_FIRST, getParWidth(self.DQTRI_FIRST__TYPE))) # DQTRI_FIRST});
)[0]
if self.DEBUG_MODE > 1:
print("SET TRISTATE PATTERNS, combined delays=%s"%str(delays))
print("SET TRISTATE PATTERNS, combined delays=0x%x"%delays)
self.x393_axi_tasks.write_contol_register(self.MCONTR_PHY_16BIT_ADDR +self.MCONTR_PHY_16BIT_PATTERNS_TRI, delays) # DQSTRI_LAST, DQSTRI_FIRST, DQTRI_LAST, DQTRI_FIRST});
......
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