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Elphel
x393
Commits
9acfc5c3
Commit
9acfc5c3
authored
Feb 10, 2015
by
Andrey Filippov
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removed some old temporary files
parent
466a4a4e
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test_dqs.v
memctrl/phy/test_dqs.v
+0
-116
test_dqs01.v
memctrl/phy/test_dqs01.v
+0
-59
test_dqs01_placement.xdc
memctrl/phy/test_dqs01_placement.xdc
+0
-95
test_dqs02.v
memctrl/phy/test_dqs02.v
+0
-154
test_dqs02_placement.xdc
memctrl/phy/test_dqs02_placement.xdc
+0
-82
test_dqs03.v
memctrl/phy/test_dqs03.v
+0
-83
test_dqs03_placement.xdc
memctrl/phy/test_dqs03_placement.xdc
+0
-152
test_dqs04.v
memctrl/phy/test_dqs04.v
+0
-129
test_dqs04_placement.xdc
memctrl/phy/test_dqs04_placement.xdc
+0
-152
test_dqs05.v
memctrl/phy/test_dqs05.v
+0
-174
test_dqs05_placement.xdc
memctrl/phy/test_dqs05_placement.xdc
+0
-154
test_dqs06.v
memctrl/phy/test_dqs06.v
+0
-74
test_dqs06_placement.xdc
memctrl/phy/test_dqs06_placement.xdc
+0
-102
test_dqs07.v
memctrl/phy/test_dqs07.v
+0
-108
test_dqs07_placement.xdc
memctrl/phy/test_dqs07_placement.xdc
+0
-104
test_phy_top_01.xdc
memctrl/phy/test_phy_top_01.xdc
+0
-236
No files found.
memctrl/phy/test_dqs.v
deleted
100644 → 0
View file @
466a4a4e
/*******************************************************************************
* Module: test_dqs
* Date:2014-04-26
* Author: Andrey Filippov
* Description: Testing DQS implementation
*
* Copyright (c) 2014 Elphel, Inc.
* test_dqs.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* test_dqs.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale
1
ns
/
1
ps
module
test_dqs
(
input
rst
,
// reset
input
refclk
,
// 200MHz/300MHz for delay calibration
input
clk_in
,
input
set
,
input
ld_dly_data
,
input
ld_dly_tri
,
input
[
7
:
0
]
dly_data
,
input
[
3
:
0
]
data_in
,
input
[
3
:
0
]
tri_in
,
inout
dqs
,
inout
ndqs
,
output
dqs_received
,
output
dly_ready
,
// input dqs_tri_a,
output
dqs_tri
)
;
wire
refclk_b
=
refclk
;
// use buffer
wire
clk
,
clk_div
;
//wire dqs_data,dqs_tri; // after odelay
wire
dqs_data
;
// after odelay
wire
pre_dqs_data
,
pre_dqs_tri
;
// before odelay
BUFR
#(
.
BUFR_DIVIDE
(
"2"
))
clk_div_i
(
.
I
(
clk_in
)
,.
O
(
clk_div
)
,.
CLR
(
rst
)
,
.
CE
(
1'b1
))
;
BUFR
#(
.
BUFR_DIVIDE
(
"BYPASS"
))
clk_i
(
.
I
(
clk_in
)
,.
O
(
clk
)
,
.
CLR
(
1'b0
)
,.
CE
(
1'b1
))
;
oserdes_mem
oserdes_dqs_i
(
.
clk
(
clk
)
,
// serial output clock
.
clk_div
(
clk_div
)
,
// oclk divided by 2, front aligned
.
rst
(
rst
)
,
// reset
.
din
(
data_in
)
,
// parallel data in
.
tin
(
tri_in
)
,
// parallel tri-state in
.
dout_dly
()
,
// data out to be connected to odelay input
.
dout_iob
(
pre_dqs_data
)
,
// data out to be connected directly to the output buffer
.
tout_dly
()
,
// tristate out to be connected to odelay input
.
tout_iob
(
pre_dqs_tri
)
// tristate out to be connected directly to the tristate control of the output buffer
)
;
idelay_ctrl
#
(
.
IODELAY_GRP
(
"IODELAY_MEMORY"
)
)
idelay_ctrl_i
(
.
refclk
(
refclk_b
)
,
.
rst
(
rst
)
,
.
rdy
(
dly_ready
)
)
;
odelay_fine_pipe
#
(
.
IODELAY_GRP
(
"IODELAY_MEMORY"
)
,
.
DELAY_VALUE
(
0
)
,
.
REFCLK_FREQUENCY
(
300.0
)
,
.
HIGH_PERFORMANCE_MODE
(
"FALSE"
)
)
dqs_data_dly_i
(
.
clk
(
clk_div
)
,
.
rst
(
rst
)
,
.
set
(
set
)
,
.
ld
(
ld_dly_data
)
,
.
delay
(
dly_data
)
,
.
data_in
(
pre_dqs_data
)
,
.
data_out
(
dqs_data
)
)
;
odelay_fine_pipe
#
(
.
IODELAY_GRP
(
"IODELAY_MEMORY"
)
,
.
DELAY_VALUE
(
0
)
,
.
REFCLK_FREQUENCY
(
300.0
)
,
.
HIGH_PERFORMANCE_MODE
(
"FALSE"
)
)
dqs_tri_dly_i
(
.
clk
(
clk_div
)
,
.
rst
(
rst
)
,
.
set
(
set
)
,
.
ld
(
ld_dly_tri
)
,
.
delay
(
dly_data
)
,
.
data_in
(
pre_dqs_tri
)
,
.
data_out
(
dqs_tri
)
)
;
//wire dqs_tri_a;
//(* keep = "true" *) BUF buf0_i(.O(dqs_tri_a), .I(dqs_tri));
IOBUFDS
#(
.
DQS_BIAS
(
"FALSE"
)
,
.
IBUF_LOW_PWR
(
"TRUE"
)
,
.
IOSTANDARD
(
"DEFAULT"
)
,
.
SLEW
(
"SLOW"
)
)
iobufs_dqs_i
(
.
O
(
dqs_received
)
,
.
IO
(
dqs
)
,
.
IOB
(
ndqs
)
,
.
I
(
dqs_data
)
,
// .T(dqs_tri_a));
.
T
(
1'b0
))
;
endmodule
memctrl/phy/test_dqs01.v
deleted
100644 → 0
View file @
466a4a4e
/*******************************************************************************
* Module: test_dqs01
* Date:2014-04-26
* Author: Andrey Filippov
* Description: Testing DQS implementation
*
* Copyright (c) 2014 Elphel, Inc.
* test_dqs01.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* test_dqs01.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale
1
ns
/
1
ps
module
test_dqs01
(
input
[
1
:
0
]
dqs_data
,
inout
[
1
:
0
]
dqs
,
inout
[
1
:
0
]
ndqs
,
output
[
1
:
0
]
dqs_received
,
input
[
1
:
0
]
dqs_tri
)
;
IOBUFDS
#(
.
DQS_BIAS
(
"FALSE"
)
,
.
IBUF_LOW_PWR
(
"TRUE"
)
,
.
IOSTANDARD
(
"DEFAULT"
)
,
.
SLEW
(
"SLOW"
)
)
iobufs_dqs_i0
(
.
O
(
dqs_received
[
0
])
,
.
IO
(
dqs
[
0
])
,
.
IOB
(
ndqs
[
0
])
,
.
I
(
dqs_data
[
0
])
,
.
T
(
dqs_tri
[
0
]))
;
IOBUFDS
#(
.
DQS_BIAS
(
"FALSE"
)
,
.
IBUF_LOW_PWR
(
"TRUE"
)
,
.
IOSTANDARD
(
"DEFAULT"
)
,
.
SLEW
(
"SLOW"
)
)
iobufs_dqs_i1
(
.
O
(
dqs_received
[
1
])
,
.
IO
(
dqs
[
1
])
,
.
IOB
(
ndqs
[
1
])
,
.
I
(
dqs_data
[
1
])
,
.
T
(
dqs_tri
[
1
]))
;
endmodule
memctrl/phy/test_dqs01_placement.xdc
deleted
100644 → 0
View file @
466a4a4e
set_property PACKAGE_PIN N7 [get_ports {dqs}]
set_property SLEW FAST [get_ports {dqs}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {dqs}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dqs}]
set_property PACKAGE_PIN N6 [get_ports {ndqs}]
set_property SLEW FAST [get_ports {ndqs}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ndqs}]
# input dqs_data,
# inout dqs,
# inout ndqs,
# output dqs_received,
# input dqs_tri
#set_property IOSTANDARD LVCMOS15 [get_ports {rst}]
#set_property IOSTANDARD LVCMOS15 [get_ports {refclk}]
#set_property IOSTANDARD LVCMOS15 [get_ports {clk_in}]
#set_property IOSTANDARD LVCMOS15 [get_ports {set}]
#set_property IOSTANDARD LVCMOS15 [get_ports {ld_dly_data}]
#set_property IOSTANDARD LVCMOS15 [get_ports {ld_dly_tri}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[7]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[6]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[5]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[4]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[3]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[2]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[1]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[0]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {data_in[3]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {data_in[2]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {data_in[1]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {data_in[0]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[3]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[2]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[1]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dqs_received}]
set_property PACKAGE_PIN K4 [get_ports {dqs_received}]
set_property IOSTANDARD LVCMOS15 [get_ports {dqs_data}]
set_property PACKAGE_PIN K6 [get_ports {dqs_data}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_ready}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dqs_date}]
set_property IOSTANDARD LVCMOS15 [get_ports {dqs_tri}]
set_property PACKAGE_PIN K7 [get_ports {dqs_tri}]
# input rst, // reset
# input refclk, // 200MHz/300MHz for delay calibration
# input clk_in,
# input set,
# input ld_dly_data,
# input ld_dly_tri,
# input [7:0] dly_data,
# input [3:0] data_in,
# input [3:0] tri_in,
# inout dqs,
# inout ndqs,
# output dqs_received,
# output dly_ready,
# input dqs_tri_a,
# output dqs_tri
#set_property PACKAGE_PIN A1 [get_ports {COUNT[2]}]
#set_property PACKAGE_PIN B2 [get_ports {COUNT[1]}]
#set_property PACKAGE_PIN C2 [get_ports {COUNT[0]}]
#set_property PULLUP true [get_ports {COUNT[3]}]
#set_property PULLUP true [get_ports {COUNT[2]}]
#set_property PULLUP true [get_ports {COUNT[1]}]
#set_property PULLUP true [get_ports {COUNT[0]}]
#set_property PACKAGE_PIN A4 [get_ports ENABLE]
#set_property PACKAGE_PIN B4 [get_ports RESET]
#set_property PACKAGE_PIN C1 [get_ports CLK]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CLK_IBUF]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[3]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[2]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[1]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[0]}]
#set_property IOSTANDARD LVCMOS18 [get_ports ENABLE]
#set_property IOSTANDARD LVCMOS18 [get_ports RESET]
#set_property IOSTANDARD LVCMOS18 [get_ports CLK]
set_property INTERNAL_VREF 0.750 [get_iobanks 34]
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
\ No newline at end of file
memctrl/phy/test_dqs02.v
deleted
100644 → 0
View file @
466a4a4e
/*******************************************************************************
* Module: test_dqs02
* Date:2014-04-26
* Author: Andrey Filippov
* Description: Testing DQS implementation
*
* Copyright (c) 2014 Elphel, Inc.
* test_dqs02.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* test_dqs02.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale
1
ns
/
1
ps
module
test_dqs02
(
input
rst
,
// reset
input
refclk
,
// 200MHz/300MHz for delay calibration
input
clk_in
,
// input set,
// input ld_dly_data,
// input ld_dly_tri,
// input [7:0] dly_data,
input
[
3
:
0
]
data_in
,
// input [3:0] tri_in,
inout
dqs
,
// inout ndqs,
output
dqs_received
,
output
dly_ready
// input dqs_tri_a,
// output dqs_tri
// output dqs_data
)
;
wire
refclk_b
=
refclk
;
// use buffer
wire
clk
,
clk_div
;
//wire dqs_data,dqs_tri; // after odelay
//wire dqs_data; // after odelay
//wire pre_dqs_data,pre_dqs_tri; // before odelay
wire
dqs_data
;
BUFR
#(
.
BUFR_DIVIDE
(
"2"
))
clk_div_i
(
.
I
(
clk_in
)
,.
O
(
clk_div
)
,.
CLR
(
rst
)
,
.
CE
(
1'b1
))
;
BUFR
#(
.
BUFR_DIVIDE
(
"BYPASS"
))
clk_i
(
.
I
(
clk_in
)
,.
O
(
clk
)
,
.
CLR
(
1'b0
)
,.
CE
(
1'b1
))
;
oserdes_mem
oserdes_dqs_i
(
.
clk
(
clk
)
,
// serial output clock
.
clk_div
(
clk_div
)
,
// oclk divided by 2, front aligned
.
rst
(
rst
)
,
// reset
.
din
(
data_in
)
,
// parallel data in
// .tin(tri_in), // parallel tri-state in
.
tin
()
,
// parallel tri-state in
.
dout_dly
()
,
//pre_dqs_data), // data out to be connected to odelay input
.
dout_iob
(
dqs_data
)
,
// data out to be connected directly to the output buffer
.
tout_dly
()
,
// tristate out to be connected to odelay input
// .tout_iob(pre_dqs_tri) // tristate out to be connected directly to the tristate control of the output buffer
.
tout_iob
()
// tristate out to be connected directly to the tristate control of the output buffer
)
;
idelay_ctrl
#
(
.
IODELAY_GRP
(
"IODELAY_MEMORY"
)
)
idelay_ctrl_i
(
.
refclk
(
refclk_b
)
,
.
rst
(
rst
)
,
.
rdy
(
dly_ready
)
)
;
/*
odelay_fine_pipe # (
.IODELAY_GRP("IODELAY_MEMORY"),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(300.0),
.HIGH_PERFORMANCE_MODE("FALSE")
) dqs_data_dly_i(
.clk(clk_div),
.rst(rst),
.set(set),
.ld(ld_dly_data),
.delay(dly_data),
.data_in(pre_dqs_data),
.data_out(dqs_data)
);
*/
/*
odelay_pipe # (
.IODELAY_GRP("IODELAY_MEMORY"),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(300.0),
.HIGH_PERFORMANCE_MODE("FALSE")
) dqs_data_dly_i(
.clk(clk_div),
.rst(rst),
.set(set),
.ld(ld_dly_data),
.delay(dly_data[7:3]),
.data_in(pre_dqs_data),
.data_out(dqs_data)
);
*/
/*
odelay_fine_pipe # (
.IODELAY_GRP("IODELAY_MEMORY"),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(300.0),
.HIGH_PERFORMANCE_MODE("FALSE")
) dqs_tri_dly_i(
.clk(clk_div),
.rst(rst),
.set(set),
.ld(ld_dly_tri),
.delay(dly_data),
.data_in(pre_dqs_tri),
.data_out(dqs_tri)
);
*/
//wire dqs_tri_a;
//(* keep = "true" *) BUF buf0_i(.O(dqs_tri_a), .I(dqs_tri));
/*
IOBUFDS #(
.DQS_BIAS("FALSE"),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
) iobufs_dqs_i (
.O(dqs_received),
.IO(dqs),
.IOB(ndqs),
.I(dqs_data),
// .T(dqs_tri));
.T());
*/
IOBUF
#(
// .DQS_BIAS("FALSE"),
.
IBUF_LOW_PWR
(
"TRUE"
)
,
.
IOSTANDARD
(
"DEFAULT"
)
,
.
SLEW
(
"SLOW"
)
)
iobufs_dqs_i
(
.
O
(
dqs_received
)
,
.
IO
(
dqs
)
,
.
I
(
dqs_data
)
,
// .T(dqs_tri));
.
T
(
dqs_data
))
;
endmodule
memctrl/phy/test_dqs02_placement.xdc
deleted
100644 → 0
View file @
466a4a4e
set_property PACKAGE_PIN N7 [get_ports {dqs}]
set_property SLEW FAST [get_ports {dqs}]
#set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {dqs}]
set_property IOSTANDARD LVCMOS15 [get_ports {dqs}]
#set_property PACKAGE_PIN N6 [get_ports {ndqs}]
#set_property SLEW FAST [get_ports {ndqs}]
#set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ndqs}]
set_property IOSTANDARD LVCMOS15 [get_ports {rst}]
set_property IOSTANDARD LVCMOS15 [get_ports {refclk}]
set_property IOSTANDARD LVCMOS15 [get_ports {clk_in}]
set_property IOSTANDARD LVCMOS15 [get_ports {set}]
set_property IOSTANDARD LVCMOS15 [get_ports {ld_dly_data}]
set_property IOSTANDARD LVCMOS15 [get_ports {ld_dly_tri}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[7]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[6]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[5]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[4]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[3]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[2]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[1]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {data_in[3]}]
set_property IOSTANDARD LVCMOS15 [get_ports {data_in[2]}]
set_property IOSTANDARD LVCMOS15 [get_ports {data_in[1]}]
set_property IOSTANDARD LVCMOS15 [get_ports {data_in[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[3]}]
set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[2]}]
set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[1]}]
set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dqs_received}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_ready}]
set_property IOSTANDARD LVCMOS15 [get_ports {dqs_tri_a}]
set_property IOSTANDARD LVCMOS15 [get_ports {dqs_tri}]
# input rst, // reset
# input refclk, // 200MHz/300MHz for delay calibration
# input clk_in,
# input set,
# input ld_dly_data,
# input ld_dly_tri,
# input [7:0] dly_data,
# input [3:0] data_in,
# input [3:0] tri_in,
# inout dqs,
# inout ndqs,
# output dqs_received,
# output dly_ready,
# input dqs_tri_a,
# output dqs_tri
#set_property PACKAGE_PIN A1 [get_ports {COUNT[2]}]
#set_property PACKAGE_PIN B2 [get_ports {COUNT[1]}]
#set_property PACKAGE_PIN C2 [get_ports {COUNT[0]}]
#set_property PULLUP true [get_ports {COUNT[3]}]
#set_property PULLUP true [get_ports {COUNT[2]}]
#set_property PULLUP true [get_ports {COUNT[1]}]
#set_property PULLUP true [get_ports {COUNT[0]}]
#set_property PACKAGE_PIN A4 [get_ports ENABLE]
#set_property PACKAGE_PIN B4 [get_ports RESET]
#set_property PACKAGE_PIN C1 [get_ports CLK]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CLK_IBUF]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[3]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[2]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[1]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[0]}]
#set_property IOSTANDARD LVCMOS18 [get_ports ENABLE]
#set_property IOSTANDARD LVCMOS18 [get_ports RESET]
#set_property IOSTANDARD LVCMOS18 [get_ports CLK]
set_property INTERNAL_VREF 0.750 [get_iobanks 34]
memctrl/phy/test_dqs03.v
deleted
100644 → 0
View file @
466a4a4e
/*******************************************************************************
* Module: test_dqs03
* Date:2014-04-26
* Author: Andrey Filippov
* Description: Testing DQS implementation
*
* Copyright (c) 2014 Elphel, Inc.
* test_dqs03.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* test_dqs03.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale
1
ns
/
1
ps
module
test_dqs03
(
input
dqs_data
,
inout
dqs
,
inout
ndqs
,
input
clk_in
,
input
clk_ref_in
,
input
rst
,
output
dqs_received
,
input
dqs_tri
,
output
dly_ready
,
input
[
4
:
0
]
dly_data
,
input
set
,
input
ld
)
;
//SuppressWarnings all
wire
clk
;
wire
clk_div
,
clk_ref
;
wire
dqs_data_dly
;
BUFR
#(
.
BUFR_DIVIDE
(
"2"
))
clk_div_i
(
.
I
(
clk_in
)
,.
O
(
clk_div
)
,.
CLR
(
rst
)
,
.
CE
(
1'b1
))
;
BUFR
#(
.
BUFR_DIVIDE
(
"BYPASS"
))
clk_i
(
.
I
(
clk_in
)
,.
O
(
clk
)
,
.
CLR
(
1'b0
)
,.
CE
(
1'b1
))
;
BUFG
ref_clk_i
(
.
I
(
clk_ref_in
)
,.
O
(
clk_ref
))
;
idelay_ctrl
#
(
.
IODELAY_GRP
(
"IODELAY_MEMORY"
)
)
idelay_ctrl_i
(
.
refclk
(
clk_ref
)
,
.
rst
(
rst
)
,
.
rdy
(
dly_ready
)
)
;
odelay_pipe
#
(
.
IODELAY_GRP
(
"IODELAY_MEMORY"
)
,
.
DELAY_VALUE
(
0
)
,
.
REFCLK_FREQUENCY
(
300.0
)
,
.
HIGH_PERFORMANCE_MODE
(
"FALSE"
)
)
dqs_data_dly_i
(
.
clk
(
clk_div
)
,
.
rst
(
rst
)
,
.
set
(
set
)
,
.
ld
(
ld
)
,
.
delay
(
dly_data
)
,
.
data_in
(
dqs_data
)
,
.
data_out
(
dqs_data_dly
)
)
;
IOBUFDS
#(
.
DQS_BIAS
(
"FALSE"
)
,
.
IBUF_LOW_PWR
(
"TRUE"
)
,
.
IOSTANDARD
(
"DEFAULT"
)
,
.
SLEW
(
"SLOW"
)
)
iobufs_dqs_i
(
.
O
(
dqs_received
)
,
.
IO
(
dqs
)
,
.
IOB
(
ndqs
)
,
.
I
(
dqs_data_dly
)
,
//dqs_data),
.
T
(
dqs_tri
))
;
endmodule
memctrl/phy/test_dqs03_placement.xdc
deleted
100644 → 0
View file @
466a4a4e
set_property PACKAGE_PIN N7 [get_ports {dqs}]
set_property SLEW FAST [get_ports {dqs}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {dqs}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dqs}]
set_property PACKAGE_PIN N6 [get_ports {ndqs}]
set_property SLEW FAST [get_ports {ndqs}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ndqs}]
# input dqs_data,
# inout dqs,
# inout ndqs,
# output dqs_received,
# input dqs_tri
#set_property IOSTANDARD LVCMOS15 [get_ports {rst}]
#set_property IOSTANDARD LVCMOS15 [get_ports {refclk}]
#set_property IOSTANDARD LVCMOS15 [get_ports {clk_in}]
#set_property IOSTANDARD LVCMOS15 [get_ports {set}]
#set_property IOSTANDARD LVCMOS15 [get_ports {ld_dly_data}]
#set_property IOSTANDARD LVCMOS15 [get_ports {ld_dly_tri}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[7]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[6]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[5]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[4]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[3]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[2]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[1]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[0]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {data_in[3]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {data_in[2]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {data_in[1]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {data_in[0]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[3]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[2]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[1]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dqs_received}]
set_property PACKAGE_PIN K4 [get_ports {dqs_received}]
set_property IOSTANDARD LVCMOS15 [get_ports {dqs_data}]
set_property PACKAGE_PIN K6 [get_ports {dqs_data}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_ready}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dqs_date}]
set_property IOSTANDARD LVCMOS15 [get_ports {dqs_tri}]
set_property PACKAGE_PIN K7 [get_ports {dqs_tri}]
# input dqs_data,
# inout dqs,
# inout ndqs,
# output dqs_received,
# input dqs_tri,
set_property IOSTANDARD LVCMOS15 [get_ports {clk_in}]
set_property PACKAGE_PIN M5 [get_ports {clk_in}]
set_property IOSTANDARD LVCMOS15 [get_ports {clk_ref_in}]
set_property PACKAGE_PIN L4 [get_ports {clk_ref_in}]
set_property IOSTANDARD LVCMOS15 [get_ports {rst}]
set_property PACKAGE_PIN L5 [get_ports {rst}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_ready}]
set_property PACKAGE_PIN M2 [get_ports {dly_ready}]
# input clk_in,
# input clk_ref_in,
# input rst,
# output dly_ready
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[4]}]
set_property PACKAGE_PIN J1 [get_ports {dly_data[4]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[3]}]
set_property PACKAGE_PIN J3 [get_ports {dly_data[3]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[2]}]
set_property PACKAGE_PIN J4 [get_ports {dly_data[2]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[1]}]
set_property PACKAGE_PIN J5 [get_ports {dly_data[1]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[0]}]
set_property PACKAGE_PIN J6 [get_ports {dly_data[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {set}]
set_property PACKAGE_PIN L6 [get_ports {set}]
set_property IOSTANDARD LVCMOS15 [get_ports {ld}]
set_property PACKAGE_PIN L7 [get_ports {ld}]
# input rst, // reset
# input refclk, // 200MHz/300MHz for delay calibration
# input clk_in,
# input set,
# input ld_dly_data,
# input ld_dly_tri,
# input [7:0] dly_data,
# input [3:0] data_in,
# input [3:0] tri_in,
# inout dqs,
# inout ndqs,
# output dqs_received,
# output dly_ready,
# input dqs_tri_a,
# output dqs_tri
#set_property PACKAGE_PIN A1 [get_ports {COUNT[2]}]
#set_property PACKAGE_PIN B2 [get_ports {COUNT[1]}]
#set_property PACKAGE_PIN C2 [get_ports {COUNT[0]}]
#set_property PULLUP true [get_ports {COUNT[3]}]
#set_property PULLUP true [get_ports {COUNT[2]}]
#set_property PULLUP true [get_ports {COUNT[1]}]
#set_property PULLUP true [get_ports {COUNT[0]}]
#set_property PACKAGE_PIN A4 [get_ports ENABLE]
#set_property PACKAGE_PIN B4 [get_ports RESET]
#set_property PACKAGE_PIN C1 [get_ports CLK]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CLK_IBUF]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[3]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[2]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[1]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[0]}]
#set_property IOSTANDARD LVCMOS18 [get_ports ENABLE]
#set_property IOSTANDARD LVCMOS18 [get_ports RESET]
#set_property IOSTANDARD LVCMOS18 [get_ports CLK]
set_property INTERNAL_VREF 0.750 [get_iobanks 34]
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
#ERROR: [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable
# for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING.
# However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override
# this clock rule.
# < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_ref_in_IBUF] >
# clk_ref_in_IBUF_inst (IBUF.O) is locked to IOB_X1Y123
# ref_clk_i (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31
# Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two.
# There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that
# result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is
# not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended
# clock has been placed on the N-Side of a differential pair CCIO-pin.
# set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_ref_in_IBUF]
memctrl/phy/test_dqs04.v
deleted
100644 → 0
View file @
466a4a4e
/*******************************************************************************
* Module: test_dqs04
* Date:2014-04-26
* Author: Andrey Filippov
* Description: Testing DQS implementation
*
* Copyright (c) 2014 Elphel, Inc.