Fixed generate that instantiated 4*4 histogram modules (including disables), tried with single histogram per channel - added 8% of all slices

Made several modifications to fix all timing violations to run compressor @250MHz - 1.0 Gigapixel/sec in JP4 mode

Imlemented single-clock bit stuffer to aggregate MSB aligned variable-length (1..27) data to 32-bit words

implemented optional skipping/fast forward of the data blocks when buffer is over/underrun during memory access

added simuilation modules for frequency multiplication/division, fractional period delays, started parallel12 -> HiSPi packetized SP converter

started modification of the i2c sequencer to support SMIA registers (2 bytes address, >=2 bytes of data) and register read