More debugging, fixed file length calculation and embedded timestamp (cbd5dc78) · Commits · Elphel / x393

.project

+8 −8

Original line number	Original line	Diff line number	Diff line
	@@ -62,42 +62,42 @@
	<link>		<link>
	<name>vivado_logs/VivadoBitstream.log</name>		<name>vivado_logs/VivadoBitstream.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150919172017385.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150923173658295.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOpt.log</name>		<name>vivado_logs/VivadoOpt.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150919172017385.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150923173658295.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOptPhys.log</name>		<name>vivado_logs/VivadoOptPhys.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150919172017385.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150923173658295.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOptPower.log</name>		<name>vivado_logs/VivadoOptPower.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150919172017385.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150923173658295.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoPlace.log</name>		<name>vivado_logs/VivadoPlace.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150919172017385.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150923173658295.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoRoute.log</name>		<name>vivado_logs/VivadoRoute.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150919172017385.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150923173658295.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoSynthesis.log</name>		<name>vivado_logs/VivadoSynthesis.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150919164827543.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150923170916067.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>		<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150919172017385.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150923173658295.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>		<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

compressor_jp/cmprs_frame_sync.v

+3 −1

Original line number	Original line	Diff line number	Diff line
	@@ -36,6 +36,8 @@ module cmprs_frame_sync#(
	input cmprs_en, // @mclk 0 resets immediately		input cmprs_en, // @mclk 0 resets immediately
	output cmprs_en_extend, // @mclk keep compressor enabled for graceful shutdown		output cmprs_en_extend, // @mclk keep compressor enabled for graceful shutdown

			// TODO: delay vsync_late if still compressing previous frame in multi-frame buffer mode

	input cmprs_run, // @mclk enable propagation of vsync_late to frame_start_dst in bonded(sync to src) mode		input cmprs_run, // @mclk enable propagation of vsync_late to frame_start_dst in bonded(sync to src) mode
	input cmprs_standalone, // @mclk single-cycle: generate a single frame_start_dst in unbonded (not synchronized) mode.		input cmprs_standalone, // @mclk single-cycle: generate a single frame_start_dst in unbonded (not synchronized) mode.
	// cmprs_run should be off		// cmprs_run should be off

compressor_jp/jp_channel.v

+35 −15

Original line number	Original line	Diff line number	Diff line
	@@ -311,7 +311,7 @@ module jp_channel#(
	wire [3:0] huff_dl; // output[3:0] reg		wire [3:0] huff_dl; // output[3:0] reg
	wire huff_dv; // output reg		wire huff_dv; // output reg
	wire flush; // output reg @ negedge xclk2x		wire flush; // output reg @ negedge xclk2x
			wire last_block; // @negedge xxlk2x - used to copy timestamp in stuffer


	wire [31:0] cmd_data; // 32-bit data to write to tables and registers(LSB first) - from cmd_deser		wire [31:0] cmd_data; // 32-bit data to write to tables and registers(LSB first) - from cmd_deser
	@@ -362,11 +362,15 @@ module jp_channel#(
	reg dbg_stuffer_ext_running;		reg dbg_stuffer_ext_running;
	reg dbg_reset_fifo;		reg dbg_reset_fifo;
	wire [3:0] etrax_dma;		wire [3:0] etrax_dma;
			wire dbg_ts_rstb; // output
			wire [7:0] dbg_ts_dout; //output [7:0]
			wire [31:0] dbg_sec;
			wire [31:0] dbg_usec;

	wire dbg_flushing;		wire dbg_flushing;
	reg dbg_flush_hclk;		reg dbg_flush_hclk;
	reg dbg_en_hclk;		reg dbg_en_hclk;

	wire dbg_last_block;
	reg dbg_en_n2x;		reg dbg_en_n2x;
	reg dbg_last_block_persist;		reg dbg_last_block_persist;
	wire dbg_test_lbw;		wire dbg_test_lbw;
	@@ -383,6 +387,14 @@ module jp_channel#(
	wire [2:0] dbg_block_mem_wa;		wire [2:0] dbg_block_mem_wa;
	wire [2:0] dbg_block_mem_wa_save;		wire [2:0] dbg_block_mem_wa_save;

			timestamp_to_parallel dbg_timestamp_to_parallel_i (
			.clk (~xclk2x), // input
			.pre_stb (dbg_ts_rstb), // input
			.tdata (dbg_ts_dout), // input[7:0]
			.sec (dbg_sec), // output[31:0] reg
			.usec (dbg_usec), // output[19:0] reg
			.done() // output
			);


	// cmprs_standalone - use to reset flush		// cmprs_standalone - use to reset flush
	@@ -394,7 +406,7 @@ module jp_channel#(
	dbg_en_n2x <= stuffer_en;		dbg_en_n2x <= stuffer_en;

	if (!dbg_en_n2x) dbg_last_block_persist <= 0;		if (!dbg_en_n2x) dbg_last_block_persist <= 0;
	else if (dbg_last_block) dbg_last_block_persist <= 1;		else if (last_block) dbg_last_block_persist <= 1;

	if (!dbg_en_n2x) dbg_gotLastBlock_persist <= 0;		if (!dbg_en_n2x) dbg_gotLastBlock_persist <= 0;
	else if (dbg_gotLastBlock) dbg_gotLastBlock_persist <= 1;		else if (dbg_gotLastBlock) dbg_gotLastBlock_persist <= 1;
	@@ -454,8 +466,8 @@ module jp_channel#(
	//frame_start_dst		//frame_start_dst

	debug_slave #(		debug_slave #(
	.SHIFT_WIDTH (320),		.SHIFT_WIDTH (384),
	.READ_WIDTH (320),		.READ_WIDTH (384),
	.WRITE_WIDTH (32),		.WRITE_WIDTH (32),
	.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)		.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
	) debug_slave_i (		) debug_slave_i (
	@@ -465,6 +477,8 @@ module jp_channel#(
	.debug_sl (debug_sl), // input		.debug_sl (debug_sl), // input
	.debug_do (debug_do), // output		.debug_do (debug_do), // output
	.rd_data ({		.rd_data ({
			dbg_usec,
			dbg_sec,
	26'h0, dbg_block_mem_wa_save[2:0],dbg_block_mem_wa[2:0],		26'h0, dbg_block_mem_wa_save[2:0],dbg_block_mem_wa[2:0],
	dbg_zds_cntr[15:0],		dbg_zds_cntr[15:0],
	dbg_stb_cntr[15:0],		dbg_stb_cntr[15:0],
	@@ -476,7 +490,7 @@ module jp_channel#(
	pages_requested[15:0],		pages_requested[15:0],
	dbg_comp_lastinmbo, dbg_block_mem_ra[2:0], debug_fifo_out[27:0],		dbg_comp_lastinmbo, dbg_block_mem_ra[2:0], debug_fifo_out[27:0],
	debug_fifo_in[31:0],		debug_fifo_in[31:0],
	color_last, dbg_last_block_persist, dbg_gotLastBlock, dbg_test_lbw, dbg_last_block,		color_last, dbg_last_block_persist, dbg_gotLastBlock, dbg_test_lbw, last_block,
	dbg_flush_hclk, dbg_flushing, stuffer_rdy, etrax_dma[3:0], dbg_stuffer_ext_running, stuffer_running_mclk, debug_frame_done, reading_frame,		dbg_flush_hclk, dbg_flushing, stuffer_rdy, etrax_dma[3:0], dbg_stuffer_ext_running, stuffer_running_mclk, debug_frame_done, reading_frame,
	fifo_count[7:0],		fifo_count[7:0],
	2'b0, dbg_fifo_or_full, dbg_gotLastBlock_persist, dbg_lastBlock_sent, dbg_last_DCAC, sigle_frame_buf, suspend,		2'b0, dbg_fifo_or_full, dbg_gotLastBlock_persist, dbg_lastBlock_sent, dbg_last_DCAC, sigle_frame_buf, suspend,
	@@ -1054,12 +1068,11 @@ module jp_channel#(
	.dl (huff_dl[3:0]), // output[3:0] reg		.dl (huff_dl[3:0]), // output[3:0] reg
	.dv (huff_dv), // output reg		.dv (huff_dv), // output reg
	.flush (flush), // output reg		.flush (flush), // output reg
			.last_block (last_block), // output reg
	`ifdef DEBUG_RING		`ifdef DEBUG_RING
	.last_block (dbg_last_block), // output reg unused does not get out
	.test_lbw (dbg_test_lbw), // output reg ??		.test_lbw (dbg_test_lbw), // output reg ??
	.gotLastBlock (dbg_gotLastBlock), // output ?? - unused (was for debug)		.gotLastBlock (dbg_gotLastBlock), // output ?? - unused (was for debug)
	`else		`else
	.last_block (), // output reg unused
	.test_lbw (), // output reg ??		.test_lbw (), // output reg ??
	.gotLastBlock (), // output ?? - unused (was for debug)		.gotLastBlock (), // output ?? - unused (was for debug)
	`endif		`endif
	@@ -1078,7 +1091,7 @@ module jp_channel#(
	.mclk (mclk), // input		.mclk (mclk), // input
	.mrst (mrst), // input		.mrst (mrst), // input
	.xrst (xrst), // input		.xrst (xrst), // input
			.last_block (last_block), // input @negedge xclk2x - use it to copy timestamp from fifo
	.ts_pre_stb (ts_pre_stb), // input 1 cycle before timestamp data, @mclk		.ts_pre_stb (ts_pre_stb), // input 1 cycle before timestamp data, @mclk
	.ts_data (ts_data), // input[7:0] 8-byte timestamp data (s0,s1,s2,s3,us0,us1,us2,us3==0)		.ts_data (ts_data), // input[7:0] 8-byte timestamp data (s0,s1,s2,s3,us0,us1,us2,us3==0)
	.color_first (color_first), // input valid @xclk - only for sec/usec		.color_first (color_first), // input valid @xclk - only for sec/usec
	@@ -1103,6 +1116,9 @@ module jp_channel#(
	.running (stuffer_running) // from registering timestamp until done		.running (stuffer_running) // from registering timestamp until done
	`ifdef DEBUG_RING		`ifdef DEBUG_RING
	, .dbg_etrax_dma (etrax_dma)		, .dbg_etrax_dma (etrax_dma)
			,.dbg_ts_rstb (dbg_ts_rstb) // output
			,.dbg_ts_dout (dbg_ts_dout) //output [7:0]

	`endif		`endif
	`ifdef debug_stuffer		`ifdef debug_stuffer
	,.etrax_dma_r(tst_stuf_etrax[3:0]) // [3:0] just for testing		,.etrax_dma_r(tst_stuf_etrax[3:0]) // [3:0] just for testing
	@@ -1110,7 +1126,11 @@ module jp_channel#(
	,.test_cntr1(test_cntr1[7:0])		,.test_cntr1(test_cntr1[7:0])
	`endif		`endif
	);		);
			/*
			,output dbg_ts_rstb
			,output [7:0] dbg_ts_dout

			*/
	pulse_cross_clock stuffer_done_mclk_i (.rst(xrst2xn), .src_clk(~xclk2x), .dst_clk(mclk), .in_pulse(stuffer_done), .out_pulse(stuffer_done_mclk),.busy());		pulse_cross_clock stuffer_done_mclk_i (.rst(xrst2xn), .src_clk(~xclk2x), .dst_clk(mclk), .in_pulse(stuffer_done), .out_pulse(stuffer_done_mclk),.busy());
	cmprs_out_fifo cmprs_out_fifo_i (		cmprs_out_fifo cmprs_out_fifo_i (
	// .rst (rst), // input mostly for simulation		// .rst (rst), // input mostly for simulation

compressor_jp/stuffer393.v

+19 −6

Original line number	Original line	Diff line number	Diff line
	@@ -46,6 +46,8 @@ module stuffer393 (
	input mclk,		input mclk,
	input mrst, // @posedge mclk, sync reset		input mrst, // @posedge mclk, sync reset
	input xrst, // @posedge xclk, sync reset		input xrst, // @posedge xclk, sync reset
			input last_block, // use it to copy timestamp from fifo


	// time stamping - will copy time at the end of color_first (later than the first hact after vact in the current frame, but before the next one		// time stamping - will copy time at the end of color_first (later than the first hact after vact in the current frame, but before the next one
	// and before the data is needed for output		// and before the data is needed for output
	@@ -73,14 +75,24 @@ module stuffer393 (
	output reg running // from registering timestamp until done		output reg running // from registering timestamp until done
	`ifdef DEBUG_RING		`ifdef DEBUG_RING
	, output reg [3:0] dbg_etrax_dma		, output reg [3:0] dbg_etrax_dma
			,output dbg_ts_rstb
			,output [7:0] dbg_ts_dout

	`endif		`endif

	`ifdef debug_stuffer		`ifdef debug_stuffer
	, output reg [3:0] etrax_dma_r // [3:0] just for testing		, output reg [3:0] etrax_dma_r // [3:0] just for testing
	, output reg [3:0] test_cntr,		, output reg [3:0] test_cntr,
	output reg [7:0] test_cntr1		output reg [7:0] test_cntr1

	`endif		`endif
	);		);

			`ifdef DEBUG_RING
			assign dbg_ts_rstb = ts_rstb;
			assign dbg_ts_dout = ts_dout;
			`endif

	//etrax_dma[3:0]		//etrax_dma[3:0]
	`ifdef debug_stuffer		`ifdef debug_stuffer
	reg en_d;		reg en_d;
	@@ -120,7 +132,7 @@ module stuffer393 (
	reg busy_eob; // flushing and sending length		reg busy_eob; // flushing and sending length
	reg trailer; // sending out data length and 32 bytes for ETRAX		reg trailer; // sending out data length and 32 bytes for ETRAX
	reg was_trailer; // sending out data length and 32 bytes for ETRAX		reg was_trailer; // sending out data length and 32 bytes for ETRAX
			reg last_block_d; // last_block delayed by one clock
	reg [ 3:0] etrax_dma; // count words to make total size multiple of 32 bytes.		reg [ 3:0] etrax_dma; // count words to make total size multiple of 32 bytes.
	// Last 4 bytes of data will have actual length in bytes		// Last 4 bytes of data will have actual length in bytes
	// There will always be at least 4 more bytes (0-es) before length - needed for software		// There will always be at least 4 more bytes (0-es) before length - needed for software
	@@ -157,9 +169,10 @@ module stuffer393 (
	wire stb_start; // re-clocked color_first		wire stb_start; // re-clocked color_first


	assign ts_rstb = trailer && !was_trailer; // enough time to have timestamp data		// assign ts_rstb = trailer && !was_trailer; // enough time to have timestamp data
			assign ts_rstb = last_block && !last_block_d; // enough time to have timestamp data
	always @ (negedge clk) begin		always @ (negedge clk) begin
	// ts_cycles <= {ts_cycles[6:0],ts_rstb};		last_block_d <= last_block;
	ts_cycles <= {ts_cycles[5:0],ts_rstb};		ts_cycles <= {ts_cycles[5:0],ts_rstb};
	if (ts_cycles[0]) sec_r[ 7: 0] <= ts_dout;		if (ts_cycles[0]) sec_r[ 7: 0] <= ts_dout;
	else if (start_sizeout) sec_r[ 7: 0] <= size_count[ 7:0];		else if (start_sizeout) sec_r[ 7: 0] <= size_count[ 7:0];

fpga_version.vh

+1 −1

Original line number	Original line	Diff line number	Diff line
	parameter FPGA_VERSION = 32'h03930035;		parameter FPGA_VERSION = 32'h03930038;
	No newline at end of file		No newline at end of file

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