Commits · faaa504f66c35bc9f77ca81678350aef36464665 · Elphel / x393

31 Mar, 2015 1 commit
- added DQS_IDELAY vs PHASE measurement/calculation · faaa504f
  Andrey Filippov authored Mar 31, 2015
  
  faaa504f
28 Mar, 2015 3 commits
- fixed last of the known so far errors in the DQ input delays vs DQS input delays LMA fitting · 3d603296
  Andrey Filippov authored Mar 28, 2015
  
  3d603296
- debugging weights and derivatives · 07f11d45
  Andrey Filippov authored Mar 28, 2015
  
  07f11d45
- debugging, adding more parameters to fit · b7eab69e
  Andrey Filippov authored Mar 28, 2015
  
  b7eab69e
26 Mar, 2015 1 commit
- Made LMA work with numpy libraries · 50aca841
  Andrey Filippov authored Mar 26, 2015
  
  50aca841
25 Mar, 2015 3 commits
- working on DQS+DQ inpute delays adjustment · 6989d804
  Andrey Filippov authored Mar 25, 2015
  
  6989d804
- started module for LMA fitting · 4f1a1c28
  Andrey Filippov authored Mar 25, 2015
  
  4f1a1c28
- temporary file to provide data normally measured by the hardware · 2f9f2a8b
  Andrey Filippov authored Mar 25, 2015
  
  2f9f2a8b
23 Mar, 2015 1 commit
- debugging write levelling measuring/results approximation · 4cf7bd61
  Andrey Filippov authored Mar 23, 2015
  
  4cf7bd61
22 Mar, 2015 1 commit
- debugging command/address timing adjustment · e4dae58e
  Andrey Filippov authored Mar 22, 2015
  
  e4dae58e
20 Mar, 2015 2 commits
- chaneged handling of the shared parameters, added defaults and saving modified... · 1902d5ce
  Andrey Filippov authored Mar 20, 2015
```
chaneged handling of the shared parameters, added defaults and saving modified parameters as Verilog include file
```
  1902d5ce
- module to keep global (Verilog) parameters, self-modified code to include... · e6b5bfc1
  Andrey Filippov authored Mar 20, 2015
```
module to keep global (Verilog) parameters, self-modified code to include pre-defines fro PyDev to be happy)
```
  e6b5bfc1
18 Mar, 2015 1 commit
- testing hardware, adding related code · 7a0b9347
  Andrey Filippov authored Mar 18, 2015
  
  7a0b9347
15 Mar, 2015 4 commits
- more porting dealy scan/adjust functionality from eddr3 · e6bc87ee
  Andrey Filippov authored Mar 15, 2015
  
  e6bc87ee
- added module with ported delays scan/adjustment functions · aabad99e
  Andrey Filippov authored Mar 15, 2015
  
  aabad99e
- porting delay scan/adjustment functions from the eddr3 Python code · 6ff31a13
  Andrey Filippov authored Mar 15, 2015
  
  6ff31a13
- Description of the memory controller clocks and programmable delays · 652c47ec
  Andrey Filippov authored Mar 15, 2015
  
  652c47ec
13 Mar, 2015 1 commit
- more hardware tests · 8df14818
  Andrey Filippov authored Mar 13, 2015
  
  8df14818
12 Mar, 2015 3 commits
- debugging hardware, added re filters for parameters and macros · 49288bf2
  Andrey Filippov authored Mar 12, 2015
  
  49288bf2
- debugging · 9326e242
  Andrey Filippov authored Mar 12, 2015
  
  9326e242
- working on hardware testing, added utility functions to load bitstream and use GPIO for debugging · 27a6599b
  Andrey Filippov authored Mar 12, 2015
  
  27a6599b
11 Mar, 2015 1 commit
- implemented help for task based on functions documentation · fad107cb
  Andrey Filippov authored Mar 11, 2015
  
  fad107cb
10 Mar, 2015 1 commit
- implemented @file in the test_mcntrl.py command line · e6868ded
  Andrey Filippov authored Mar 10, 2015
  
  e6868ded
08 Mar, 2015 1 commit
- more verilog tasks converted to python · f7c03985
  Andrey Filippov authored Mar 08, 2015
  
  f7c03985
07 Mar, 2015 1 commit
- next snapshot, implemented more expression types in parameter parsing · 8de61d31
  Andrey Filippov authored Mar 07, 2015
  
  8de61d31
05 Mar, 2015 2 commits
- more code converted from Verilog to Python · 21e45a99
  Andrey Filippov authored Mar 05, 2015
  
  21e45a99
- continue with python hardware test code · eba342eb
  Andrey Filippov authored Mar 05, 2015
  
  eba342eb
04 Mar, 2015 1 commit
- working on Python code for hardware testing · 63ff2819
  Andrey Filippov authored Mar 04, 2015
  
  63ff2819
03 Mar, 2015 1 commit
- creating Python program to pass Verilog parameters to Python FPGA tests · 4c3995d6
  Andrey Filippov authored Mar 03, 2015
  
  4c3995d6
01 Mar, 2015 1 commit
- working with Xilinx ISE/Vivado to synthesize and P&R the design · 0466926c
  Andrey Filippov authored Mar 01, 2015
  
  0466926c
28 Feb, 2015 1 commit
- working on synthesis with Vivado tools · 05378ee7
  Andrey Filippov authored Feb 28, 2015
  
  05378ee7
25 Feb, 2015 2 commits
- more fixes · df69d555
  Andrey Filippov authored Feb 25, 2015
  
  df69d555
- more bugs fixing with simulation · 7b13989a
  Andrey Filippov authored Feb 25, 2015
  
  7b13989a
23 Feb, 2015 1 commit
- before adding extra register layer between channel buffers outputs and memory controller · 943fc4a1
  Andrey Filippov authored Feb 23, 2015
  
  943fc4a1
22 Feb, 2015 3 commits
- more simulatin/bug fixing · d2db8c14
  Andrey Filippov authored Feb 22, 2015
  
  d2db8c14
- debugging after modifications · 7614ead5
  Andrey Filippov authored Feb 22, 2015
  
  7614ead5
- re-organized top structure · ad0351ef
  Andrey Filippov authored Feb 22, 2015
  
  ad0351ef
20 Feb, 2015 3 commits
- created and tested cmd_encod_tiled_32_wr.v - tiles with 32-byte columns · f35bb39d
  Andrey Filippov authored Feb 20, 2015
  
  f35bb39d
- added another channel for testing - tile write · a445ef42
  Andrey Filippov authored Feb 20, 2015
  
  a445ef42
- added tile write (column order) · 31a6b971
  Andrey Filippov authored Feb 20, 2015
  
  31a6b971