x393:faaa504f66c35bc9f77ca81678350aef36464665 commitshttps://git.elphel.com/Elphel/x393/commits/faaa504f66c35bc9f77ca81678350aef364646652015-03-31T07:33:44Zhttps://git.elphel.com/Elphel/x393/commit/faaa504f66c35bc9f77ca81678350aef36464665added DQS_IDELAY vs PHASE measurement/calculation2015-03-31T07:33:44ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/3d603296b9a9250c367ef9a4ead8a1a3e6691b82fixed last of the known so far errors in the DQ input delays vs DQS input del...2015-03-28T23:28:22ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/07f11d45b300a3531a40f234e0e589d4e12c1fb9debugging weights and derivatives2015-03-28T19:28:34ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/b7eab69e23b48f04595b9c31ecc1f5b0bb4ac6e6debugging, adding more parameters to fit2015-03-28T07:03:19ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/50aca84180c6f6d2a5b0519d0e72d71de21eaae5Made LMA work with numpy libraries2015-03-26T04:55:21ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/6989d804ea1ab8f22e1333a5b825dec7b9bc27eeworking on DQS+DQ inpute delays adjustment2015-03-25T05:41:44ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/4f1a1c28bf75e37e3e2bcafd482121d6bfa50532started module for LMA fitting2015-03-25T05:40:55ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/2f9f2a8b512d3a53ada8b8322d2d8504da5836datemporary file to provide data normally measured by the hardware2015-03-25T05:39:22ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/4cf7bd6179dc3a8787334d89c7bf2a2d62679ed0debugging write levelling measuring/results approximation2015-03-23T00:54:40ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/e4dae58ee0b815129e8c22570a9cb29e1b031fd0debugging command/address timing adjustment2015-03-22T19:35:07ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/1902d5ce1e404a90441674ee106e80501d6adc10chaneged handling of the shared parameters, added defaults and saving modifie...2015-03-20T06:07:00ZAndrey Filippovandrey@elphel.comchaneged handling of the shared parameters, added defaults and saving modified parameters as Verilog include file
https://git.elphel.com/Elphel/x393/commit/e6b5bfc1b2fef28837a4e9d633c735689dc14792module to keep global (Verilog) parameters, self-modified code to include...2015-03-20T06:05:43ZAndrey Filippovandrey@elphel.commodule to keep global (Verilog) parameters, self-modified code to include pre-defines fro PyDev to be happy)
https://git.elphel.com/Elphel/x393/commit/7a0b9347ebe85eba48e76421255943ee5a8e77d9testing hardware, adding related code2015-03-18T04:59:01ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/e6bc87ee5fe8b0cb054b86c689fe566519b3896emore porting dealy scan/adjust functionality from eddr32015-03-15T07:08:23ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/aabad99e4758c8df6bb02623f8ff4814367022a8added module with ported delays scan/adjustment functions2015-03-15T04:32:15ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/6ff31a1390f5d752909850179acf3867bb9e607cporting delay scan/adjustment functions from the eddr3 Python code2015-03-15T04:30:50ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/652c47ec2d107be126df973b161b5dfcbde4f4b2Description of the memory controller clocks and programmable delays2015-03-15T04:29:38ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/8df14818b49fc8533911b2b94febb8b628f36827more hardware tests2015-03-13T02:22:01ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/49288bf210bb27ea05089aac419b880e49474247debugging hardware, added re filters for parameters and macros2015-03-12T20:48:41ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/9326e2420317ccb529214c4cbbf83900b246cf21debugging2015-03-12T06:44:56ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/27a6599b69dcb394996795c94a997b019868cf08working on hardware testing, added utility functions to load bitstream and us...2015-03-12T03:24:03ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/fad107cb2ca57d575d0bdcf7091def89e6752192implemented help for task based on functions documentation2015-03-11T05:48:46ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/e6868ded7eea0b7f8281cac4c74da753a2df5594implemented @file in the test_mcntrl.py command line2015-03-10T05:33:32ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/f7c039856cce093f4cb94895355c64434d815788more verilog tasks converted to python2015-03-08T05:37:27ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/8de61d312ef16a4c818258fc941bb6fb8d5a7bdbnext snapshot, implemented more expression types in parameter parsing2015-03-07T18:46:36ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/21e45a9976b1094e94d7c808c8ead12d63a7dce2more code converted from Verilog to Python2015-03-05T06:17:28ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/eba342eb85c65470dd63b71c9e2899b912285403continue with python hardware test code2015-03-05T02:17:26ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/63ff28196f1947fbe67394d2772bfb0a3a241fefworking on Python code for hardware testing2015-03-04T08:09:15ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/4c3995d60e80de575bd9e252ff345eb2adca56cbcreating Python program to pass Verilog parameters to Python FPGA tests2015-03-03T03:25:45ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/0466926cc72c1177ca3da46a75dcebddcc62b0f3working with Xilinx ISE/Vivado to synthesize and P&R the design2015-03-01T05:00:39ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/05378ee794495b9e30e0b6080f489a9965804b0eworking on synthesis with Vivado tools2015-02-28T07:25:56ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/df69d5558e5626cc06d45eac44459e10bf472d81more fixes2015-02-25T03:23:54ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/7b13989a8a8018e9a2769009a13fc6194fd7a03dmore bugs fixing with simulation2015-02-25T01:48:12ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/943fc4a1d621ee4d34700788e5793d04baf08c1bbefore adding extra register layer between channel buffers outputs and memory...2015-02-23T20:45:44ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/d2db8c14bec3351c03a3baa4d17b900ca6e2cb03more simulatin/bug fixing2015-02-22T22:36:15ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/7614ead578505a40e9ef9beccfdf2a0e261d50afdebugging after modifications2015-02-22T08:01:48ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/ad0351ef12f2a368a8571ff148b3feb689075980re-organized top structure2015-02-22T04:46:27ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/f35bb39d9ba6f256b1ad0d1352db07fb4a86d5f4created and tested cmd_encod_tiled_32_wr.v - tiles with 32-byte columns2015-02-20T08:02:51ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/a445ef42b7671646d5bf50bf1bdd0a8929048a95added another channel for testing - tile write2015-02-20T01:33:38ZAndrey Filippovandrey@elphel.comhttps://git.elphel.com/Elphel/x393/commit/31a6b9715722780461c54f89e30bb6af82d36173added tile write (column order)2015-02-20T01:32:46ZAndrey Filippovandrey@elphel.com