Commits · 2317d4fd0524929d638a091f1ed332ade27ec478 · Elphel / x393

11 Apr, 2021 1 commit
- 103993A, no DE deglitch, FPGA_VERSION = 32'h03934014 · b732c0f0
  Andrey Filippov authored 4 years ago
  
  b732c0f0
03 Apr, 2021 1 commit
- Switching 103993-> 10399A hardware · 1153e80a
  Andrey Filippov authored 4 years ago
  
  1153e80a
01 Apr, 2021 1 commit
- FPGA_VERSION = 32'h03934006, before revA · 6b653653
  Andrey Filippov authored 4 years ago
  
  6b653653
31 Mar, 2021 2 commits
- added nedw fields to c-export · bd64002a
  Andrey Filippov authored 4 years ago
  
  bd64002a
- 103993-rev0 with DRP MMCM/PLL control · ad1c2b04
  Andrey Filippov authored 4 years ago
  
  ad1c2b04
22 Mar, 2021 1 commit
- adding trigger decimation · d8258888
  Andrey Filippov authored 4 years ago
  
  d8258888
04 Mar, 2021 1 commit
- multiple updates, fpga version 0393021f · a7d6e9ea
  Andrey Filippov authored 4 years ago
  
  a7d6e9ea
13 Feb, 2021 1 commit
- fixing recover from broken frames by optional disabling of pending frame starts, other debug · 2cb5c0b4
  Andrey Filippov authored 4 years ago
  
  2cb5c0b4
08 Feb, 2021 1 commit
- got images from Boson640 · a6df0611
  Andrey Filippov authored 4 years ago
  
  a6df0611
20 Jan, 2021 1 commit
- added boson bit, generated for as if 2.5V · c4b3e834
  Andrey Filippov authored 4 years ago
  
  c4b3e834
12 Jan, 2021 1 commit
- simulating image generation and debugging implementation · da24e724
  Andrey Filippov authored 4 years ago
  
  da24e724
01 Jan, 2021 1 commit
- debugging uart transmit · a31012ed
  Andrey Filippov authored 4 years ago
  
  a31012ed
26 Dec, 2020 1 commit
- working on boson implementaion, fixed old bug in python code · 043d4849
  Andrey Filippov authored 4 years ago
  
  043d4849
04 May, 2019 1 commit
- adding rigger out from the sensors running i free mode · 8f05c2c2
  Andrey Filippov authored 5 years ago
  
  8f05c2c2
03 May, 2019 1 commit
- implemented sync reset, fpga version 0x03930136 · ae33ff53
  Andrey Filippov authored 5 years ago
  
  ae33ff53
30 Apr, 2019 1 commit
- Debugging vospi mode, fpga: 0x03930133 · 9b620b6b
  Andrey Filippov authored 5 years ago
  
  9b620b6b
26 Apr, 2019 2 commits
- implemented telemetry on/off, updated mode bits. FPGA version 0393012e · 36912bd3
  Andrey Filippov authored 5 years ago
  
  36912bd3
- vospi debug, implemented packet synchronization by signature · 9d60666b
  Andrey Filippov authored 5 years ago
  
  9d60666b
19 Apr, 2019 1 commit
- passed big endian in 16-bit mode from Python simulation/implementation script · a5c0516e
  Andrey Filippov authored 5 years ago
  
  a5c0516e
18 Apr, 2019 1 commit
- simulating/debugging LWIR sensor FPGA code · f35c087d
  Andrey Filippov authored 5 years ago
  
  f35c087d
14 Apr, 2019 1 commit
- More development of the Verilog and Python code for LWIR sensors · 654584f3
  Andrey Filippov authored 6 years ago
  
  654584f3
12 Apr, 2019 1 commit
- more code for LWIR sensor · 37190574
  Andrey Filippov authored 6 years ago
  
  37190574
11 Apr, 2019 1 commit
- commands and status for LWIR/VOSPI, exported to C · 691579c0
  Andrey Filippov authored 6 years ago
  
  691579c0
10 Apr, 2019 1 commit
- modifying TCL scripts for Xilinx tools to support LWIR sensors · 3e5d8c1c
  Andrey Filippov authored 6 years ago
  
  3e5d8c1c
04 Apr, 2019 1 commit
- Updated simulation code · d189269a
  Andrey Filippov authored 6 years ago
  
  d189269a
30 Mar, 2019 1 commit
- v. 0105, fixed raw for large window - channel interefence remains · 10d144ea
  Andrey Filippov authored 6 years ago
  
  10d144ea
24 Mar, 2019 1 commit
- Introducing new parameters and other changes to implement raw data out. · d30c9b6a
  Andrey Filippov authored 6 years ago
  
  d30c9b6a
21 Mar, 2019 1 commit
- Working on compression bypassing in raw data mode · a22c0250
  Andrey Filippov authored 6 years ago
  
  a22c0250
16 Mar, 2018 1 commit
- Added measurement of HISPI cycles between SOF, EOF, SOL, EOL. Version · 722e3aca
  Andrey Filippov authored 7 years ago
```
03930101
```
  722e3aca
01 Mar, 2018 1 commit
- fixed phase adjustment · fbb7ef43
  Oleg Dzhimiev authored 7 years ago
  
  fbb7ef43
12 Feb, 2018 1 commit
- HISPI: added per-lane line-sync monitoring, TRIG as programmable option · 429b228d
  Andrey Filippov authored 7 years ago
```
for GP0 and GP1
```
  429b228d
13 Apr, 2017 1 commit
- modified source to include new SATA code (not in the bitstream) · 8cdabd55
  Andrey Filippov authored 8 years ago
  
  8cdabd55
11 Dec, 2016 1 commit
- synchronized with x393_sata, added irq on/off logging · ecaf0e84
  Andrey Filippov authored 8 years ago
  
  ecaf0e84
10 Dec, 2016 1 commit
- updated sata subsystem to v12 · 897e8b86
  Andrey Filippov authored 8 years ago
  
  897e8b86
08 Dec, 2016 1 commit
- updated from x393_sata, fixed behavior after desk errors. Matching x393_sata bitsteram version 0x0b · 18f4a937
  Andrey Filippov authored 8 years ago
  
  18f4a937
14 Nov, 2016 1 commit
- added more simulation images, more fixing of JPEG tail · 87900556
  Andrey Filippov authored 8 years ago
  
  87900556
11 Nov, 2016 1 commit
- more work on JPEG tail, version 0x039300ca · a17b36ec
  Andrey Filippov authored 8 years ago
  
  a17b36ec
10 Nov, 2016 1 commit
- more fixing jpeg tail · 4b42ed42
  Andrey Filippov authored 8 years ago
  
  4b42ed42
29 Oct, 2016 1 commit
- Added EOF/SOF swoitch for i2c sequencer, bitstream version c4 · eb0f6b26
  Andrey Filippov authored 8 years ago
  
  eb0f6b26
27 Oct, 2016 1 commit
- Implemented Eyesis external trigger, lost trigger recover · d65592bb
  Andrey Filippov authored 8 years ago
  
  d65592bb