Commit 6b653653 authored by Andrey Filippov's avatar Andrey Filippov

FPGA_VERSION = 32'h03934006, before revA

parent 3377d53b
......@@ -35,10 +35,11 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h03934005; // Boson640, testing
// parameter FPGA_VERSION = 32'h03934005; // Boson640, implementing DRP to control MMCME2/PLLE2 trying more BUFR
// parameter FPGA_VERSION = 32'h03934004; // Boson640, implementing DRP to control MMCME2/PLLE2
// parameter FPGA_VERSION = 32'h03934003; // Boson640, mitigating LVDS errors
parameter FPGA_VERSION = 32'h03934006; // Boson640, adjusted initial phase to 70.5 degrees (47 counts)
// parameter FPGA_VERSION = 32'h03934005; // Boson640, testing
// parameter FPGA_VERSION = 32'h03934005; // Boson640, implementing DRP to control MMCME2/PLLE2 trying more BUFR
// parameter FPGA_VERSION = 32'h03934004; // Boson640, implementing DRP to control MMCME2/PLLE2
// parameter FPGA_VERSION = 32'h03934003; // Boson640, mitigating LVDS errors
// parameter FPGA_VERSION = 32'h03934002; // Boson640, mitigating LVDS errors
// parameter FPGA_VERSION = 32'h03934001; // Boson640, adding camsync trigger decimation // git commit
///parameter FPGA_VERSION = 32'h03931003; // parallel, adding camsync trigger decimation - debugging // git commit
......
......@@ -732,7 +732,7 @@
`ifdef SIMULATION
parameter CLKFBOUT_PHASE_SENSOR = 54.0, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
`else
parameter CLKFBOUT_PHASE_SENSOR = -22.5, // -21.0, // 19.5, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter CLKFBOUT_PHASE_SENSOR = 70.5, // -22.5, // -21.0, // 19.5, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
`endif
parameter PCLK_PHASE = 0.000, // not used
parameter IPCLK1X_PHASE = 0.000, // -3.000, // trying both ways (PCLK_PHASE inside sens_103993)
......
......@@ -1827,7 +1827,7 @@ uart_print_packet 0 False False
num_sensor,
wait_lock = True):
"""
Close DRP connection, remove MMCM/PLL reset
Close DRP connection by de-asserting MMCM/PLL reset
@param num_sensor - sensor port number (0..3)
@param wait_lock - wait MMCM/PLL to lock
"""
......@@ -1835,7 +1835,7 @@ uart_print_packet 0 False False
locked_pxd_mmcm = False
while not locked_pxd_mmcm:
sensor_status = self.x393Sensor.get_new_status(num_sensor=num_sensor)
sensor_status = self.get_new_status(num_sensor=num_sensor)
locked_pxd_mmcm = ((sensor_status >> 12) & 1) != 0
......
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Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
| Date : Tue Mar 30 18:19:38 2021
| Date : Wed Mar 31 22:30:11 2021
| Host : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS
| Command : report_utilization -file vivado_build/x393_boson_utilization.report
| Design : x393
......
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