Commit 8f05c2c2 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

adding rigger out from the sensors running i free mode

parent ae33ff53

cocotb/x393_cocotb_lwir_04.sav

+33 −5
Original line number Diff line number Diff line 
[*]

[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI

[*] Fri May  3 04:06:38 2019

[*] Fri May  3 15:28:46 2019

[*]

[dumpfile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/simulation/x393_dut-20190502213839545.fst"

[dumpfile_mtime] "Fri May  3 04:06:09 2019"
@@ -3061,16 +3061,44 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepto 
@28

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.start_spi_seq_mclk

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.start_spi_seq_pclk

@29

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.spi_timeout_cntr[1:0]

@28

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.spi_seq

@200

-

@1000200

-reset_seq

@800200

-sens_channel0

-timestamping

@22

x393_dut.x393_i.timing393_i.frame_sync[3:0]

@28

x393_dut.x393_i.timing393_i.frsync_chn0

x393_dut.x393_i.timing393_i.frsync_chn1

x393_dut.x393_i.timing393_i.frsync_chn2

x393_dut.x393_i.timing393_i.frsync_chn3

@22

x393_dut.x393_i.timing393_i.trig[3:0]

@28

x393_dut.x393_i.timing393_i.trig_chn0

x393_dut.x393_i.timing393_i.trig_chn1

x393_dut.x393_i.timing393_i.trig_chn2

x393_dut.x393_i.timing393_i.trig_chn3

x393_dut.x393_i.timing393_i.triggered_mode

@22

x393_dut.x393_i.timing393_i.ts_data_chn0[7:0]

x393_dut.x393_i.timing393_i.ts_data_chn1[7:0]

x393_dut.x393_i.timing393_i.ts_data_chn2[7:0]

x393_dut.x393_i.timing393_i.ts_data_chn3[7:0]

x393_dut.x393_i.timing393_i.ts_stb[3:0]

@28

x393_dut.x393_i.timing393_i.ts_stb_chn0

x393_dut.x393_i.timing393_i.ts_stb_chn1

x393_dut.x393_i.timing393_i.ts_stb_chn2

x393_dut.x393_i.timing393_i.ts_stb_chn3

@201

-

@1000200

-timestamping

@800200

-lepto3_0

@28

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.prst

fpga_version.vh

+2 −1
Original line number Diff line number Diff line
@@ -35,7 +35,8 @@ 
 * contains all the components and scripts required to completely simulate it

 * with at least one of the Free Software programs.

 */

        parameter FPGA_VERSION =          32'h03930136;      // Fiixing spi_seq 

        parameter FPGA_VERSION =          32'h03930137;       // longer reset, sync output 

//        parameter FPGA_VERSION =          32'h03930136;      // Fiixing spi_seq 

//        parameter FPGA_VERSION =          32'h03930135;      // Adding multi-cam reset 

//        parameter FPGA_VERSION =          32'h0393014;      // Adding multi-cam reset - buggy 

//        parameter FPGA_VERSION =          32'h03930133;      // Works with linux kernel rocko commit of 05/01/2019 bd61276e05f7343415929112ae368230a9c472f0

includes/x393_parameters.vh

+1 −1
Original line number Diff line number Diff line
@@ -594,7 +594,7 @@ 
        parameter VOSPI_MRST_AFTER_MS =      5, // Wait after master reset and generate SOF pulse to advance sequencer  

        parameter VOSPI_SPI_TIMEOUT_MS =     3, // Wait to tymeout SPI when needed to re-sync

    `else

        parameter VOSPI_MRST_MS =            5, // master reset duration in ms

        parameter VOSPI_MRST_MS =          200, // master reset duration in ms (so even all channels would overlap)

        parameter VOSPI_MRST_AFTER_MS =   2000, // Wait after master reset and generate SOF pulse to advance sequencer  

        parameter VOSPI_SPI_TIMEOUT_MS =   185, // Wait to tymeout SPI when needed to re-sync

    `endif

sensor/sens_lepton3.v

+1 −1
Original line number Diff line number Diff line
@@ -89,7 +89,7 @@ module sens_lepton3 #( 
    parameter VOSPI_SOF_TO_HACT =    100, //  10,  // clock cycles from SOF to HACT (limited to 8 bits)

    parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF

    parameter VOSPI_MCLK_HALFDIV =     4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock

    parameter VOSPI_MRST_MS =          5, // master reset duration in ms

    parameter VOSPI_MRST_MS =        200, // master reset duration in ms (so even all channels would overlap)

    parameter VOSPI_MRST_AFTER_MS = 2000,  // Wait after master reset and generate SOF pulse to advance sequencer  

    parameter VOSPI_SPI_TIMEOUT_MS = 185 // Wait to tymeout SPI when needed to re-sync

)(

sensor/sensor_channel.v

+2 −2
Original line number Diff line number Diff line
@@ -276,7 +276,7 @@ module sensor_channel#( 
    parameter VOSPI_SOF_TO_HACT =      100, //  10,  // clock cycles from SOF to HACT (limited to 8 bits)

    parameter VOSPI_HACT_TO_HACT_EOF =   2,  // minimal clock cycles from HACT to HACT or to EOF

    parameter VOSPI_MCLK_HALFDIV =       4,  // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock 

    parameter VOSPI_MRST_MS =            5, // master reset duration in ms

    parameter VOSPI_MRST_MS =          200, // master reset duration in ms (so even all channels would overlap)

    parameter VOSPI_MRST_AFTER_MS =   2000,  // Wait after master reset and generate SOF pulse to advance sequencer  

    parameter VOSPI_SPI_TIMEOUT_MS =   185 // Wait to tymeout SPI when needed to re-sync

`else
@@ -1061,7 +1061,7 @@ module sensor_channel#( 
            .VOSPI_SOF_TO_HACT      (VOSPI_SOF_TO_HACT), //      100,

            .VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF), //   2,

            .VOSPI_MCLK_HALFDIV     (VOSPI_MCLK_HALFDIV), //       4

            .VOSPI_MRST_MS          (VOSPI_MRST_MS), //            5

            .VOSPI_MRST_MS          (VOSPI_MRST_MS), //          200, // master reset duration in ms (so even all channels would overlap)

            .VOSPI_MRST_AFTER_MS    (VOSPI_MRST_AFTER_MS), //   2000

            .VOSPI_SPI_TIMEOUT_MS   (VOSPI_SPI_TIMEOUT_MS) //    185

    ) sens_lepton3_i (