Loading includes/ahci_defaults.vh +1 −1 Original line number Original line Diff line number Diff line Loading @@ -2,6 +2,6 @@ , .INIT_08 (256'h000000000024000600000000000000000000000080000C000000000080000800) , .INIT_08 (256'h000000000024000600000000000000000000000080000C000000000080000800) , .INIT_09 (256'h000000000000000000000000000000000000000000000000FFFFFFFF00000000) , .INIT_09 (256'h000000000000000000000000000000000000000000000000FFFFFFFF00000000) , .INIT_0B (256'h0000000000000000000000000000003300000000000000000000000000000000) , .INIT_0B (256'h0000000000000000000000000000003300000000000000000000000000000000) , .INIT_0C (256'h000000000000000000000000000000000000000001010002001000000001FFFE) , .INIT_0C (256'h00000000000000000000000000000000000000000101000B001000000001FFFE) , .INIT_0D (256'h000001000000000000000040000000000001FFFE000000008000000000000000) , .INIT_0D (256'h000001000000000000000040000000000001FFFE000000008000000000000000) , .INIT_0E (256'h0000000000000000000000000000000000000000000000000000000040000001) , .INIT_0E (256'h0000000000000000000000000000000000000000000000000000000040000001) includes/ahci_localparams.vh +1 −1 Original line number Original line Diff line number Diff line Loading @@ -97,7 +97,7 @@ // RO: HBA Revision ID // RO: HBA Revision ID localparam PCI_Header__RID__RID__ADDR = 'h62; localparam PCI_Header__RID__RID__ADDR = 'h62; localparam PCI_Header__RID__RID__MASK = 'hff; localparam PCI_Header__RID__RID__MASK = 'hff; localparam PCI_Header__RID__RID__DFLT = 'h2; localparam PCI_Header__RID__RID__DFLT = 'hb; // RO: Base Class Code: 1 - Mass Storage Device // RO: Base Class Code: 1 - Mass Storage Device localparam PCI_Header__CC__BCC__ADDR = 'h62; localparam PCI_Header__CC__BCC__ADDR = 'h62; localparam PCI_Header__CC__BCC__MASK = 'hff000000; localparam PCI_Header__CC__BCC__MASK = 'hff000000; Loading x393_sata/ahci/ahci_ctrl_stat.v +1 −1 Original line number Original line Diff line number Diff line Loading @@ -498,7 +498,7 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK | // 'hf0000000; else if (swr_HBA_PORT__PxCI) pxci0_r <= soft_write_data[0]; else if (swr_HBA_PORT__PxCI) pxci0_r <= soft_write_data[0]; end end // HBA_PORT__PxCMD register - different behaviors of differtnt fields // HBA_PORT__PxCMD register - different behaviors of different fields // use PxCMD_MASK to prevent generation of unneeded register bits // use PxCMD_MASK to prevent generation of unneeded register bits always @(posedge mclk) begin always @(posedge mclk) begin Loading x393_sata/ahci/ahci_fsm.v +3 −1 Original line number Original line Diff line number Diff line Loading @@ -394,7 +394,9 @@ module ahci_fsm if (fsm_actions && fsm_next) was_last_action_r <= fsm_last_act_w; if (fsm_actions && fsm_next) was_last_action_r <= fsm_last_act_w; if (hba_rst || pre_jump_w) fsm_transitions <= 0; //// if (hba_rst || pre_jump_w) fsm_transitions <= 0; /// 2016.12.07 jumps were not disabled after async transitions, they came from the previously executed code if (hba_rst || pre_jump_w || dis_actions) fsm_transitions <= 0; else if (fsm_transitions_w) fsm_transitions <= 1; else if (fsm_transitions_w) fsm_transitions <= 1; // else if ((fsm_last_act_w && fsm_actions && fsm_next && !fsm_wait_act_w) || // else if ((fsm_last_act_w && fsm_actions && fsm_next && !fsm_wait_act_w) || // (fsm_act_busy && fsm_act_done && was_last_action_r) ) fsm_transitions <= 1; // (fsm_act_busy && fsm_act_done && was_last_action_r) ) fsm_transitions <= 1; Loading x393_sata/ahci/axi_ahci_regs.v +2 −1 Original line number Original line Diff line number Diff line Loading @@ -332,7 +332,8 @@ module axi_ahci_regs#( end end always @ (hba_clk) begin //// always @ (hba_clk) begin always @ (posedge aclk) begin was_hba_rst_r <= {was_hba_rst_aclk, was_hba_rst_r[2:1]}; was_hba_rst_r <= {was_hba_rst_aclk, was_hba_rst_r[2:1]}; was_port_rst_r <= {was_port_rst_aclk, was_port_rst_r[2:1]}; was_port_rst_r <= {was_port_rst_aclk, was_port_rst_r[2:1]}; end end Loading Loading
includes/ahci_defaults.vh +1 −1 Original line number Original line Diff line number Diff line Loading @@ -2,6 +2,6 @@ , .INIT_08 (256'h000000000024000600000000000000000000000080000C000000000080000800) , .INIT_08 (256'h000000000024000600000000000000000000000080000C000000000080000800) , .INIT_09 (256'h000000000000000000000000000000000000000000000000FFFFFFFF00000000) , .INIT_09 (256'h000000000000000000000000000000000000000000000000FFFFFFFF00000000) , .INIT_0B (256'h0000000000000000000000000000003300000000000000000000000000000000) , .INIT_0B (256'h0000000000000000000000000000003300000000000000000000000000000000) , .INIT_0C (256'h000000000000000000000000000000000000000001010002001000000001FFFE) , .INIT_0C (256'h00000000000000000000000000000000000000000101000B001000000001FFFE) , .INIT_0D (256'h000001000000000000000040000000000001FFFE000000008000000000000000) , .INIT_0D (256'h000001000000000000000040000000000001FFFE000000008000000000000000) , .INIT_0E (256'h0000000000000000000000000000000000000000000000000000000040000001) , .INIT_0E (256'h0000000000000000000000000000000000000000000000000000000040000001)
includes/ahci_localparams.vh +1 −1 Original line number Original line Diff line number Diff line Loading @@ -97,7 +97,7 @@ // RO: HBA Revision ID // RO: HBA Revision ID localparam PCI_Header__RID__RID__ADDR = 'h62; localparam PCI_Header__RID__RID__ADDR = 'h62; localparam PCI_Header__RID__RID__MASK = 'hff; localparam PCI_Header__RID__RID__MASK = 'hff; localparam PCI_Header__RID__RID__DFLT = 'h2; localparam PCI_Header__RID__RID__DFLT = 'hb; // RO: Base Class Code: 1 - Mass Storage Device // RO: Base Class Code: 1 - Mass Storage Device localparam PCI_Header__CC__BCC__ADDR = 'h62; localparam PCI_Header__CC__BCC__ADDR = 'h62; localparam PCI_Header__CC__BCC__MASK = 'hff000000; localparam PCI_Header__CC__BCC__MASK = 'hff000000; Loading
x393_sata/ahci/ahci_ctrl_stat.v +1 −1 Original line number Original line Diff line number Diff line Loading @@ -498,7 +498,7 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK | // 'hf0000000; else if (swr_HBA_PORT__PxCI) pxci0_r <= soft_write_data[0]; else if (swr_HBA_PORT__PxCI) pxci0_r <= soft_write_data[0]; end end // HBA_PORT__PxCMD register - different behaviors of differtnt fields // HBA_PORT__PxCMD register - different behaviors of different fields // use PxCMD_MASK to prevent generation of unneeded register bits // use PxCMD_MASK to prevent generation of unneeded register bits always @(posedge mclk) begin always @(posedge mclk) begin Loading
x393_sata/ahci/ahci_fsm.v +3 −1 Original line number Original line Diff line number Diff line Loading @@ -394,7 +394,9 @@ module ahci_fsm if (fsm_actions && fsm_next) was_last_action_r <= fsm_last_act_w; if (fsm_actions && fsm_next) was_last_action_r <= fsm_last_act_w; if (hba_rst || pre_jump_w) fsm_transitions <= 0; //// if (hba_rst || pre_jump_w) fsm_transitions <= 0; /// 2016.12.07 jumps were not disabled after async transitions, they came from the previously executed code if (hba_rst || pre_jump_w || dis_actions) fsm_transitions <= 0; else if (fsm_transitions_w) fsm_transitions <= 1; else if (fsm_transitions_w) fsm_transitions <= 1; // else if ((fsm_last_act_w && fsm_actions && fsm_next && !fsm_wait_act_w) || // else if ((fsm_last_act_w && fsm_actions && fsm_next && !fsm_wait_act_w) || // (fsm_act_busy && fsm_act_done && was_last_action_r) ) fsm_transitions <= 1; // (fsm_act_busy && fsm_act_done && was_last_action_r) ) fsm_transitions <= 1; Loading
x393_sata/ahci/axi_ahci_regs.v +2 −1 Original line number Original line Diff line number Diff line Loading @@ -332,7 +332,8 @@ module axi_ahci_regs#( end end always @ (hba_clk) begin //// always @ (hba_clk) begin always @ (posedge aclk) begin was_hba_rst_r <= {was_hba_rst_aclk, was_hba_rst_r[2:1]}; was_hba_rst_r <= {was_hba_rst_aclk, was_hba_rst_r[2:1]}; was_port_rst_r <= {was_port_rst_aclk, was_port_rst_r[2:1]}; was_port_rst_r <= {was_port_rst_aclk, was_port_rst_r[2:1]}; end end Loading