fixing recover from broken frames by optional disabling of pending frame starts, other debug (2cb5c0b4) · Commits · Elphel / x393

fpga_version.vh

+8 −3

Original line number	Diff line number	Diff line
		@@ -35,9 +35,14 @@
		* contains all the components and scripts required to completely simulate it
		* with at least one of the Free Software programs.
		*/
		parameter FPGA_VERSION = 32'h0393020f; // added test mode
		// parameter FPGA_VERSION = 32'h0393020f; // changing MMCM phase -20.0 (use clk_fb) IBUF_LOW_PWR=FALSE
		// parameter FPGA_VERSION = 32'h0393020e; // changing MMCM phase -20.0 (use clk_fb)
		parameter FPGA_VERSION = 32'h03930215; // pclk phase -3.0 (multiple of 1.5)
		// parameter FPGA_VERSION = 32'h03930214; // pclk phase +3.0 (multiple of 1.5)
		// parameter FPGA_VERSION = 32'h03930213; // bug fixing in frame_start_pending_long
		// parameter FPGA_VERSION = 32'h03930212; // test mode interface, no-pending frames
		// parameter FPGA_VERSION = 32'h03930211; // test mode, IBUF_LOW_PWR=TRUE, CLKFBOUT_PHASE_SENSOR = -21.0
		// parameter FPGA_VERSION = 32'h03930210; // added test mode
		// parameter FPGA_VERSION = 32'h0393020f; // changing MMCM phase -19.5 (use clk_fb) IBUF_LOW_PWR=FALSE
		// parameter FPGA_VERSION = 32'h0393020e; // changing MMCM phase -19.5 (use clk_fb)
		// parameter FPGA_VERSION = 32'h0393020e; // changing MMCM phase -19.5 (use clk_fb)
		// parameter FPGA_VERSION = 32'h0393020d; // changing MMCM phase -18.0 (use clk_fb)
		// parameter FPGA_VERSION = 32'h0393020c; // changing MMCM phase 18.0 (use clk_fb)

includes/x393_parameters.vh

+14 −3

Original line number	Diff line number	Diff line
		@@ -303,6 +303,7 @@
		parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers
		parameter MCONTR_LINTILE_COPY_FRAME = 13, // copy frame number from the master channel (single event, not a persistent mode)
		parameter MCONTR_LINTILE_ABORT_LATE = 14, // abort frame if not finished by the new frame sync (wait pending memory)
		parameter MCONTR_LINTILE_NO_PENDING = 15, // ignore new frame start if previous frame is not finished

		parameter MCNTRL_SCANLINE_DLY_WIDTH = 12, // delay start pulse by 1..64 mclk

		@@ -512,6 +513,16 @@
		parameter SENS_UART_RECV_RST = 4, // 5: 4
		parameter SENS_UART_XMIT_START = 6, // 6
		parameter SENS_UART_RECV_NEXT = 7, // 7
		parameter SENS_ALT_STATUS = 24,
		parameter SENS_ALT_STATUS_SET = 25,
		parameter SENS_TEST_MODES = 26,
		parameter SENS_TEST_BITS = 3,
		parameter SENS_TEST_SET= 29,
		parameter SENS_TEST_WIDTH_BITS = 10,
		parameter SENS_TEST_HEIGHT_BITS= 10,
		parameter SENS_TEST_WIDTH_INC = 3,
		parameter SENS_TEST_HEIGHT_INC = 3,

		//`else
		parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
		parameter SENS_CTRL_QUADRANTS_WIDTH = 7, // 6,
		@@ -707,8 +718,8 @@
		parameter CLKIN_PERIOD_SENSOR = 37.037, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
		parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz)
		//MMCME2_ADV_i has a CLKFBOUT_PHASE value (-20.000) with CLKFBOUT_USE_FINE_PS set to FALSE. It should be a multiple of [45 / CLKFBOUT_MULT_F] = [45 / 30.000] = 1.500.
		parameter CLKFBOUT_PHASE_SENSOR = -19.5, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
		parameter IPCLK_PHASE = 0.000,
		parameter CLKFBOUT_PHASE_SENSOR = -21.0, // 19.5, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
		parameter IPCLK_PHASE = -3.000, // trying both ways (PCLK_PHASE inside sens_103993)
		parameter IPCLK2X_PHASE = 0.000,
		`ifdef TWEAKING_IOSTANDARD
		parameter PXD_IOSTANDARD = "LVCMOS25", // with 1.8 actually applied voltage
		@@ -794,7 +805,7 @@
		parameter HISPI_DQS_BIAS = "TRUE",
		parameter HISPI_IBUF_DELAY_VALUE = "0",
		`ifdef BOSON
		parameter HISPI_IBUF_LOW_PWR = "FALSE", // "TRUE",
		parameter HISPI_IBUF_LOW_PWR = "TRUE", // "FALSE", // "TRUE",
		`else
		parameter HISPI_IBUF_LOW_PWR = "TRUE", // "FALSE", // try
		`endif

memctrl/mcntrl393.v

+4 −0

Original line number	Diff line number	Diff line
		@@ -264,6 +264,7 @@ module mcntrl393 #(
		parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers
		parameter MCONTR_LINTILE_COPY_FRAME = 13, // copy frame number from the master channel (single event, not a persistent mode)
		parameter MCONTR_LINTILE_ABORT_LATE = 14, // abort frame if not finished by the new frame sync (wait pending memory)
		parameter MCONTR_LINTILE_NO_PENDING = 16, // ignore new frame start if previous frame is not finished
		parameter MCNTRL_SCANLINE_DLY_WIDTH = 12, // delay start pulse by 1..64 mclk
		parameter MCNTRL_SCANLINE_DLY_DEFAULT = 1024 // initial delay value for start pulse

		@@ -1122,6 +1123,7 @@ module mcntrl393 #(
		.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
		.MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE),
		.MCONTR_LINTILE_ABORT_LATE (MCONTR_LINTILE_ABORT_LATE),
		.MCONTR_LINTILE_NO_PENDING (MCONTR_LINTILE_NO_PENDING),
		.MCNTRL_SCANLINE_DLY_WIDTH (MCNTRL_SCANLINE_DLY_WIDTH),
		.MCNTRL_SCANLINE_DLY_DEFAULT (MCNTRL_SCANLINE_DLY_DEFAULT)
		) mcntrl_linear_wr_sensor_i (
		@@ -1281,6 +1283,7 @@ module mcntrl393 #(
		.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
		.MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE),
		.MCONTR_LINTILE_ABORT_LATE (MCONTR_LINTILE_ABORT_LATE),
		.MCONTR_LINTILE_NO_PENDING (MCONTR_LINTILE_NO_PENDING),
		.MCNTRL_SCANLINE_DLY_WIDTH (MCNTRL_SCANLINE_DLY_WIDTH),
		.MCNTRL_SCANLINE_DLY_DEFAULT (MCNTRL_SCANLINE_DLY_DEFAULT)

		@@ -1357,6 +1360,7 @@ module mcntrl393 #(
		.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
		.MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE),
		.MCONTR_LINTILE_ABORT_LATE (MCONTR_LINTILE_ABORT_LATE),
		.MCONTR_LINTILE_NO_PENDING (MCONTR_LINTILE_NO_PENDING),
		.MCNTRL_SCANLINE_DLY_WIDTH (MCNTRL_SCANLINE_DLY_WIDTH),
		.MCNTRL_SCANLINE_DLY_DEFAULT (MCNTRL_SCANLINE_DLY_DEFAULT)
		) mcntrl_linear_rw_chn3_i (

memctrl/mcntrl_linear_rw.v

+8 −5

Original line number	Diff line number	Diff line
		@@ -81,6 +81,7 @@ module mcntrl_linear_rw #(
		parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
		parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers
		parameter MCONTR_LINTILE_ABORT_LATE = 14, // abort frame if not finished by the new frame sync (wait pending memory)
		parameter MCONTR_LINTILE_NO_PENDING = 15, // ignore new frame start if previous frame is not finished

		// TODO NC393: This delay may be too long for serail sensors. Make them always start to fill the
		// first buffer page, waiting for the request from mcntrl_linear during that first page. And if it will arrive -
		@@ -182,6 +183,7 @@ module mcntrl_linear_rw #(
		wire chn_rst; // resets command, including fifo;
		reg chn_rst_d; // delayed by 1 cycle do detect turning off
		wire abort_en; // enable frame abort (mode register bit)
		wire no_pending; // ignore new frame start if previous frame is not finished
		reg aborting_r; // waiting pending memory transactions at if the frame was not finished at frame sync
		// reg xfer_reset_page_r;
		reg xfer_page_rst_r=1;
		@@ -245,7 +247,7 @@ module mcntrl_linear_rw #(
		wire msw_zero= !(\|cmd_data[31:16]); // MSW all bits are 0 - set carry bit


		reg [14:0] mode_reg;//mode register: {dis_need,repet,single,rst_frame,na[2:0],extra_pages[1:0],write_mode,enable,!reset}
		reg [16:0] mode_reg;//mode register: {no_pending,abort_en,copy_frame,skip_too_late,dis_need,repet,single,rst_frame,na[2:0],extra_pages[1:0],write_mode,enable,!reset}

		reg [NUM_RC_BURST_BITS-1:0] start_range_addr; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0
		reg [NUM_RC_BURST_BITS-1:0] frame_size; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0
		@@ -302,7 +304,7 @@ module mcntrl_linear_rw #(
		// Set parameter registers
		always @(posedge mclk) begin
		if (mrst) mode_reg <= 0;
		else if (set_mode_w) mode_reg <= cmd_data[14:0]; // 4:0]; // [4:0];
		else if (set_mode_w) mode_reg <= cmd_data[16:0]; // 4:0]; // [4:0];

		if (mrst) single_frame_r <= 0;
		else single_frame_r <= single_frame_w;
		@@ -429,6 +431,7 @@ module mcntrl_linear_rw #(
		assign disable_need = mode_reg[MCONTR_LINTILE_DIS_NEED];
		assign skip_too_late = mode_reg[MCONTR_LINTILE_SKIP_LATE];
		assign abort_en = mode_reg[MCONTR_LINTILE_ABORT_LATE];
		assign no_pending = mode_reg[MCONTR_LINTILE_NO_PENDING];

		`ifdef DEBUG_MCNTRL_LINEAR_EXTRA_STATUS
		assign status_data= {last_row_w, last_in_row,line_unfinished[7:0], frame_finished_r, busy_r};
		@@ -490,10 +493,10 @@ module mcntrl_linear_rw #(
		// if (mrst \|\| frame_start_delayed) frame_start_pending <= 0;
		if (mrst) frame_start_pending <= 0;
		// else frame_start_pending <= {frame_start_pending[0], busy_r && (frame_start_pending[0] \| frame_start_late)};
		else frame_start_pending <= busy_r && (frame_start_pending \| frame_start_late);
		else frame_start_pending <= !no_pending && busy_r && (frame_start_pending \| frame_start_late);

		if (mrst) frame_start_pending_long <= 0;
		else frame_start_pending_long <= {frame_start_pending_long[0], (busy_r \|\| skip_run) && (frame_start_pending_long[0] \| frame_start_late)};
		else frame_start_pending_long <= {frame_start_pending_long[0], ~no_pending & (busy_r \| skip_run) && (frame_start_pending_long[0] \| frame_start_late)};

		if (mrst) frame_start_r <= 0;
		// else frame_start_r <= {frame_start_r[3:0], frame_start_late & frame_en};

py393/update_predefines.sh

0 → 100755

+3 −0

Original line number	Diff line number	Diff line
		#!/bin/bash
		# Updates vrlg.py to include predefines for pydev. Needed when new parameters are added to the Verilog header files
		./test_mcntrl.py @cargs_test <<< $'pydev_predefines\nexit\n'

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