implemented sync reset, fpga version 0x03930136 (ae33ff53) · Commits · Elphel / x393

cocotb/x393_cocotb_lwir_04.sav

+58 −11

Original line number	Diff line number	Diff line
		[*]
		[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
		[*] Tue Apr 30 17:21:50 2019
		[*] Fri May 3 04:06:38 2019
		[*]
		[dumpfile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/simulation/x393_dut-20190430003141791.fst"
		[dumpfile_mtime] "Tue Apr 30 17:20:36 2019"
		[dumpfile_size] 1896466138
		[dumpfile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/simulation/x393_dut-20190502213839545.fst"
		[dumpfile_mtime] "Fri May 3 04:06:09 2019"
		[dumpfile_size] 19575412
		[savefile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/cocotb/x393_cocotb_lwir_04.sav"
		[timestart] 0
		[size] 1804 1171
		[pos] -1 -1
		*-28.897251 1413970273 1022561895 855534694 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
		*-25.245840 49300000 1022561895 855534694 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
		[treeopen] x393_dut.
		[treeopen] x393_dut.simul_lwir160x120_vospi1_i.
		[treeopen] x393_dut.x393_i.
		[treeopen] x393_dut.x393_i.compressor393_i.
		[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].
		[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.
		[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.
		@@ -87,9 +86,11 @@
		[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
		[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.lens_flat393_i.
		[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_sync_i.
		[treeopen] x393_dut.x393_i.timing393_i.
		[treeopen] x393_dut.x393_i.timing393_i.camsync393_i.
		[treeopen] x393_dut.x393_i.timing393_i.camsync393_i.i_frsync_pclk0.
		[sst_width] 204
		[treeopen] x393_dut.x393_i.timing393_i.rtc393_i.
		[sst_width] 402
		[signals_width] 335
		[sst_expanded] 1
		[sst_vpaned_height] 459
		@@ -3022,6 +3023,53 @@ x393_dut.sns1_sda
		@1401200
		-SENSOR3
		@800200
		-khz
		-timing
		@1000200
		-timing
		@800200
		-rtc393
		@28
		x393_dut.x393_i.timing393_i.rtc393_i.enable_rtc
		x393_dut.x393_i.timing393_i.rtc393_i.mclk
		x393_dut.x393_i.timing393_i.rtc393_i.khz
		@22
		x393_dut.x393_i.timing393_i.rtc393_i.khz_cntr[9:0]
		@28
		(0)x393_dut.x393_i.timing393_i.rtc393_i.inc_usec[1:0]
		@1000200
		-rtc393
		-khz
		@800200
		-reset_seq
		@28
		x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.set_ctrl_r
		x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.ms
		x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.start_rst_seq_mclk
		x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.start_rst_seq_pclk
		@800022
		x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.mrst_seq[1:0]
		@28
		(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.mrst_seq[1:0]
		(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.mrst_seq[1:0]
		@1001200
		-group_end
		@28
		x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.mrst_on_cntr
		@22
		x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.mrst_after_cntr[2:0]
		@28
		x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.start_spi_seq_mclk
		x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.start_spi_seq_pclk
		@29
		x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.spi_timeout_cntr[1:0]
		@28
		x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.spi_seq
		@200
		-
		@1000200
		-reset_seq
		@800200
		-sens_channel0
		-lepto3_0
		@28
		@@ -3094,14 +3142,13 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepto
		x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.segment_stb
		x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.segment_good_w
		x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.discard_set
		@200
		-
		@28
		x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.sof_w
		@22
		x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.raddr[10:0]
		@29
		@28
		x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.hact_r[2:0]
		@200
		-
		@800200
		-packet
		@28

fpga_version.vh

+4 −1

Original line number	Diff line number	Diff line
		@@ -35,7 +35,10 @@
		* contains all the components and scripts required to completely simulate it
		* with at least one of the Free Software programs.
		*/
		parameter FPGA_VERSION = 32'h03930133; // Testing sof to hact delay
		parameter FPGA_VERSION = 32'h03930136; // Fiixing spi_seq
		// parameter FPGA_VERSION = 32'h03930135; // Adding multi-cam reset
		// parameter FPGA_VERSION = 32'h0393014; // Adding multi-cam reset - buggy
		// parameter FPGA_VERSION = 32'h03930133; // Works with linux kernel rocko commit of 05/01/2019 bd61276e05f7343415929112ae368230a9c472f0
		// parameter FPGA_VERSION = 32'h03930132; // Sync from serial bumber start, added output (with hact)
		// parameter FPGA_VERSION = 32'h03930131; // Sync from serial bumber start
		// parameter FPGA_VERSION = 32'h03930130; // Adding output for receive start frame

includes/x393_parameters.vh

+13 −3

Original line number	Diff line number	Diff line
		@@ -548,8 +548,8 @@
		//`elsif LWIR
		parameter VOSPI_MRST = 0,
		parameter VOSPI_MRST_BITS = 2,
		parameter VOSPI_PWDN = 2,
		parameter VOSPI_PWDN_BITS = 2,
		parameter VOSPI_RST_SEQ = 2, // initiate reset cycle (master drives all sensors), generate frame start when ready
		parameter VOSPI_SPI_SEQ = 3, // initilate SPI re-sync (will automatically generate frame syncs when re-synced)
		parameter VOSPI_MCLK = 4,
		parameter VOSPI_MCLK_BITS = 2,
		parameter VOSPI_EN = 6,
		@@ -589,6 +589,16 @@
		parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
		`endif
		parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
		`ifdef SIMULATION
		parameter VOSPI_MRST_MS = 1, // master reset duration in ms
		parameter VOSPI_MRST_AFTER_MS = 5, // Wait after master reset and generate SOF pulse to advance sequencer
		parameter VOSPI_SPI_TIMEOUT_MS = 3, // Wait to tymeout SPI when needed to re-sync
		`else
		parameter VOSPI_MRST_MS = 5, // master reset duration in ms
		parameter VOSPI_MRST_AFTER_MS = 2000, // Wait after master reset and generate SOF pulse to advance sequencer
		parameter VOSPI_SPI_TIMEOUT_MS = 185, // Wait to tymeout SPI when needed to re-sync
		`endif

		//`else
		//sensor_fifo parameters (for parallel12)
		parameter SENSOR_DATA_WIDTH = 12,

py393/vrlg.py

+23 −14

Original line number	Diff line number	Diff line
		@@ -576,7 +576,6 @@ SENSOR_IMAGE_TYPE1__TYPE = str
		MCONTR_TOP_16BIT_REFRESH_ADDRESS__TYPE = str
		MCONTR_LINTILE_DIS_NEED__TYPE = str
		DFLT_DQS_PATTERN__RAW = str
		CMPRS_TABLES__TYPE = str
		MCNTRL_PS_STATUS_CNTRL__TYPE = str
		MCONTR_PHY_16BIT_ADDR = int
		REF_JITTER1__TYPE = str
		@@ -616,6 +615,7 @@ SENS_CTRL_GP1__TYPE = str
		MCNTRL_TEST01_MASK__TYPE = str
		SENSOR_16BIT_BIT_SET__RAW = str
		LWIR_TELEMETRY__TYPE = str
		HISPI_IBUF_LOW_PWR__TYPE = str
		MULTICLK_BUF_DLYREF__RAW = str
		SENSOR_FIFO_DELAY__RAW = str
		DLY_SET = int
		@@ -737,6 +737,7 @@ MULT_SAXI_HALF_BRAM_IN__RAW = str
		HISTOGRAM_HEIGHT = int
		SENSI2C_TBL_SA__RAW = str
		CMPRS_CBIT_CMODE_JP4__RAW = str
		VOSPI_RST_SEQ__RAW = str
		MULTICLK_BUF_AXIHP__RAW = str
		CLK_STATUS__TYPE = str
		VOSPI_OUT_EN_BITS = int
		@@ -762,11 +763,13 @@ SENS_SYNC_RADDR__TYPE = str
		BUF_IPCLK_SENS0__TYPE = str
		SENSI2C_CMD_RUN__RAW = str
		VOSPI_SEGM0_OK = int
		VOSPI_RST_SEQ = int
		MCNTRL_TILED_STARTADDR__TYPE = str
		DLY_LD_MASK = int
		VOSPI_MRST_BITS__TYPE = str
		CAMSYNC_TRIG_DELAY3__RAW = str
		NUM_CYCLES_09__RAW = str
		VOSPI_SPI_SEQ = int
		SENS_SYNC_LBITS__RAW = str
		MEMBRIDGE_SIZE64__TYPE = str
		SENS_GAMMA_HEIGHT2 = int
		@@ -835,7 +838,6 @@ REFRESH_OFFSET = int
		MCNTRL_PS_EN_RST = int
		MCONTR_SENS_BASE__RAW = str
		SENS_GAMMA_ADDR_MASK__TYPE = str
		VOSPI_PWDN__RAW = str
		CMPRS_CSAT_CR = int
		CMPRS_CBIT_RUN_ENABLE = int
		INITIALIZE_OFFSET = int
		@@ -950,7 +952,7 @@ VOSPI_MRST_BITS__RAW = str
		HISTOGRAM_RADDR2__RAW = str
		SENSI2C_STATUS = int
		CMPRS_CBIT_CMODE_JP4DIFF__TYPE = str
		MULTICLK_DIV_XCLK__TYPE = str
		MEMBRIDGE_LEN64 = int
		SENS_SYNC_LATE_DFLT = int
		SENSI2C_STATUS_REG_BASE__RAW = str
		AFI_LO_ADDR64__RAW = str
		@@ -1051,7 +1053,7 @@ NUM_CYCLES_19__RAW = str
		SIMULATE_CMPRS_CMODE2__RAW = str
		MCNTRL_PS_MASK__RAW = str
		CMPRS_CBIT_CMODE_JPEG20__TYPE = str
		HISPI_IBUF_LOW_PWR__TYPE = str
		VOSPI_SPI_SEQ__TYPE = str
		CMPRS_TIMEOUT_BITS__RAW = str
		MEMBRIDGE_LO_ADDR64__RAW = str
		LWIR_TELEMETRY_VIDEO_FORMAT = int
		@@ -1201,6 +1203,7 @@ CAMSYNC_DELAY = int
		BUF_IPCLK2X_SENS2__TYPE = str
		SENSI2C_CMD_USE_EOF__TYPE = str
		MULTICLK_PHASE_AXIHP__RAW = str
		VOSPI_MRST_MS = int
		QUADRANTS_PXD_HACT_VACT = int
		FFCLK0_IOSTANDARD__RAW = str
		MULTICLK_DIV_XCLK__RAW = str
		@@ -1214,6 +1217,7 @@ MULTICLK_BUF_XCLK__TYPE = str
		MCONTR_TOP_0BIT_ADDR__TYPE = str
		VOSPI_VSYNC__RAW = str
		CLKFBOUT_PHASE_SENSOR__RAW = str
		CMPRS_AFIMUX_REG_ADDR0 = int
		MCONTR_SENS_BASE = int
		CMPRS_CBIT_RUN__TYPE = str
		SENS_LENS_FAT0_OUT = int
		@@ -1405,6 +1409,7 @@ NUM_CYCLES_29__TYPE = str
		RTC_SET_SEC__TYPE = str
		CAMSYNC_ADDR = int
		FFCLK1_CAPACITANCE__RAW = str
		VOSPI_SPI_SEQ__RAW = str
		VOSPI_PACKET_LAST__RAW = str
		RTC_SET_CORR__TYPE = str
		PHASE_WIDTH__RAW = str
		@@ -1429,7 +1434,6 @@ SENSI2C_TBL_RAH_BITS__TYPE = str
		LWIR_WINDOW_WIDTH = int
		CMPRS_AFIMUX_WIDTH = int
		HISTOGRAM_ADDR_MASK__TYPE = str
		VOSPI_PWDN__TYPE = str
		HISTOGRAM_RADDR3__TYPE = str
		CMPRS_CBIT_CMODE_MONO1__TYPE = str
		SENSOR_TIMING_START = int
		@@ -1474,6 +1478,7 @@ LAST_BUF_FRAME = int
		SENS_REF_JITTER1 = float
		SENS_REF_JITTER2 = float
		MCNTRL_TILED_FRAME_SIZE__RAW = str
		VOSPI_MRST_AFTER_MS = int
		MULT_SAXI_HALF_BRAM__RAW = str
		SIMUL_AXI_READ_WIDTH__TYPE = str
		DFLT_DQS_TRI_ON_PATTERN__RAW = str
		@@ -1777,7 +1782,7 @@ HIST_SAXI_AWCACHE = int
		SENSI2C_CMD_RUN_PBITS = int
		CMPRS_MONO8__RAW = str
		CMPRS_AFIMUX_REG_ADDR1 = int
		CMPRS_AFIMUX_REG_ADDR0 = int
		SENS_LENS_FAT0_OUT__TYPE = str
		SENS_BANDWIDTH__TYPE = str
		LD_DLY_LANE0_IDELAY__TYPE = str
		CLKFBOUT_PHASE__RAW = str
		@@ -1987,6 +1992,7 @@ SENS_CTRL_QUADRANTS_EN = int
		MCNTRL_SCANLINE_WINDOW_WH__RAW = str
		MULTICLK_PHASE_FB__TYPE = str
		SENSI2C_TBL_NBWR_BITS = int
		VOSPI_RST_SEQ__TYPE = str
		BUF_IPCLK2X_SENS2 = str
		BUF_IPCLK2X_SENS3 = str
		BUF_IPCLK2X_SENS0 = str
		@@ -2035,6 +2041,7 @@ MCONTR_BUF0_RD_ADDR__TYPE = str
		CMPRS_STATUS_REG_INC__TYPE = str
		DLY_LANE0_IDELAY__TYPE = str
		MCNTRL_PS_ADDR__TYPE = str
		VOSPI_SPI_TIMEOUT_MS = int
		WINDOW_WIDTH__RAW = str
		MULTICLK_MULT__RAW = str
		MCONTR_PHY_16BIT_ADDR__RAW = str
		@@ -2043,9 +2050,8 @@ SENS_GAMMA_HEIGHT2__TYPE = str
		VOSPI_GPIO_BITS__TYPE = str
		IPCLK2X_PHASE__TYPE = str
		SENSOR_HIST_BITS_SET = int
		VOSPI_DBG_SRC__TYPE = str
		CLK_MASK = int
		MCNTRL_SCANLINE_CHN1_ADDR = int
		VOSPI_PWDN_BITS__TYPE = str
		VOSPI_MCLK__TYPE = str
		MULT_SAXI_HALF_BRAM_IN = int
		CMDFRAMESEQ_ADDR_INC__RAW = str
		@@ -2131,6 +2137,7 @@ CAMSYNC_SNDEN_BIT = int
		DQSTRI_FIRST__RAW = str
		SENSI2C_CTRL_MASK__TYPE = str
		LWIR_TELEMETRY_SREV = int
		VOSPI_SPI_TIMEOUT_MS__RAW = str
		SENS_LENS_SCALES__TYPE = str
		SENS_LENS_COEFF__TYPE = str
		LOGGER_STATUS__RAW = str
		@@ -2146,12 +2153,14 @@ MCNTRL_TEST01_CHN3_MODE__TYPE = str
		MCONTR_BUF2_RD_ADDR__TYPE = str
		SENS_SYNC_RADDR__RAW = str
		SENS_HIGH_PERFORMANCE_MODE__RAW = str
		VOSPI_MRST_AFTER_MS__RAW = str
		MCNTRL_TEST01_CHN2_STATUS_CNTRL = int
		CLKFBOUT_PHASE_SENSOR__TYPE = str
		SENSOR_HIST_NRST_BITS__TYPE = str
		GPIO_PORTEN = int
		RTC_STATUS_REG_ADDR__TYPE = str
		SENS_JTAG_TCK__TYPE = str
		VOSPI_SPI_TIMEOUT_MS__TYPE = str
		MCNTRL_TILED_FRAME_SIZE__TYPE = str
		CMPRS_AFIMUX_REG_ADDR1__RAW = str
		WOI_HEIGHT__RAW = str
		@@ -2172,6 +2181,7 @@ MCNTRL_SCANLINE_CHN3_ADDR = int
		NUM_CYCLES_26__RAW = str
		DEFAULT_STATUS_MODE__RAW = str
		MCONTR_LINTILE_KEEP_OPEN__RAW = str
		VOSPI_MRST_AFTER_MS__TYPE = str
		MCONTR_PHY_16BIT_ADDR__TYPE = str
		VOSPI_PACKET_TTT__TYPE = str
		CMDFRAMESEQ_RST_BIT__RAW = str
		@@ -2185,7 +2195,6 @@ MCONTR_PHY_16BIT_PATTERNS_TRI__RAW = str
		CMDSEQMUX_MASK = int
		MCNTRL_SCANLINE_PENDING_CNTR_BITS__RAW = str
		MEMCLK_CAPACITANCE__RAW = str
		VOSPI_PWDN_BITS__RAW = str
		DQTRI_FIRST = int
		CONTROL_RBACK_DEPTH = int
		CAMSYNC_TRIG_DELAY0 = int
		@@ -2249,6 +2258,7 @@ HISPI_DQS_BIAS__RAW = str
		MCONTR_LINTILE_WRITE = int
		TILE_VSTEP__TYPE = str
		MCONTR_PHY_STATUS_CNTRL__RAW = str
		VOSPI_MRST_MS__TYPE = str
		DLY_LANE0_DQS_WLV_IDELAY = long
		MCNTRL_SCANLINE_STATUS_CNTRL = int
		CMDSEQMUX_MASK__TYPE = str
		@@ -2321,7 +2331,7 @@ CMPRS_CBIT_RUN_BITS = int
		SENS_LENS_AY_MASK = int
		BUF_IPCLK2X_SENS3__RAW = str
		MCNTRL_SCANLINE_CHN1_ADDR__RAW = str
		MEMBRIDGE_LEN64 = int
		MULTICLK_DIV_XCLK__TYPE = str
		HISPI_MMCM2__TYPE = str
		SENSOR_NUM_HISTOGRAM__TYPE = str
		HIST_SAXI_EN = int
		@@ -2381,7 +2391,6 @@ CLK_DIV_PHASE__RAW = str
		STATUS_MSB_RSHFT__RAW = str
		SLEW_CMDA__RAW = str
		HISPI_MMCM0__RAW = str
		VOSPI_PWDN_BITS = int
		MCONTR_PHY_16BIT_PATTERNS_TRI = int
		MCONTR_TOP_STATUS_REG_ADDR__RAW = str
		DFLT_DQS_TRI_ON_PATTERN = int
		@@ -2391,6 +2400,7 @@ DFLT_CHN_EN = int
		GPIO_STATUS_REG_ADDR__RAW = str
		DLY_DQS_ODELAY = long
		SENSOR_CHN_EN_BIT__RAW = str
		VOSPI_MRST_MS__RAW = str
		CMPRS_AFIMUX_RADDR1 = int
		CAMSYNC_TRIG_SRC__TYPE = str
		SENSI2C_CMD_FIFO_RD = int
		@@ -2403,7 +2413,6 @@ SENSI2C_CMD_TAND__RAW = str
		WINDOW_HEIGHT__TYPE = str
		SENSOR_IMAGE_TYPE2__TYPE = str
		IBUF_LOW_PWR__TYPE = str
		VOSPI_PWDN = int
		FFCLK1_IBUF_LOW_PWR__TYPE = str
		CLK_DIV_PHASE = float
		VOSPI_MRST = int
		@@ -2519,7 +2528,7 @@ VOSPI_HACT_TO_HACT_EOF__TYPE = str
		CMPRS_TABLES__RAW = str
		SENS_GAMMA_MODE_EN__TYPE = str
		CMDFRAMESEQ_IRQ_BIT__TYPE = str
		CLK_MASK = int
		VOSPI_DBG_SRC__TYPE = str
		MCONTR_BUF4_WR_ADDR__TYPE = str
		MCNTRL_TILED_CHN2_ADDR = int
		LWIR_TELEMETRY_AGC_ROI_BOTTOM__RAW = str
		@@ -2598,7 +2607,7 @@ MULT_SAXI_MASK__RAW = str
		SENSOR12BITS_TMD = int
		MCONTR_CMPRS_STATUS_BASE__TYPE = str
		NUM_CYCLES_10__RAW = str
		SENS_LENS_FAT0_OUT__TYPE = str
		CMPRS_TABLES__TYPE = str
		VOSPI_SPI_CLK = int
		DEBUG_SHIFT_DATA__RAW = str
		SENSOR_16BIT_BIT__TYPE = str

py393/x393_export_c.py

+3 −4

Original line number	Diff line number	Diff line
		@@ -2126,10 +2126,9 @@ class X393ExportC(object):

		def _enc_sensio_ctrl_vospi(self):
		dw=[]
		dw.append(("mrst", vrlg.VOSPI_MRST, 1, 0, "RESET signal level to the sensor (0 - low(active), 1 - high (inactive)"))
		dw.append(("mrst_set", vrlg.VOSPI_MRST + 1, 1, 0, "When set to 1, RESET is set to the 'rst' field value"))
		dw.append(("pwdn", vrlg.VOSPI_PWDN, 1, 0, "POWER DOWN signal level to the sensor (0 - low(active), 1 - high (inactive)"))
		dw.append(("pwdn_set", vrlg.VOSPI_PWDN + 1, 1, 0, "When set to 1, POWER DOWN is set to the 'pwdn' field value"))
		dw.append(("reset", vrlg.VOSPI_MRST, 2, 0, "Sensor reset/power down control (0 - NOP, 1 - power down + reset, 2 - no pwdn, reset, 3 - no pwdn, no reset"))
		dw.append(("rst_seq", vrlg.VOSPI_RST_SEQ, 1, 0, "Initiate simultaneous all sensors reset, generate SOF after pause"))
		dw.append(("spi_seq", vrlg.VOSPI_SPI_SEQ, 1, 0, "Initiate VOSPI reset, will generate normal SOF if successful"))
		dw.append(("mclk", vrlg.VOSPI_MCLK, 1, 0, "Enable master clock (25MHz) to sensor"))
		dw.append(("mclk_set", vrlg.VOSPI_MCLK + 1, 1, 0, "When set to 1, MCLK enable is set to the 'mclk' field value"))
		dw.append(("spi_en", vrlg.VOSPI_EN, 2, 0, "SPI reset/enable: 0 - NOP, 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable"))

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