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Elphel
x393
Commits
ae33ff53
Commit
ae33ff53
authored
May 03, 2019
by
Andrey Filippov
Browse files
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Plain Diff
implemented sync reset, fpga version 0x03930136
parent
823ad682
Changes
16
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16 changed files
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1475 additions
and
1294 deletions
+1475
-1294
x393_cocotb_lwir_04.sav
cocotb/x393_cocotb_lwir_04.sav
+58
-11
fpga_version.vh
fpga_version.vh
+4
-1
x393_parameters.vh
includes/x393_parameters.vh
+13
-3
vrlg.py
py393/vrlg.py
+23
-14
x393_export_c.py
py393/x393_export_c.py
+3
-4
x393_sens_cmprs.py
py393/x393_sens_cmprs.py
+4
-7
x393_sensor.py
py393/x393_sensor.py
+24
-17
sens_lepton3.v
sensor/sens_lepton3.v
+138
-77
sensor_channel.v
sensor/sensor_channel.v
+36
-59
sensors393.v
sensor/sensors393.v
+52
-34
rtc393.v
timing/rtc393.v
+26
-4
timing393.v
timing/timing393.v
+5
-3
x393.v
x393.v
+9
-5
x393_vospi.bit
x393_vospi.bit
+0
-0
x393_vospi.timing_summary_impl
x393_vospi.timing_summary_impl
+1044
-1019
x393_vospi_utilization.report
x393_vospi_utilization.report
+36
-36
No files found.
cocotb/x393_cocotb_lwir_04.sav
View file @
ae33ff53
[*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*]
Tue Apr 30 17:21:50
2019
[*]
Fri May 3 04:06:38
2019
[*]
[dumpfile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/simulation/x393_dut-20190
430003141791
.fst"
[dumpfile_mtime] "
Tue Apr 30 17:20:36
2019"
[dumpfile_size] 1
896466138
[dumpfile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/simulation/x393_dut-20190
502213839545
.fst"
[dumpfile_mtime] "
Fri May 3 04:06:09
2019"
[dumpfile_size] 1
9575412
[savefile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/cocotb/x393_cocotb_lwir_04.sav"
[timestart] 0
[size] 1804 1171
[pos] -1 -1
*-2
8.897251 1413970273
1022561895 855534694 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-2
5.245840 49300000
1022561895 855534694 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_dut.
[treeopen] x393_dut.simul_lwir160x120_vospi1_i.
[treeopen] x393_dut.x393_i.
[treeopen] x393_dut.x393_i.compressor393_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.
...
...
@@ -87,9 +86,11 @@
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.lens_flat393_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_sync_i.
[treeopen] x393_dut.x393_i.timing393_i.
[treeopen] x393_dut.x393_i.timing393_i.camsync393_i.
[treeopen] x393_dut.x393_i.timing393_i.camsync393_i.i_frsync_pclk0.
[sst_width] 204
[treeopen] x393_dut.x393_i.timing393_i.rtc393_i.
[sst_width] 402
[signals_width] 335
[sst_expanded] 1
[sst_vpaned_height] 459
...
...
@@ -3022,6 +3023,53 @@ x393_dut.sns1_sda
@1401200
-SENSOR3
@800200
-khz
-timing
@1000200
-timing
@800200
-rtc393
@28
x393_dut.x393_i.timing393_i.rtc393_i.enable_rtc
x393_dut.x393_i.timing393_i.rtc393_i.mclk
x393_dut.x393_i.timing393_i.rtc393_i.khz
@22
x393_dut.x393_i.timing393_i.rtc393_i.khz_cntr[9:0]
@28
(0)x393_dut.x393_i.timing393_i.rtc393_i.inc_usec[1:0]
@1000200
-rtc393
-khz
@800200
-reset_seq
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.set_ctrl_r
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.ms
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.start_rst_seq_mclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.start_rst_seq_pclk
@800022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.mrst_seq[1:0]
@28
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.mrst_seq[1:0]
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.mrst_seq[1:0]
@1001200
-group_end
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.mrst_on_cntr
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.mrst_after_cntr[2:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.start_spi_seq_mclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.start_spi_seq_pclk
@29
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.spi_timeout_cntr[1:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.spi_seq
@200
-
@1000200
-reset_seq
@800200
-sens_channel0
-lepto3_0
@28
...
...
@@ -3094,14 +3142,13 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepto
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.segment_stb
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.segment_good_w
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.discard_set
@200
-
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.sof_w
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.raddr[10:0]
@2
9
@2
8
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.hact_r[2:0]
@200
-
@800200
-packet
@28
...
...
fpga_version.vh
View file @
ae33ff53
...
...
@@ -35,7 +35,10 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h03930133; // Testing sof to hact delay
parameter FPGA_VERSION = 32'h03930136; // Fiixing spi_seq
// parameter FPGA_VERSION = 32'h03930135; // Adding multi-cam reset
// parameter FPGA_VERSION = 32'h0393014; // Adding multi-cam reset - buggy
// parameter FPGA_VERSION = 32'h03930133; // Works with linux kernel rocko commit of 05/01/2019 bd61276e05f7343415929112ae368230a9c472f0
// parameter FPGA_VERSION = 32'h03930132; // Sync from serial bumber start, added output (with hact)
// parameter FPGA_VERSION = 32'h03930131; // Sync from serial bumber start
// parameter FPGA_VERSION = 32'h03930130; // Adding output for receive start frame
...
...
includes/x393_parameters.vh
View file @
ae33ff53
...
...
@@ -548,8 +548,8 @@
//`elsif LWIR
parameter VOSPI_MRST = 0,
parameter VOSPI_MRST_BITS = 2,
parameter VOSPI_
PWDN = 2,
parameter VOSPI_
PWDN_BITS = 2,
parameter VOSPI_
RST_SEQ = 2, // initiate reset cycle (master drives all sensors), generate frame start when ready
parameter VOSPI_
SPI_SEQ = 3, // initilate SPI re-sync (will automatically generate frame syncs when re-synced)
parameter VOSPI_MCLK = 4,
parameter VOSPI_MCLK_BITS = 2,
parameter VOSPI_EN = 6,
...
...
@@ -588,7 +588,17 @@
parameter VOSPI_SOF_TO_HACT = 100, // 10, // clock cycles from SOF to HACT (limited to 8 bits)
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
`endif
parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
`ifdef SIMULATION
parameter VOSPI_MRST_MS = 1, // master reset duration in ms
parameter VOSPI_MRST_AFTER_MS = 5, // Wait after master reset and generate SOF pulse to advance sequencer
parameter VOSPI_SPI_TIMEOUT_MS = 3, // Wait to tymeout SPI when needed to re-sync
`else
parameter VOSPI_MRST_MS = 5, // master reset duration in ms
parameter VOSPI_MRST_AFTER_MS = 2000, // Wait after master reset and generate SOF pulse to advance sequencer
parameter VOSPI_SPI_TIMEOUT_MS = 185, // Wait to tymeout SPI when needed to re-sync
`endif
//`else
//sensor_fifo parameters (for parallel12)
parameter SENSOR_DATA_WIDTH = 12,
...
...
py393/vrlg.py
View file @
ae33ff53
...
...
@@ -576,7 +576,6 @@ SENSOR_IMAGE_TYPE1__TYPE = str
MCONTR_TOP_16BIT_REFRESH_ADDRESS__TYPE
=
str
MCONTR_LINTILE_DIS_NEED__TYPE
=
str
DFLT_DQS_PATTERN__RAW
=
str
CMPRS_TABLES__TYPE
=
str
MCNTRL_PS_STATUS_CNTRL__TYPE
=
str
MCONTR_PHY_16BIT_ADDR
=
int
REF_JITTER1__TYPE
=
str
...
...
@@ -616,6 +615,7 @@ SENS_CTRL_GP1__TYPE = str
MCNTRL_TEST01_MASK__TYPE
=
str
SENSOR_16BIT_BIT_SET__RAW
=
str
LWIR_TELEMETRY__TYPE
=
str
HISPI_IBUF_LOW_PWR__TYPE
=
str
MULTICLK_BUF_DLYREF__RAW
=
str
SENSOR_FIFO_DELAY__RAW
=
str
DLY_SET
=
int
...
...
@@ -737,6 +737,7 @@ MULT_SAXI_HALF_BRAM_IN__RAW = str
HISTOGRAM_HEIGHT
=
int
SENSI2C_TBL_SA__RAW
=
str
CMPRS_CBIT_CMODE_JP4__RAW
=
str
VOSPI_RST_SEQ__RAW
=
str
MULTICLK_BUF_AXIHP__RAW
=
str
CLK_STATUS__TYPE
=
str
VOSPI_OUT_EN_BITS
=
int
...
...
@@ -762,11 +763,13 @@ SENS_SYNC_RADDR__TYPE = str
BUF_IPCLK_SENS0__TYPE
=
str
SENSI2C_CMD_RUN__RAW
=
str
VOSPI_SEGM0_OK
=
int
VOSPI_RST_SEQ
=
int
MCNTRL_TILED_STARTADDR__TYPE
=
str
DLY_LD_MASK
=
int
VOSPI_MRST_BITS__TYPE
=
str
CAMSYNC_TRIG_DELAY3__RAW
=
str
NUM_CYCLES_09__RAW
=
str
VOSPI_SPI_SEQ
=
int
SENS_SYNC_LBITS__RAW
=
str
MEMBRIDGE_SIZE64__TYPE
=
str
SENS_GAMMA_HEIGHT2
=
int
...
...
@@ -835,7 +838,6 @@ REFRESH_OFFSET = int
MCNTRL_PS_EN_RST
=
int
MCONTR_SENS_BASE__RAW
=
str
SENS_GAMMA_ADDR_MASK__TYPE
=
str
VOSPI_PWDN__RAW
=
str
CMPRS_CSAT_CR
=
int
CMPRS_CBIT_RUN_ENABLE
=
int
INITIALIZE_OFFSET
=
int
...
...
@@ -950,7 +952,7 @@ VOSPI_MRST_BITS__RAW = str
HISTOGRAM_RADDR2__RAW
=
str
SENSI2C_STATUS
=
int
CMPRS_CBIT_CMODE_JP4DIFF__TYPE
=
str
M
ULTICLK_DIV_XCLK__TYPE
=
str
M
EMBRIDGE_LEN64
=
int
SENS_SYNC_LATE_DFLT
=
int
SENSI2C_STATUS_REG_BASE__RAW
=
str
AFI_LO_ADDR64__RAW
=
str
...
...
@@ -1051,7 +1053,7 @@ NUM_CYCLES_19__RAW = str
SIMULATE_CMPRS_CMODE2__RAW
=
str
MCNTRL_PS_MASK__RAW
=
str
CMPRS_CBIT_CMODE_JPEG20__TYPE
=
str
HISPI_IBUF_LOW_PWR
__TYPE
=
str
VOSPI_SPI_SEQ
__TYPE
=
str
CMPRS_TIMEOUT_BITS__RAW
=
str
MEMBRIDGE_LO_ADDR64__RAW
=
str
LWIR_TELEMETRY_VIDEO_FORMAT
=
int
...
...
@@ -1201,6 +1203,7 @@ CAMSYNC_DELAY = int
BUF_IPCLK2X_SENS2__TYPE
=
str
SENSI2C_CMD_USE_EOF__TYPE
=
str
MULTICLK_PHASE_AXIHP__RAW
=
str
VOSPI_MRST_MS
=
int
QUADRANTS_PXD_HACT_VACT
=
int
FFCLK0_IOSTANDARD__RAW
=
str
MULTICLK_DIV_XCLK__RAW
=
str
...
...
@@ -1214,6 +1217,7 @@ MULTICLK_BUF_XCLK__TYPE = str
MCONTR_TOP_0BIT_ADDR__TYPE
=
str
VOSPI_VSYNC__RAW
=
str
CLKFBOUT_PHASE_SENSOR__RAW
=
str
CMPRS_AFIMUX_REG_ADDR0
=
int
MCONTR_SENS_BASE
=
int
CMPRS_CBIT_RUN__TYPE
=
str
SENS_LENS_FAT0_OUT
=
int
...
...
@@ -1405,6 +1409,7 @@ NUM_CYCLES_29__TYPE = str
RTC_SET_SEC__TYPE
=
str
CAMSYNC_ADDR
=
int
FFCLK1_CAPACITANCE__RAW
=
str
VOSPI_SPI_SEQ__RAW
=
str
VOSPI_PACKET_LAST__RAW
=
str
RTC_SET_CORR__TYPE
=
str
PHASE_WIDTH__RAW
=
str
...
...
@@ -1429,7 +1434,6 @@ SENSI2C_TBL_RAH_BITS__TYPE = str
LWIR_WINDOW_WIDTH
=
int
CMPRS_AFIMUX_WIDTH
=
int
HISTOGRAM_ADDR_MASK__TYPE
=
str
VOSPI_PWDN__TYPE
=
str
HISTOGRAM_RADDR3__TYPE
=
str
CMPRS_CBIT_CMODE_MONO1__TYPE
=
str
SENSOR_TIMING_START
=
int
...
...
@@ -1474,6 +1478,7 @@ LAST_BUF_FRAME = int
SENS_REF_JITTER1
=
float
SENS_REF_JITTER2
=
float
MCNTRL_TILED_FRAME_SIZE__RAW
=
str
VOSPI_MRST_AFTER_MS
=
int
MULT_SAXI_HALF_BRAM__RAW
=
str
SIMUL_AXI_READ_WIDTH__TYPE
=
str
DFLT_DQS_TRI_ON_PATTERN__RAW
=
str
...
...
@@ -1777,7 +1782,7 @@ HIST_SAXI_AWCACHE = int
SENSI2C_CMD_RUN_PBITS
=
int
CMPRS_MONO8__RAW
=
str
CMPRS_AFIMUX_REG_ADDR1
=
int
CMPRS_AFIMUX_REG_ADDR0
=
int
SENS_LENS_FAT0_OUT__TYPE
=
str
SENS_BANDWIDTH__TYPE
=
str
LD_DLY_LANE0_IDELAY__TYPE
=
str
CLKFBOUT_PHASE__RAW
=
str
...
...
@@ -1987,6 +1992,7 @@ SENS_CTRL_QUADRANTS_EN = int
MCNTRL_SCANLINE_WINDOW_WH__RAW
=
str
MULTICLK_PHASE_FB__TYPE
=
str
SENSI2C_TBL_NBWR_BITS
=
int
VOSPI_RST_SEQ__TYPE
=
str
BUF_IPCLK2X_SENS2
=
str
BUF_IPCLK2X_SENS3
=
str
BUF_IPCLK2X_SENS0
=
str
...
...
@@ -2035,6 +2041,7 @@ MCONTR_BUF0_RD_ADDR__TYPE = str
CMPRS_STATUS_REG_INC__TYPE
=
str
DLY_LANE0_IDELAY__TYPE
=
str
MCNTRL_PS_ADDR__TYPE
=
str
VOSPI_SPI_TIMEOUT_MS
=
int
WINDOW_WIDTH__RAW
=
str
MULTICLK_MULT__RAW
=
str
MCONTR_PHY_16BIT_ADDR__RAW
=
str
...
...
@@ -2043,9 +2050,8 @@ SENS_GAMMA_HEIGHT2__TYPE = str
VOSPI_GPIO_BITS__TYPE
=
str
IPCLK2X_PHASE__TYPE
=
str
SENSOR_HIST_BITS_SET
=
int
VOSPI_DBG_SRC__TYPE
=
str
CLK_MASK
=
int
MCNTRL_SCANLINE_CHN1_ADDR
=
int
VOSPI_PWDN_BITS__TYPE
=
str
VOSPI_MCLK__TYPE
=
str
MULT_SAXI_HALF_BRAM_IN
=
int
CMDFRAMESEQ_ADDR_INC__RAW
=
str
...
...
@@ -2131,6 +2137,7 @@ CAMSYNC_SNDEN_BIT = int
DQSTRI_FIRST__RAW
=
str
SENSI2C_CTRL_MASK__TYPE
=
str
LWIR_TELEMETRY_SREV
=
int
VOSPI_SPI_TIMEOUT_MS__RAW
=
str
SENS_LENS_SCALES__TYPE
=
str
SENS_LENS_COEFF__TYPE
=
str
LOGGER_STATUS__RAW
=
str
...
...
@@ -2146,12 +2153,14 @@ MCNTRL_TEST01_CHN3_MODE__TYPE = str
MCONTR_BUF2_RD_ADDR__TYPE
=
str
SENS_SYNC_RADDR__RAW
=
str
SENS_HIGH_PERFORMANCE_MODE__RAW
=
str
VOSPI_MRST_AFTER_MS__RAW
=
str
MCNTRL_TEST01_CHN2_STATUS_CNTRL
=
int
CLKFBOUT_PHASE_SENSOR__TYPE
=
str
SENSOR_HIST_NRST_BITS__TYPE
=
str
GPIO_PORTEN
=
int
RTC_STATUS_REG_ADDR__TYPE
=
str
SENS_JTAG_TCK__TYPE
=
str
VOSPI_SPI_TIMEOUT_MS__TYPE
=
str
MCNTRL_TILED_FRAME_SIZE__TYPE
=
str
CMPRS_AFIMUX_REG_ADDR1__RAW
=
str
WOI_HEIGHT__RAW
=
str
...
...
@@ -2172,6 +2181,7 @@ MCNTRL_SCANLINE_CHN3_ADDR = int
NUM_CYCLES_26__RAW
=
str
DEFAULT_STATUS_MODE__RAW
=
str
MCONTR_LINTILE_KEEP_OPEN__RAW
=
str
VOSPI_MRST_AFTER_MS__TYPE
=
str
MCONTR_PHY_16BIT_ADDR__TYPE
=
str
VOSPI_PACKET_TTT__TYPE
=
str
CMDFRAMESEQ_RST_BIT__RAW
=
str
...
...
@@ -2185,7 +2195,6 @@ MCONTR_PHY_16BIT_PATTERNS_TRI__RAW = str
CMDSEQMUX_MASK
=
int
MCNTRL_SCANLINE_PENDING_CNTR_BITS__RAW
=
str
MEMCLK_CAPACITANCE__RAW
=
str
VOSPI_PWDN_BITS__RAW
=
str
DQTRI_FIRST
=
int
CONTROL_RBACK_DEPTH
=
int
CAMSYNC_TRIG_DELAY0
=
int
...
...
@@ -2249,6 +2258,7 @@ HISPI_DQS_BIAS__RAW = str
MCONTR_LINTILE_WRITE
=
int
TILE_VSTEP__TYPE
=
str
MCONTR_PHY_STATUS_CNTRL__RAW
=
str
VOSPI_MRST_MS__TYPE
=
str
DLY_LANE0_DQS_WLV_IDELAY
=
long
MCNTRL_SCANLINE_STATUS_CNTRL
=
int
CMDSEQMUX_MASK__TYPE
=
str
...
...
@@ -2321,7 +2331,7 @@ CMPRS_CBIT_RUN_BITS = int
SENS_LENS_AY_MASK
=
int
BUF_IPCLK2X_SENS3__RAW
=
str
MCNTRL_SCANLINE_CHN1_ADDR__RAW
=
str
M
EMBRIDGE_LEN64
=
int
M
ULTICLK_DIV_XCLK__TYPE
=
str
HISPI_MMCM2__TYPE
=
str
SENSOR_NUM_HISTOGRAM__TYPE
=
str
HIST_SAXI_EN
=
int
...
...
@@ -2381,7 +2391,6 @@ CLK_DIV_PHASE__RAW = str
STATUS_MSB_RSHFT__RAW
=
str
SLEW_CMDA__RAW
=
str
HISPI_MMCM0__RAW
=
str
VOSPI_PWDN_BITS
=
int
MCONTR_PHY_16BIT_PATTERNS_TRI
=
int
MCONTR_TOP_STATUS_REG_ADDR__RAW
=
str
DFLT_DQS_TRI_ON_PATTERN
=
int
...
...
@@ -2391,6 +2400,7 @@ DFLT_CHN_EN = int
GPIO_STATUS_REG_ADDR__RAW
=
str
DLY_DQS_ODELAY
=
long
SENSOR_CHN_EN_BIT__RAW
=
str
VOSPI_MRST_MS__RAW
=
str
CMPRS_AFIMUX_RADDR1
=
int
CAMSYNC_TRIG_SRC__TYPE
=
str
SENSI2C_CMD_FIFO_RD
=
int
...
...
@@ -2403,7 +2413,6 @@ SENSI2C_CMD_TAND__RAW = str
WINDOW_HEIGHT__TYPE
=
str
SENSOR_IMAGE_TYPE2__TYPE
=
str
IBUF_LOW_PWR__TYPE
=
str
VOSPI_PWDN
=
int
FFCLK1_IBUF_LOW_PWR__TYPE
=
str
CLK_DIV_PHASE
=
float
VOSPI_MRST
=
int
...
...
@@ -2519,7 +2528,7 @@ VOSPI_HACT_TO_HACT_EOF__TYPE = str
CMPRS_TABLES__RAW
=
str
SENS_GAMMA_MODE_EN__TYPE
=
str
CMDFRAMESEQ_IRQ_BIT__TYPE
=
str
CLK_MASK
=
int
VOSPI_DBG_SRC__TYPE
=
str
MCONTR_BUF4_WR_ADDR__TYPE
=
str
MCNTRL_TILED_CHN2_ADDR
=
int
LWIR_TELEMETRY_AGC_ROI_BOTTOM__RAW
=
str
...
...
@@ -2598,7 +2607,7 @@ MULT_SAXI_MASK__RAW = str
SENSOR12BITS_TMD
=
int
MCONTR_CMPRS_STATUS_BASE__TYPE
=
str
NUM_CYCLES_10__RAW
=
str
SENS_LENS_FAT0_OUT
__TYPE
=
str
CMPRS_TABLES
__TYPE
=
str
VOSPI_SPI_CLK
=
int
DEBUG_SHIFT_DATA__RAW
=
str
SENSOR_16BIT_BIT__TYPE
=
str
...
...
py393/x393_export_c.py
View file @
ae33ff53
...
...
@@ -2126,10 +2126,9 @@ class X393ExportC(object):
def
_enc_sensio_ctrl_vospi
(
self
):
dw
=
[]
dw
.
append
((
"mrst"
,
vrlg
.
VOSPI_MRST
,
1
,
0
,
"RESET signal level to the sensor (0 - low(active), 1 - high (inactive)"
))
dw
.
append
((
"mrst_set"
,
vrlg
.
VOSPI_MRST
+
1
,
1
,
0
,
"When set to 1, RESET is set to the 'rst' field value"
))
dw
.
append
((
"pwdn"
,
vrlg
.
VOSPI_PWDN
,
1
,
0
,
"POWER DOWN signal level to the sensor (0 - low(active), 1 - high (inactive)"
))
dw
.
append
((
"pwdn_set"
,
vrlg
.
VOSPI_PWDN
+
1
,
1
,
0
,
"When set to 1, POWER DOWN is set to the 'pwdn' field value"
))
dw
.
append
((
"reset"
,
vrlg
.
VOSPI_MRST
,
2
,
0
,
"Sensor reset/power down control (0 - NOP, 1 - power down + reset, 2 - no pwdn, reset, 3 - no pwdn, no reset"
))
dw
.
append
((
"rst_seq"
,
vrlg
.
VOSPI_RST_SEQ
,
1
,
0
,
"Initiate simultaneous all sensors reset, generate SOF after pause"
))
dw
.
append
((
"spi_seq"
,
vrlg
.
VOSPI_SPI_SEQ
,
1
,
0
,
"Initiate VOSPI reset, will generate normal SOF if successful"
))
dw
.
append
((
"mclk"
,
vrlg
.
VOSPI_MCLK
,
1
,
0
,
"Enable master clock (25MHz) to sensor"
))
dw
.
append
((
"mclk_set"
,
vrlg
.
VOSPI_MCLK
+
1
,
1
,
0
,
"When set to 1, MCLK enable is set to the 'mclk' field value"
))
dw
.
append
((
"spi_en"
,
vrlg
.
VOSPI_EN
,
2
,
0
,
"SPI reset/enable: 0 - NOP, 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable"
))
...
...
py393/x393_sens_cmprs.py
View file @
ae33ff53
...
...
@@ -763,8 +763,8 @@ class X393SensCmprs(object):
elif
sensorType
==
x393_sensor
.
SENSOR_INTERFACE_VOSPI
:
self
.
x393Sensor
.
set_sensor_io_ctl_lwir
(
num_sensor
=
num_sensor
,
mrst
=
True
,
pwdn
=
False
,
rst
=
2
,
# mrst, no power down
# TODO - use rst_seq instead?
mclk
=
True
,
# None,
spi_en
=
1
,
#None, # 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable
segm_zero
=
True
,
#None,
...
...
@@ -776,13 +776,10 @@ class X393SensCmprs(object):
if
self
.
DRY_MODE
:
self
.
x393Sensor
.
set_sensor_io_ctl_lwir
(
num_sensor
=
num_sensor
,
mrst
=
False
)
rst
=
3
)
# no mrst, no power down
self
.
x393Sensor
.
set_sensor_io_ctl_lwir
(
num_sensor
=
num_sensor
,
spi_en
=
2
)
#None, # 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable
# self.x393Sensor.set_sensor_io_ctl_lwir (
# num_sensor = num_sensor,
# spi_en = 2) #None, # 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable
self
.
x393Sensor
.
set_sensor_io_ctl_lwir
(
num_sensor
=
num_sensor
,
spi_en
=
3
,
#None, # 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable
...
...
@@ -791,7 +788,7 @@ class X393SensCmprs(object):
self
.
sleep_ms
(
0.2
)
# 1 ms. TODO: For real camera turn off all channels simultaneously ***
self
.
x393Sensor
.
set_sensor_io_ctl_lwir
(
num_sensor
=
num_sensor
,
mrst
=
False
,
rst
=
3
,
# no mrst, no power down
spi_en
=
3
,
#None, # 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable
out_en
=
True
)
...
...
py393/x393_sensor.py
View file @
ae33ff53
...
...
@@ -454,8 +454,9 @@ class X393Sensor(object):
return
rslt
def
func_sensor_io_ctl_lwir
(
self
,
mrst
=
None
,
pwdn
=
None
,
rst
=
None
,
rst_seq
=
None
,
spi_seq
=
None
,
mclk
=
None
,
spi_en
=
None
,
# 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable
segm_zero
=
None
,
...
...
@@ -474,8 +475,9 @@ class X393Sensor(object):
dbg_src
=
None
):
"""
Combine sensor I/O control parameters into a control word
@param mrst - True - activate MRST signal (low), False - deactivate MRST (high), None - no change
@param pwdn - True - activate POWER_DOWN signal (low), False - deactivate POWER_DOWN (high), None - no change
@param rst - Sensor reset/power down control (0 - NOP, 1 - power down + reset, 2 - no pwdn, reset, 3 - no pwdn, no reset
@param rst_seq Initiate simultaneous all sensors reset, generate SOF after pause
@param spi_seq Initiate VOSPI reset, will generate normal SOF if successful
@param mclk - True - enable master clock (25MHz) to sensor, False - disable, None - no change
@param spi_en - True - SPI reset/enable: 0 - NOP, 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable, None - no change
@param segm_zero = True - allow receiving segment ID==0 (ITAR invalid), False - disallow, None - no change,
...
...
@@ -500,10 +502,12 @@ class X393Sensor(object):
@return VOSPI sensor i/o control word
"""
rslt
=
0
if
not
mrst
is
None
:
rslt
|=
(
3
,
2
)[
mrst
]
<<
vrlg
.
VOSPI_MRST
if
not
pwdn
is
None
:
rslt
|=
(
3
,
2
)[
pwdn
]
<<
vrlg
.
VOSPI_PWDN
if
not
rst
is
None
:
rslt
|=
(
rst
&
3
)
<<
vrlg
.
VOSPI_MRST
if
rst_seq
:
rslt
|=
1
<<
vrlg
.
VOSPI_RST_SEQ
if
spi_seq
:
rslt
|=
1
<<
vrlg
.
VOSPI_SPI_SEQ
if
not
mclk
is
None
:
rslt
|=
(
2
,
3
)[
mclk
]
<<
vrlg
.
VOSPI_MCLK
if
not
spi_en
is
None
:
...
...
@@ -1068,8 +1072,9 @@ class X393Sensor(object):
def
set_sensor_io_ctl_lwir
(
self
,
num_sensor
,
mrst
=
None
,
pwdn
=
None
,
rst
=
None
,
rst_seq
=
None
,
spi_seq
=
None
,
mclk
=
None
,
spi_en
=
None
,
# 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable
segm_zero
=
None
,
...
...
@@ -1085,11 +1090,11 @@ class X393Sensor(object):
vsync_use
=
None
,
noresync
=
None
,
dbg_src
=
None
):
"""
Combine sensor I/O control parameters into a control word
@param mrst - True - activate MRST signal (low), False - deactivate MRST (high), None - no change
@param pwdn - True - activate POWER_DOWN signal (low), False - deactivate POWER_DOWN (high), None - no change
@param rst - Sensor reset/power down control (0 - NOP, 1 - power down + reset, 2 - no pwdn, reset, 3 - no pwdn, no reset
@param rst_seq Initiate simultaneous all sensors reset, generate SOF after pause
@param spi_seq Initiate VOSPI reset, will generate normal SOF if successful
@param mclk - True - enable master clock (25MHz) to sensor, False - disable, None - no change
@param spi_en - True - SPI reset/enable: 0 - NOP, 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable, None - no change
@param segm_zero = True - allow receiving segment ID==0 (ITAR invalid), False - disallow, None - no change,
...
...
@@ -1116,8 +1121,9 @@ class X393Sensor(object):
if
(
num_sensor
==
all
)
or
(
num_sensor
[
0
]
.
upper
()
==
"A"
):
#all is a built-in function
for
num_sensor
in
range
(
4
):
self
.
set_sensor_io_ctl_lwir
(
num_sensor
,
mrst
=
mrst
,
pwdn
=
pwdn
,
rst
=
rst
,
rst_seq
=
rst_seq
,
spi_seq
=
spi_seq
,
mclk
=
mclk
,
spi_en
=
spi_en
,
segm_zero
=
segm_zero
,
...
...
@@ -1137,8 +1143,9 @@ class X393Sensor(object):
except
:
pass
data
=
self
.
func_sensor_io_ctl_lwir
(
mrst
=
mrst
,
pwdn
=
pwdn
,
rst
=
rst
,
rst_seq
=
rst_seq
,
spi_seq
=
spi_seq
,
mclk
=
mclk
,
spi_en
=
spi_en
,
segm_zero
=
segm_zero
,
...
...
sensor/sens_lepton3.v
View file @
ae33ff53
This diff is collapsed.
Click to expand it.
sensor/sensor_channel.v
View file @
ae33ff53
...
...
@@ -240,8 +240,8 @@ module sensor_channel#(
parameter
VOSPI_MRST
=
0
,
parameter
VOSPI_MRST_BITS
=
2
,
parameter
VOSPI_
PWDN
=
2
,
parameter
VOSPI_
PWDN_BITS
=
2
,
parameter
VOSPI_
RST_SEQ
=
2
,
// initiate reset cycle (master drives all sensors), generate frame start when ready
parameter
VOSPI_
SPI_SEQ
=
3
,
// initilate SPI re-sync (will automatically generate frame syncs when re-synced)
parameter
VOSPI_MCLK
=
4
,
parameter
VOSPI_MCLK_BITS
=
2
,
parameter
VOSPI_EN
=
6
,
...
...
@@ -275,8 +275,10 @@ module sensor_channel#(
parameter
VOSPI_PACKET_TTT
=
20
,
// line number where segment number is provided
parameter
VOSPI_SOF_TO_HACT
=
100
,
// 10, // clock cycles from SOF to HACT (limited to 8 bits)
parameter
VOSPI_HACT_TO_HACT_EOF
=
2
,
// minimal clock cycles from HACT to HACT or to EOF
parameter
VOSPI_MCLK_HALFDIV
=
4
// divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
parameter
VOSPI_MCLK_HALFDIV
=
4
,
// divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
parameter
VOSPI_MRST_MS
=
5
,
// master reset duration in ms
parameter
VOSPI_MRST_AFTER_MS
=
2000
,
// Wait after master reset and generate SOF pulse to advance sequencer
parameter
VOSPI_SPI_TIMEOUT_MS
=
185
// Wait to tymeout SPI when needed to re-sync
`else
//sensor_fifo parameters
parameter
SENSOR_DATA_WIDTH
=
12
,
...
...
@@ -437,6 +439,18 @@ module sensor_channel#(
output
[
1
:
0
]
hist_chn
,
// output[1:0] histogram (sub) channel, valid with request and transfer
output
hist_dvalid
,
// output data valid - active when sending a burst
output
[
31
:
0
]
hist_data
// output[31:0] histogram data
`ifdef
LWIR
// reset synchronization
,
input
ext_rst_in
,
input
ext_rstseq_in
,
output
ext_rst_out
,
output
ext_rstseq_out
`endif
// currently used only for LWIR
,
input
khz
// 1 KHz 50% @mclk
`ifdef
DEBUG_RING
,
output
debug_do
,
// output to the debug ring
input
debug_sl
,
// 0 - idle, (1,0) - shift, (1,1) - load
...
...
@@ -1000,65 +1014,19 @@ module sensor_channel#(
)
;
`elsif
LWIR
sens_lepton3
#(
.
SENSIO_ADDR
(
SENSIO_ADDR
)
,
.
SENSIO_ADDR_MASK
(
SENSIO_ADDR_MASK
)
,
.
SENSIO_CTRL
(
SENSIO_CTRL
)
,
.
SENSIO_STATUS
(
SENSIO_STATUS
)
,
/*
.SENSIO_JTAG (SENSIO_JTAG),
.SENSIO_WIDTH (SENSIO_WIDTH),
.SENSIO_DELAYS (SENSIO_DELAYS),
*/
.
SENSIO_STATUS_REG
(
SENSIO_STATUS_REG
)
,
/*
.SENS_JTAG_PGMEN (SENS_JTAG_PGMEN),
.SENS_JTAG_PROG (SENS_JTAG_PROG),
.SENS_JTAG_TCK (SENS_JTAG_TCK),
.SENS_JTAG_TMS (SENS_JTAG_TMS),
.SENS_JTAG_TDI (SENS_JTAG_TDI),
.SENS_CTRL_MRST (SENS_CTRL_MRST),
.SENS_CTRL_ARST (SENS_CTRL_ARST),
.SENS_CTRL_ARO (SENS_CTRL_ARO),
.SENS_CTRL_RST_MMCM (SENS_CTRL_RST_MMCM),
.SENS_CTRL_EXT_CLK (SENS_CTRL_EXT_CLK),
.SENS_CTRL_LD_DLY (SENS_CTRL_LD_DLY),
.SENS_CTRL_QUADRANTS (SENS_CTRL_QUADRANTS),
.SENS_CTRL_ODD (SENS_CTRL_ODD),
.SENS_CTRL_QUADRANTS_WIDTH (SENS_CTRL_QUADRANTS_WIDTH),
.SENS_CTRL_QUADRANTS_EN (SENS_CTRL_QUADRANTS_EN),
.IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE),
.PXD_DRIVE (PXD_DRIVE),
.PXD_IOSTANDARD (PXD_IOSTANDARD),
.PXD_SLEW (PXD_SLEW),
.SENS_REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE),
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.IPCLK_PHASE (IPCLK_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE),
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.BUF_IPCLK (BUF_IPCLK),
.BUF_IPCLK2X (BUF_IPCLK2X),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1),
.SENS_REF_JITTER2 (SENS_REF_JITTER2),
.SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.STATUS_ALIVE_WIDTH (STATUS_ALIVE_WIDTH),
*/
.
SENSIO_ADDR
(
SENSIO_ADDR
)
,
.
SENSIO_ADDR_MASK
(
SENSIO_ADDR_MASK
)
,
.
SENSIO_CTRL
(
SENSIO_CTRL
)
,
.
SENSIO_STATUS
(
SENSIO_STATUS
)
,
.
SENSIO_STATUS_REG
(
SENSIO_STATUS_REG
)
,
.
VOSPI_DRIVE
(
VOSPI_DRIVE
)
,
.
VOSPI_IBUF_LOW_PWR
(
VOSPI_IBUF_LOW_PWR
)
,
.
VOSPI_IOSTANDARD
(
VOSPI_IOSTANDARD
)
,
.
VOSPI_SLEW
(
VOSPI_SLEW
)
,
.
VOSPI_MRST
(
VOSPI_MRST
)
,
// 0,
.
VOSPI_MRST_BITS
(
VOSPI_MRST_BITS
)
,
// 2,
.
VOSPI_
PWDN
(
VOSPI_PWDN
)
,
//
2,
.
VOSPI_
PWDN_BITS
(
VOSPI_PWDN_BITS
)
,
// 2
,
.
VOSPI_
RST_SEQ
(
VOSPI_RST_SEQ
)
,
//
2,
.
VOSPI_
SPI_SEQ
(
VOSPI_SPI_SEQ
)
,
// 3
,
.
VOSPI_MCLK
(
VOSPI_MCLK
)
,
// 4,
.
VOSPI_MCLK_BITS
(
VOSPI_MCLK_BITS
)
,
// 2,
.
VOSPI_EN
(
VOSPI_EN
)
,
// 6,
...
...
@@ -1092,7 +1060,10 @@ module sensor_channel#(
.
VOSPI_PACKET_TTT
(
VOSPI_PACKET_TTT
)
,
// 20,
.
VOSPI_SOF_TO_HACT
(
VOSPI_SOF_TO_HACT
)
,
// 100,
.
VOSPI_HACT_TO_HACT_EOF
(
VOSPI_HACT_TO_HACT_EOF
)
,
// 2,
.
VOSPI_MCLK_HALFDIV
(
VOSPI_MCLK_HALFDIV
)
// 4
.
VOSPI_MCLK_HALFDIV
(
VOSPI_MCLK_HALFDIV
)
,
// 4
.
VOSPI_MRST_MS
(
VOSPI_MRST_MS
)
,
// 5
.
VOSPI_MRST_AFTER_MS
(
VOSPI_MRST_AFTER_MS
)
,
// 2000
.
VOSPI_SPI_TIMEOUT_MS
(
VOSPI_SPI_TIMEOUT_MS
)
// 185
)
sens_lepton3_i
(
.
mrst
(
mrst
)
,
// input
.
mclk
(
mclk
)
,
// input
...
...
@@ -1126,7 +1097,13 @@ module sensor_channel#(
// not used PADS, keep for compatibility with PCB
.
dp2
(
sns_dp40
[
2
])
,
// inout reserved - used for debug
.
dn2
(
sns_dn40
[
2
])
,
// input reserved
.
dn6
(
sns_dn76
[
6
])
// input reserved
.
dn6
(
sns_dn76
[
6
])
,
// input reserved
// reset synchronization
.
ext_rst_in
(
ext_rst_in
)
,
// input
.
ext_rstseq_in
(
ext_rstseq_in
)
,
// input
.
ext_rst_out
(
ext_rst_out
)
,
// output
.
ext_rstseq_out
(
ext_rstseq_out
)
,
// output
.
khz
(
khz
)
// input 1 KHz 50% duty @ mclk
)
;
// sns_dn76[6] - not used
// sns_dn40[2] - not used
...
...
sensor/sensors393.v
View file @
ae33ff53
...
...
@@ -236,8 +236,8 @@ module sensors393 #(
parameter
VOSPI_SLEW
=
"FAST"
,
// "SLOW",
parameter
VOSPI_MRST
=
0
,
parameter
VOSPI_MRST_BITS
=
2
,
parameter
VOSPI_
PWDN
=
2
,
parameter
VOSPI_
PWDN_BITS
=
2
,
parameter
VOSPI_
RST_SEQ
=
2
,
// initiate reset cycle (master drives all sensors), generate frame start when ready
parameter
VOSPI_
SPI_SEQ
=
3
,
// initilate SPI re-sync (will automatically generate frame syncs when re-synced)
parameter
VOSPI_MCLK
=
4
,
parameter
VOSPI_MCLK_BITS
=
2
,
parameter
VOSPI_EN
=
6
,
...
...
@@ -272,7 +272,9 @@ module sensors393 #(
parameter
VOSPI_SOF_TO_HACT
=
100
,
// 10, // clock cycles from SOF to HACT (limited to 8 bits)
parameter
VOSPI_HACT_TO_HACT_EOF
=
2
,
// minimal clock cycles from HACT to HACT or to EOF
parameter
VOSPI_MCLK_HALFDIV
=
4
,
// divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
parameter
VOSPI_MRST_MS
=
5
,
// master reset duration in ms
parameter
VOSPI_MRST_AFTER_MS
=
2000
,
// Wait after master reset and generate SOF pulse to advance sequencer
parameter
VOSPI_SPI_TIMEOUT_MS
=
185
,
// Wait to tymeout SPI when needed to re-sync
`else
//sensor_fifo parameters
parameter
SENSOR_DATA_WIDTH
=
12
,
...
...
@@ -506,6 +508,7 @@ module sensors393 #(
,
output
[
2
*
4
-
1
:
0
]
dbg_rpage
,
output
[
2
*
4
-
1
:
0
]
dbg_wpage
`endif
,
input
khz
// 1 KHz 50% @mclk
`ifdef
DEBUG_RING
,
output
debug_do
,
// output to the debug ring
...
...
@@ -543,8 +546,13 @@ module sensors393 #(
wire
[
4
*
NUM_FRAME_BITS
-
1
:
0
]
frame_num
=
{
frame_num3
,
frame_num2
,
frame_num1
,
frame_num0
};
wire
[
4
*
NUM_FRAME_BITS
-
1
:
0
]
hist_frame
;
// frame numbers of the histogram outputs
wire
ext_rst_in
;
wire
ext_rstseq_in
;
wire
[
3
:
0
]
ext_rst_out
;
wire
[
3
:
0
]
ext_rstseq_out
;
assign
ext_rst_in
=
|
ext_rst_out
;
assign
ext_rstseq_in
=
|
ext_rstseq_out
;
always
@
(
posedge
mclk
)
begin
cmd_ad
<=
cmd_ad_in
;
...
...
@@ -720,8 +728,8 @@ module sensors393 #(
.
VOSPI_SLEW
(
VOSPI_SLEW
)
,
.
VOSPI_MRST
(
VOSPI_MRST
)
,
// 0,
.
VOSPI_MRST_BITS
(
VOSPI_MRST_BITS
)
,
// 2,
.
VOSPI_
PWDN
(
VOSPI_PWDN
)
,
//
2,
.
VOSPI_
PWDN_BITS
(
VOSPI_PWDN_BITS
)
,
// 2
,
.
VOSPI_
RST_SEQ
(
VOSPI_RST_SEQ
)
,
//
2,
.
VOSPI_
SPI_SEQ
(
VOSPI_SPI_SEQ
)
,
// 3
,
.
VOSPI_MCLK
(
VOSPI_MCLK
)
,
// 4,
.
VOSPI_MCLK_BITS
(
VOSPI_MCLK_BITS
)
,
// 2,
.
VOSPI_EN
(
VOSPI_EN
)
,
// 6,
...
...
@@ -755,8 +763,10 @@ module sensors393 #(
.
VOSPI_PACKET_TTT
(
VOSPI_PACKET_TTT
)
,
// 20,
.
VOSPI_SOF_TO_HACT
(
VOSPI_SOF_TO_HACT
)
,
// 100,
.
VOSPI_HACT_TO_HACT_EOF
(
VOSPI_HACT_TO_HACT_EOF
)
,
// 2,
.
VOSPI_MCLK_HALFDIV
(
VOSPI_MCLK_HALFDIV
)
// 4
.
VOSPI_MCLK_HALFDIV
(
VOSPI_MCLK_HALFDIV
)
,
// 4
.
VOSPI_MRST_MS
(
VOSPI_MRST_MS
)
,
// 5
.
VOSPI_MRST_AFTER_MS
(
VOSPI_MRST_AFTER_MS
)
,
// 2000
.
VOSPI_SPI_TIMEOUT_MS
(
VOSPI_SPI_TIMEOUT_MS
)
// 185
`else
.
SENSOR_DATA_WIDTH
(
SENSOR_DATA_WIDTH
)
,
.
SENSOR_FIFO_2DEPTH
(
SENSOR_FIFO_2DEPTH
)
,
...
...
@@ -855,34 +865,42 @@ module sensors393 #(
.
sns_clkp
(
sns_clkp
[
i
])
,
// inout
.
sns_clkn
(
sns_clkn
[
i
])
,
// inout
`endif
.
sns_scl
(
sns_scl
[
i
])
,
// inout
.
sns_sda
(
sns_sda
[
i
])
,
// inout
.
sns_ctl
(
sns_ctl
[
i
])
,
// inout
.
sns_pg
(
sns_pg
[
i
])
,
// inout
.
sns_scl
(
sns_scl
[
i
])
,
// inout
.
sns_sda
(
sns_sda
[
i
])
,
// inout
.
sns_ctl
(
sns_ctl
[
i
])
,
// inout
.
sns_pg
(
sns_pg
[
i
])
,
// inout
.
mclk
(
mclk
)
,
// input
.
cmd_ad_in
(
cmd_ad
)
,
// input[7:0]
.
cmd_stb_in
(
cmd_stb
)
,
// input
.
status_ad
(
status_ad_chn
[
i
*
8
+:
8
])
,
// output[7:0]
.
status_rq
(
status_rq_chn
[
i
])
,
// output
.
status_start
(
status_start_chn
[
i
])
,
// input
.
trigger_mode
(
trigger_mode
)
,
// input
.
trig_in
(
trig_in
[
i
])
,
// input
.
frame_num_seq
(
frame_num
[
NUM_FRAME_BITS
*
i
+:
NUM_FRAME_BITS
])
,
// input[3:0]
.
dout
(
px_data
[
16
*
i
+:
16
])
,
// output[15:0]