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Commit 043d4849 authored by Andrey Filippov's avatar Andrey Filippov
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working on boson implementaion, fixed old bug in python code

parent 28848f7a
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cocotb/x393_dut.v
View file @ 043d4849
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fpga_version.vh
View file @ 043d4849
......@@ -35,7 +35,9 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h03930139; // Adding pullup on senspgm
parameter FPGA_VERSION = 32'h03930200; // Initial Boson implementation
//BOSON
// parameter FPGA_VERSION = 32'h03930139; // Adding pullup on senspgm
// parameter FPGA_VERSION = 32'h03930138; // Fixing output trigger in free running mode
// parameter FPGA_VERSION = 32'h03930137; // longer reset, sync output
// parameter FPGA_VERSION = 32'h03930136; // Fiixing spi_seq
......
includes/x393_parameters.vh
View file @ 043d4849
......@@ -429,6 +429,8 @@
parameter SENSI2C_TBL_NABRD = 19, // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
parameter SENSI2C_TBL_DLY = 20, // bit delay (number of mclk periods in 1/4 of SCL period)
parameter SENSI2C_TBL_DLY_BITS= 8,
parameter SENSI2C_TBL_EXTIF = 30, // extrenal interface mode (0 - i2c, 1 uart for boson)
parameter SENSI2C_TBL_EXTIF_BITS= 2,
parameter SENSI2C_STATUS = 'h1,
......@@ -500,8 +502,16 @@
//`endif
parameter SENS_CTRL_LD_DLY = 10, // 10
//`ifdef HISPI
parameter SENS_CTRL_GP0= 12, // 14:12
parameter SENS_CTRL_GP1= 15, // 17:15
parameter SENS_CTRL_GP0= 12, // 14:12
parameter SENS_CTRL_GP1= 15, // 17:15
//`elsif BOSON
parameter SENS_CTRL_GP2= 18, // 20:18 00 - float, 01 - low, 10 - high, 11 - trigger
parameter SENS_CTRL_GP3= 21, // 23:21 00 - float, 01 - low, 10 - high, 11 - trigger
parameter SENS_UART_EXTIF_EN = 0, // 1: 0
parameter SENS_UART_XMIT_RST = 2, // 3: 2
parameter SENS_UART_RECV_RST = 4, // 5: 4
parameter SENS_UART_XMIT_START = 6, // 6
parameter SENS_UART_RECV_NEXT = 7, // 7
//`else
parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
parameter SENS_CTRL_QUADRANTS_WIDTH = 7, // 6,
......@@ -589,15 +599,15 @@
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
`endif
parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
`ifdef SIMULATION
`ifdef SIMULATION
parameter VOSPI_MRST_MS = 1, // master reset duration in ms
parameter VOSPI_MRST_AFTER_MS = 5, // Wait after master reset and generate SOF pulse to advance sequencer
parameter VOSPI_SPI_TIMEOUT_MS = 3, // Wait to tymeout SPI when needed to re-sync
`else
`else
parameter VOSPI_MRST_MS = 200, // master reset duration in ms (so even all channels would overlap)
parameter VOSPI_MRST_AFTER_MS = 2000, // Wait after master reset and generate SOF pulse to advance sequencer
parameter VOSPI_SPI_TIMEOUT_MS = 185, // Wait to tymeout SPI when needed to re-sync
`endif
`endif
//`else
//sensor_fifo parameters (for parallel12)
......@@ -658,6 +668,7 @@
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
// parameters for the sensor-synchronous clock PLL
// ALL PARAMETERS HERE SHOULD BE DEFINED (for use in C-generator)
`define TWEAKING_IOSTANDARD
`ifdef HISPI
parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
......@@ -668,12 +679,18 @@
`ifdef TWEAKING_IOSTANDARD
parameter PXD_IOSTANDARD = "LVCMOS25", // with 1.8 actually applied voltage
parameter SENSI2C_IOSTANDARD = "LVCMOS25", // with 1.8 actually applied voltage
// parameter PXD_IOSTANDARD = "LVCMOS18", // with 1.8 actually applied voltage
// parameter SENSI2C_IOSTANDARD = "LVCMOS18", // with 1.8 actually applied voltage
`else
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
`endif
`elsif BOSON
parameter CLKIN_PERIOD_SENSOR = 37.037, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz)
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
`else
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
......@@ -686,17 +703,15 @@
`endif
`ifdef TWEAKING_IOSTANDARD
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DIFF_TERM = "TRUE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
// parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
// parameter HISPI_IOSTANDARD = "PPDS_25", // "LVDS_25", "MINI_LVDS_25", "PPDS_25", "RSDS_25"
parameter HISPI_IOSTANDARD = "LVDS_25", // "LVDS_25", "MINI_LVDS_25", "PPDS_25", "RSDS_25"
`else
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
`endif
`ifdef TWEAKING_IOSTANDARD
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DIFF_TERM = "TRUE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
parameter HISPI_IOSTANDARD = "LVDS_25", // "LVDS_25", "MINI_LVDS_25", "PPDS_25", "RSDS_25"
`else
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
`endif
// parameter BUF_IPCLK = "BUFMR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
......
includes/x393_simulation_parameters.vh
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......@@ -53,8 +53,8 @@
parameter FCLK0_PERIOD = 41.667, // 24MHz
`endif
parameter FCLK1_PERIOD = 0.0,
`ifdef LWIR
// for python (export to C header) all parameters should be defined
//`ifdef LWIR
parameter LWIR_DATA_FILE1 = "/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat",
parameter LWIR_DATA_FILE2 = "/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat",
parameter LWIR_DATA_FILE3 = "/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat",
......@@ -83,7 +83,17 @@
parameter LWIR_GPIO_IN = 4'b0000,
`endif
parameter BOSON_DATA_FILE = "/input_data/pattern_160_120_16.dat",
parameter BOSON_WIDTH = 160, // 640
parameter BOSON_HEIGHT = 120, // 513
parameter BOSON_OUT_BITS = 16, // 16
parameter BOSON_FPS = 60.0, // 60.0
parameter BOSON_HSW = 8, // 8
parameter BOSON_FP_BP = 22, // 102 (FP+BP)
parameter BOSON_FP = 12, // 52
parameter BOSON_VSW = 7, // 87, // in scan lines
//`endif
// parameter SENSOR12BITS_LLINE = 192, // 1664;// line duration in clocks
......@@ -192,9 +202,16 @@
parameter HISTOGRAM_START_PAGE = 20'h12345,
parameter FRAME_WIDTH_ROUND_BITS = 9, // multiple of 512 pixels (32 16-byte bursts) (11 - ful SDRAM page)
`ifdef LWIR
parameter WOI_WIDTH= 160,
parameter WOI_HEIGHT= 122,
`elsif BOSON
parameter WOI_WIDTH= 160, // 640,
parameter WOI_HEIGHT= 120, // 513,
`else
parameter WOI_WIDTH= 256, // 512, // 256, //1040, // 64,
parameter WOI_HEIGHT= 256, // 512, // 256, // 64, // 32,
`endif
parameter QUADRANTS_PXD_HACT_VACT = 6'h01, // 2 bits each: data-0, hact - 1, vact - 2
// 90-degree shifts for data [1:0], hact [3:2] and vact [5:4]
parameter SENSOR_PRIORITY = 1000
input_data/pattern_160_120_14.dat
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//
// autogenerated from /data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.tiff
// autogenerated from ../input_data/pattern_160_120_14.tiff
// GENERATOR = ./x393_tiff_verilog.py
// WIDTH = 160
// HEIGHT = 120
//
160e 3189 3348 3256 3201 31ef 3258 324e 32e9 333d 3365 3427 3690 2714 13d1 0e40 11f6 3293 334b 31f1 31d0 31e8 3210 31bb 3173 31ec 3255 3264 3301 33d1 3568 16c0 0dd6 103b 1092 10fa 10e2 115e 1206 11f6 1123 10d7 0ff5 10e3 2c2c 3435 3288 33c3 3738 252f 0dcf 0dc3 0e3e 0eab 0f5b 104b 1008 0ebb 0cd8 0b4f 0f2c 2a2e 3436 3257 3241 31f4 321c 3376 340f 207a 093e 0c08 0ec9 0f59 0fac 0fb8 102f 0e98 27f6 3774 34b2 33be 3369 3325 3349 33f8 34eb 3591 35d4 35f8 362f 366f 3610 35c1 3555 34b1 3452 3429 33d1 33a5 32a8 326d 321a 322b 356e 1fed 09cc 0d1a 0d85 0d33 0dca 0e00 0e5e 0db4 0ed4 0ec7 0e85 0e54 0dfe 0e97 0e35 0e42 0e84 0f0b 1005 100b 10d7 1104 112c 125b 283b 37fd 34f5 3507 34f9 354c 34ee 3454 343d 3432 3483 34d9 34c3 3505 34fb 3458 3437 33f4 3443 3403 33ad 3308 1ffc 0d7a 073e 09b4 0c84 0c16 0b3e 0be4
31bf 338b 329a 32f6 3291 329b 32c0 3300 3379 33a2 341d 363c 21a5 0fbb 0f56 0fbf 0e6c 2a60 35fe 3208 31a3 31b9 31ff 316b 318f 323c 3218 31c5 3230 347b 2f16 0df8 0ef1 1035 1042 0ffc 1028 1038 10a3 115b 10c8 1022 0f16 0b78 1eeb 37bd 364d 3456 21fd 0d92 0d53 0eac 0f8c 0fc1 0fb5 0f6c 0ea7 0cd1 0b4f 0d9b 2c75 3440 31cc 324a 3242 3280 3288 3287 329b 35d3 223f 09b4 0ea6 1048 10fa 1141 0fee 1185 3265 36a2 34a1 3464 33d9 3394 33a2 345e 34ee 358f 35c7 364a 375e 38d5 3907 385b 365e 352f 3503 3483 3407 33bd 3344 32bd 32eb 3249 3533 24d2 0a3c 0c79 0dc0 0e67 0ee4 0f46 0f25 0f4c 0f85 0e7d 0e98 0d7a 0d89 0e5a 0edb 0f35 0fc2 0fa5 1081 1059 10b6 1124 10d6 1141 15b1 33d9 3766 35e0 3564 356c 34c7 34ac 3484 34a5 34a2 34de 350b 34cc 3505 345c 343c 3417 3411 3416 339f 33c0 353e 317b 2298 0cc7 0946 0be2 0c17 0c41
......
input_data/pattern_160_120_14.dat0 0 → 100644
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input_data/pattern_160_120_16.dat 0 → 100644
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py393/.~lock.boson_commands.ods# 0 → 100644
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,eyesis,eyesis-SH87R,26.12.2020 00:01,file:///home/eyesis/.config/libreoffice/4;
\ No newline at end of file
py393/cargs_test 0 → 100644
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-d TARGET_MODE=1
-f ../system_defines.vh
-f ../includes/x393_parameters.vh ../includes/x393_cur_params_target.vh ../includes/x393_localparams.vh ../includes/x393_simulation_parameters.vh
-l ../includes/x393_cur_params_target_gen.vh
-p PICKLE="../includes/x393_mcntrl.pickle"
-i
py393/generate_flir_boson_cs.py 0 → 100755
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#!/usr/bin/env python3
# encoding: utf-8
'''
# Copyright (C) 2020, Elphel.inc.
# test for import_verilog_parameters.py
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
@author: Andrey Filippov
@copyright: 2020 Elphel, Inc.
@license: GPLv3.0+
@contact: andrey@elphel.coml
@deffield updated: Updated
'''
CRC16_XMODEM_TABLE =[
0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7,
0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef,
0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6,
0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de,
0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485,
0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d,
0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4,
0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc,
0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823,
0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b,
0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12,
0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a,
0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41,
0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49,
0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70,
0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78,
0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f,
0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067,
0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e,
0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256,
0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d,
0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405,
0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c,
0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634,
0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab,
0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3,
0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a,
0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92,
0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9,
0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1,
0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8,
0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0]
def create_with_parity (init_data, # numeric data (may be less than full array
num_bits, # number of bits in item, valid: 1,2,4,8,9,16,18,32,36,64,72
# start_bit, # bit number to start filling from
full_bram): # true if ramb36, false - ramb18
d = num_bits
num_bits8 = 1;
while d > 1:
d >>= 1
num_bits8 <<= 1
bsize = (0x4000,0x8000)[full_bram]
bdata = [0 for i in range(bsize)]
sb = 0
for item in init_data:
for bt in range (num_bits8):
bdata[sb+bt] = (item >> bt) & 1;
sb += num_bits8
data = []
for i in range (len(bdata)//256):
d = 0;
for b in range(255, -1,-1):
d = (d<<1) + bdata[256*i+b]
data.append(d)
data_p = []
num_bits_p = num_bits8 >> 3
sb = 0
print ("num_bits=",num_bits)
print ("num_bits8=",num_bits8)
print ("num_bits_p=",num_bits_p)
if num_bits_p:
pbsize = bsize >> 3
pbdata = [0 for i in range(pbsize)]
for item in init_data:
# print ("item = 0x%x, p = 0x%x"%(item,item >> num_bits8))
for bt in range (num_bits_p):
pbdata[sb+bt] = (item >> (bt+num_bits8)) & 1;
# print ("pbdata[%d] = 0x%x"%(sb+bt, pbdata[sb+bt]))
sb += num_bits_p
for i in range (len(pbdata)//256):
d = 0;
for b in range(255, -1,-1):
d = (d<<1) + pbdata[256*i+b]
data_p.append(d)
# print(bdata)
# print(data)
# print(pbdata)
# print(data_p)
return {'data':data,'data_p':data_p}
def print_params(data,out_file_name):
with open(out_file_name,"w") as out_file:
for i, v in enumerate(data['data']):
if v:
print (", .INIT_%02X (256'h%064X)"%(i,v), file=out_file)
for i, v in enumerate(data['data_p']):
if v:
print (", .INITP_%02X (256'h%064X)"%(i,v), file=out_file)
def print_params(data):
print("Paste following to memory parameters in Verilog source file:")
for i, v in enumerate(data['data']):
if v:
print (", .INIT_%02X (256'h%064X)"%(i,v))
for i, v in enumerate(data['data_p']):
if v:
print (", .INITP_%02X (256'h%064X)"%(i,v))
rslt = create_with_parity (CRC16_XMODEM_TABLE, # init_data, # numeric data (may be less than full array
16, # num_bits, # number of bits in item, valid: 1,2,4,8,9,16,18,32,36,64,72
False) #full_bram): # true if ramb36, false - ramb18
print_params(rslt)#,"test.vh")
# from FLIR docs:
def crc16(data, crc=0x1d0f): #Note the new initial condition is 0x1d0f instead of 0.
# in C:return(USHORT)((crcin << 8) ^ ccitt_16Table[((crcin >> 8)^(data))&255]);
for byte in data:
crc = ((crc << 8) & 0xff00) ^ CRC16_XMODEM_TABLE[((crc >> 8) & 0xff) ^ byte]
return crc & 0xffff
py393/import_verilog_parameters.py
View file @ 043d4849
......@@ -517,7 +517,7 @@ class ImportVerilogParameters(object):
self.conditions.append(not self.conditions.pop())
continue
elif tokens[0] == "elsif":
self.conditions.pop
self.conditions.pop()
self.conditions.append((tokens[1] in self.defines) and ( not False in self.conditions))
continue
else: # enabled, process all directives
......@@ -528,7 +528,7 @@ class ImportVerilogParameters(object):
self.conditions.append(not (tokens[1] in self.defines))
continue
elif tokens[0] == "elsif":
self.conditions.pop
self.conditions.pop()
self.conditions.append(tokens[1] in self.defines)
continue
elif tokens[0] == "else":
......@@ -748,4 +748,4 @@ class ImportVerilogParameters(object):
return self.parameters
def getDefines(self):
return self.defines
\ No newline at end of file
py393/test.vh 0 → 100644
View file @ 043d4849
, .INIT_00 (256'hF1EFE1CED1ADC18CB16BA14A9129810870E760C650A540843063204210210000)
, .INIT_01 (256'hE3DEF3FFC39CD3BDA35AB37B8318933962D672F7429452B52252327302101231)
, .INIT_02 (256'hD58DC5ACF5CFE5EE95098528B54BA56A548544A474C764E61401042034432462)
, .INIT_03 (256'hC7BCD79DE7FEF7DF87389719A77AB75B46B4569566F676D70630161126723653)
, .INIT_04 (256'hB92BA90A99698948F9AFE98ED9EDC9CC382328021861084078A7688658E548C4)
, .INIT_05 (256'hAB1ABB3B8B589B79EB9EFBBFCBDCDBFD2A123A330A501A716A967AB74AD45AF5)
, .INIT_06 (256'h9D498D68BD0BAD2ADDCDCDECFD8FEDAE1C410C603C032C225CC54CE47C876CA6)
, .INIT_07 (256'h8F789F59AF3ABF1BCFFCDFDDEFBEFF9F0E701E512E323E134EF45ED56EB67E97)
, .INIT_08 (256'h606770464025500420E330C200A11080E16FF14EC12DD10CA1EBB1CA81A99188)
, .INIT_09 (256'h725662775214423532D222F3129002B1F35EE37FD31CC33DB3DAA3FB939883B9)
, .INIT_0A (256'h4405542464477466048114A024C334E2C50DD52CE54FF56E858995A8A5CBB5EA)
, .INIT_0B (256'h563446157676665716B0069136F226D3D73CC71DF77EE75F97B88799B7FAA7DB)
, .INIT_0C (256'h28A3388208E118C06827780648655844A9ABB98A89E999C8E92FF90EC96DD94C)
, .INIT_0D (256'h3A922AB31AD00AF17A166A375A544A75BB9AABBB9BD88BF9FB1EEB3FDB5CCB7D)
, .INIT_0E (256'h0CC11CE02C833CA24C455C646C077C268DC99DE8AD8BBDAACD4DDD6CED0FFD2E)
, .INIT_0F (256'h1EF00ED13EB22E935E744E557E366E179FF88FD9BFBAAF9BDF7CCF5DFF3EEF1F)
py393/test_mcntrl.py
View file @ 043d4849
......@@ -580,7 +580,8 @@ USAGE
print(" 'defines' command accepts regular expression as a second parameter to filter the list")
elif (lineList[0] == 'pydev_predefines'):
predefines=""
for k,v in ivp.parsToDict(parameters).items():
# for k,v in ivp.parsToDict(parameters).items():
for k,v in list(sorted(ivp.parsToDict(parameters).items(), key=lambda item:item[0])):
typ=str(type(v))
typ=typ[typ.find("'")+1:typ.rfind("'")]
if "None" in typ:
......@@ -664,4 +665,4 @@ if __name__ == "__main__":
stats.print_stats()
statsfile.close()
sys.exit(0)
sys.exit(main())
\ No newline at end of file
sys.exit(main())
py393/vrlg.py
View file @ 043d4849
This diff is collapsed.
py393/vrlg_mod.py 0 → 100644
View file @ 043d4849
This diff is collapsed.
py393/vrlg_orig.py 0 → 100644
View file @ 043d4849
This diff is collapsed.
py393/x393_export_c.py
View file @ 043d4849
......@@ -324,7 +324,8 @@ class X393ExportC(object):
stypedefs += self.get_typedef32(comment = "Sensor/multiplexer I/O pins status",
data = [self._enc_status_sens_io(),
self._enc_status_sens_io_hispi(),
self._enc_status_sens_io_vospi()],
self._enc_status_sens_io_vospi(),
self._enc_status_sens_io_boson()],
name = "x393_status_sens_io", typ="ro",
frmt_spcs = frmt_spcs)
......@@ -434,7 +435,8 @@ class X393ExportC(object):
stypedefs += self.get_typedef32(comment = "Sensor port I/O control",
data = [self._enc_sensio_ctrl_par12(),
self._enc_sensio_ctrl_hispi(),
self._enc_sensio_ctrl_vospi()],
self._enc_sensio_ctrl_vospi(),
self._enc_sensio_ctrl_boson()],
name = "x393_sensio_ctl", typ="wo",
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "Programming interface for multiplexer FPGA",
......@@ -450,12 +452,14 @@ class X393ExportC(object):
"""
stypedefs += self.get_typedef32(comment = "Sensor i/o timing register 0 (different meanings for different sensor types)",
data = [self._enc_sensio_par12_tim0(),
self._enc_sensio_hispi_tim0()],
self._enc_sensio_hispi_tim0(),
self._enc_sensio_boson_tim0()],
name = "x393_sensio_tim0", typ="rw",
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "Sensor i/o timing register 1 (different meanings for different sensor types)",
data = [self._enc_sensio_par12_tim1(),
self._enc_sensio_hispi_tim1()],
self._enc_sensio_hispi_tim1(),
self._enc_sensio_boson_tim1()],
name = "x393_sensio_tim1", typ="rw",
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "Sensor i/o timing register 2 (different meanings for different sensor types)",
......@@ -1898,6 +1902,25 @@ class X393ExportC(object):
dw.append(("seq_num", 26, 6,0, "Sequence number"))
return dw
def _enc_status_sens_io_boson(self):
dw=[]
dw.append(("ps_out", 0, 8,0, "Sensor MMCM current phase"))
dw.append(("ps_rdy", 8, 1,0, "Sensor MMCM phase ready"))
dw.append(("perr", 9, 1,0, "Parity error in video stream"))
dw.append(("clkfb_pxd_stopped_mmcm",10, 1,0, "Sensor MMCM feedback clock stopped"))
dw.append(("clkin_pxd_stopped_mmcm",11, 1,0, "Sensor MMCM input clock stopped"))
dw.append(("locked_pxd_mmcm", 12, 1,0, "Sensor MMCM locked"))
dw.append(("hact_alive", 13, 1,0, "HACT signal from the sensor (or internal) is toggling"))
dw.append(("recv_prgrs", 14, 1,0, "UART packet receive in progress"))
dw.append(("recv_dav", 15, 1,0, "Byte available in received UART packet"))
dw.append(("recv_data", 16, 8,0, "Received UART data byte"))
dw.append(("senspgmin", 24, 1,0, "senspgm pin state (0 means non-FPGA SFE is present)"))
dw.append(("xmit_busy", 25, 1,0, "UART transmitter busy"))
dw.append(("seq_num", 26, 6,0, "Sequence number"))
return dw
def _enc_status_sens_i2c(self):
dw=[]
dw.append(("i2c_fifo_dout", 0, 8,0, "I2c byte read from the device through FIFO"))
......@@ -1964,6 +1987,7 @@ class X393ExportC(object):
dw.append(("nbwr", vrlg.SENSI2C_TBL_NBWR, vrlg.SENSI2C_TBL_NBWR_BITS,0, "Number of bytes to write (1..10)"))
dw.append(("dly", vrlg.SENSI2C_TBL_DLY, vrlg.SENSI2C_TBL_DLY_BITS, 0, "Bit delay - number of mclk periods in 1/4 of the SCL period"))
dw.append(("tbl_mode", vrlg.SENSI2C_CMD_TAND, 2, 2, "Should be 2 to select table data write mode"))
dw.append(("extif_mode", vrlg.SENSI2C_TBL_EXTIF, vrlg.SENSI2C_TBL_EXTIF_BITS,0, "External interface mode: 0 - I2C (old), 1 - UART (Boson)"))
return dw
def _enc_i2c_tbl_rmode(self):
......@@ -2156,6 +2180,29 @@ class X393ExportC(object):
dw.append(("dbg_src_set", vrlg.VOSPI_DBG_SRC+3, 1, 0, "Enable write to dbg_src"))
return dw
def _enc_sensio_ctrl_boson(self):
dw=[]
dw.append(("mrst", vrlg.SENS_CTRL_MRST, 1, 0, "MRST signal level to the sensor (0 - low(active), 1 - high (inactive)"))
dw.append(("mrst_set", vrlg.SENS_CTRL_MRST + 1, 1, 0, "when set to 1, MRST is set to the 'mrst' field value"))
# dw.append(("arst", vrlg.SENS_CTRL_ARST, 1, 0, "ARST signal to the sensor"))
# dw.append(("arst_set", vrlg.SENS_CTRL_ARST + 1, 1, 0, "ARST set to the 'arst' field"))
# dw.append(("aro", vrlg.SENS_CTRL_ARO, 1, 0, "ARO signal to the sensor"))
# dw.append(("aro_set", vrlg.SENS_CTRL_ARO + 1, 1, 0, "ARO set to the 'aro' field"))
dw.append(("mmcm_rst", vrlg.SENS_CTRL_RST_MMCM, 1, 0, "MMCM (for sensor clock) reset signal"))
dw.append(("mmcm_rst_set", vrlg.SENS_CTRL_RST_MMCM + 1, 1, 0, "MMCM reset set to 'mmcm_rst' field"))
# dw.append(("ign_embed", vrlg.SENS_CTRL_IGNORE_EMBED, 1, 0, "Ignore embedded data (non-image pixel lines"))
# dw.append(("ign_embed_set",vrlg.SENS_CTRL_IGNORE_EMBED + 1,1,0, "Set mode to 'ign_embed' field"))
dw.append(("set_dly", vrlg.SENS_CTRL_LD_DLY, 1, 0, "Set all pre-programmed delays to the sensor port input delays"))
dw.append(("gp0", vrlg.SENS_CTRL_GP0, 2, 0 , "GP0 multi-purpose signal to the sensor: 0 - float, 1 - low, 2 - high, 3 - TRIG"))
dw.append(("gp0_set", vrlg.SENS_CTRL_GP0 + 2, 1, 0, "Set GP0 to 'gp0' value"))
dw.append(("gp1", vrlg.SENS_CTRL_GP1, 2, 0 , "GP1 multi-purpose signal to the sensor: 0 - float, 1 - low, 2 - high, 3 - TRIG"))
dw.append(("gp1_set", vrlg.SENS_CTRL_GP1 + 2, 1, 0, "Set GP1 to 'gp1' value"))
dw.append(("gp2", vrlg.SENS_CTRL_GP2, 2, 0 , "GP2 multi-purpose signal to the sensor: 0 - float, 1 - low, 2 - high, 3 - TRIG"))
dw.append(("gp2_set", vrlg.SENS_CTRL_GP2 + 2, 1, 0, "Set GP2 to 'gp2' value"))
dw.append(("gp3", vrlg.SENS_CTRL_GP3, 2, 0 , "GP3 multi-purpose signal to the sensor: 0 - float, 1 - low, 2 - high, 3 - TRIG"))
dw.append(("gp3_set", vrlg.SENS_CTRL_GP3 + 2, 1, 0, "Set GP3 to 'gp3' value"))
return dw
def _enc_sensio_jtag(self):
dw=[]
dw.append(("tdi", vrlg.SENS_JTAG_TDI, 1, 0, "JTAG TDI level"))
......@@ -2266,6 +2313,26 @@ class X393ExportC(object):
dw.append(("phase_h", 0, 8, 0, "MMCM phase"))
return dw
def _enc_sensio_boson_tim0(self):
dw=[]
dw.append(("uart_txd", 0, 8, 0, "UART transmit data byte"))
return dw
def _enc_sensio_boson_tim1(self):
dw=[]
dw.append(("uart_extif_en", vrlg.SENS_UART_EXTIF_EN, 1, 0, "UART: enable sequencer commands"))
dw.append(("uart_extif_en_set", vrlg.SENS_UART_EXTIF_EN+1, 1, 0, "set 'uart_extif_en' field"))
dw.append(("uart_xmit_rst", vrlg.SENS_UART_XMIT_RST, 1, 0, "UART: reset software packet transmission"))
dw.append(("uart_xmit_rst_set", vrlg.SENS_UART_XMIT_RST+1, 1, 0, "set 'uart_xmit_rst' field"))
dw.append(("uart_recv_rst", vrlg.SENS_UART_RECV_RST, 1, 0, "UART: reset software packet receiving"))
dw.append(("uart_recv_rst_set", vrlg.SENS_UART_RECV_RST+1, 1, 0, "set 'uart_recv_rst' field"))
dw.append(("uart_xmit_start", vrlg.SENS_UART_XMIT_START, 1, 0, "UART: start transmiting prepared packet"))
dw.append(("uart_recv_next", vrlg.SENS_UART_RECV_NEXT, 1, 0, "UART: advance receive FIFO to next byte"))
return dw
def _enc_sensio_width(self):
dw=[]
dw.append(("sensor_width", 0, 16, 0, "Sensor frame width (0 - use line sync signals from the sensor)"))
......@@ -2784,4 +2851,4 @@ class X393ExportC(object):
\ No newline at end of file
py393/x393_sens_cmprs.py
View file @ 043d4849
......@@ -131,13 +131,17 @@ FRAME_START_ADDRESS_INC = 0x80000
# for now - single sensor type per interface
SENSOR_INTERFACES={x393_sensor.SENSOR_INTERFACE_PARALLEL: {"mv":2800, "freq":24.0, "iface":"2V5_LVDS"},
x393_sensor.SENSOR_INTERFACE_HISPI: {"mv":1820, "freq":24.444, "iface":"1V8_LVDS"},
x393_sensor.SENSOR_INTERFACE_VOSPI: {"mv":2800, "freq":24.0, "iface":"2V5_LVDS"}}
x393_sensor.SENSOR_INTERFACE_VOSPI: {"mv":2800, "freq":24.0, "iface":"2V5_LVDS"},
x393_sensor.SENSOR_INTERFACE_BOSON: {"mv":1820, "freq":24.444, "iface":"1V8_LVDS"}} # see if freq is not needed
# x393_sensor.SENSOR_INTERFACE_HISPI: {"mv":2500, "freq":24.444, "iface":"1V8_LVDS"}}
#slave is 7 bit
#BOSON: add parameters for uart instead of the i2C
#Use 'hardware' dimensions here, simulation ones will be overwritten
SENSOR_DEFAULTS= { x393_sensor.SENSOR_INTERFACE_PARALLEL: {"width":2592, "height":1944, "top":0, "left":0, "slave":0x48, "i2c_delay":100, "bayer":3},
x393_sensor.SENSOR_INTERFACE_HISPI: {"width":4384, "height":3288, "top":0, "left":0, "slave":0x10, "i2c_delay":100, "bayer":2},
# x393_sensor.SENSOR_INTERFACE_VOSPI: {"width":160, "height":120, "top":0, "left":0, "slave":0x2a, "i2c_delay":100, "bayer":2}}
x393_sensor.SENSOR_INTERFACE_VOSPI: {"width":160, "height":122, "top":0, "left":0, "slave":0x2a, "i2c_delay":100, "bayer":2}}
x393_sensor.SENSOR_INTERFACE_VOSPI: {"width":160, "height":122, "top":0, "left":0, "slave":0x2a, "i2c_delay":100, "bayer":2},
x393_sensor.SENSOR_INTERFACE_BOSON: {"width":640, "height":513, "top":0, "left":0, "slave":0x2a, "i2c_delay":100, "bayer":2}}
#SENSOR_DEFAULTS_SIMULATION= {x393_sensor.SENSOR_INTERFACE_PARALLEL: {"width":2592, "height":1944, "top":0, "left":0, "slave":0x48, "i2c_delay":100, "bayer":3},
# x393_sensor.SENSOR_INTERFACE_HISPI: {"width":4384, "height":3288, "top":0, "left":0, "slave":0x10, "i2c_delay":100, "bayer":2}}
......@@ -187,8 +191,10 @@ class X393SensCmprs(object):
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_PARALLEL]["height"]= vrlg.WOI_HEIGHT + 0
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["width"]= vrlg.WOI_WIDTH + 0 #4
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["height"]= vrlg.WOI_HEIGHT + 0
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_VOSPI]["width"]= vrlg.WOI_WIDTH + 0 #4
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_VOSPI]["height"]= vrlg.WOI_HEIGHT + 0
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_BOSON]["width"]= vrlg.WOI_WIDTH + 0 #4
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_BOSON]["height"]= vrlg.WOI_HEIGHT + 0
print ("Using simulation size sensor defaults ",SENSOR_DEFAULTS)
except:
......@@ -792,6 +798,37 @@ class X393SensCmprs(object):
spi_en = 3, #None, # 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable
out_en = True)
elif sensorType == x393_sensor.SENSOR_INTERFACE_BOSON:
self.x393Sensor.set_sensor_io_ctl_boson (
num_sensor = num_sensor,
mrst = True,
mmcm_rst = True, #reset mmcm
set_delays = False)
self.x393Sensor.func_sensor_uart_ctl_boson (
uart_extif_en = False,
uart_xmit_rst = True,
uart_recv_rst = True,
uart_xmit_start = False,
uart_recv_next = False)
self.x393Sensor.set_sensor_io_ctl_boson (
num_sensor = num_sensor,
mrst = False,
mmcm_rst = True, #reset mmcm
set_delays = False)
self.x393Sensor.set_sensor_io_ctl_boson (
num_sensor = num_sensor,
mrst = False,
mmcm_rst = False,
set_delays = False)
self.x393Sensor.func_sensor_uart_ctl_boson (
uart_extif_en = True,
uart_xmit_rst = False,
uart_recv_rst = False,
uart_xmit_start = False,
uart_recv_next = False)
if exit_step == 17: return False
"""
......@@ -1844,7 +1881,8 @@ class X393SensCmprs(object):
num_bytes_rd = 2,
bit_delay = i2c_delay,
verbose = verbose)
elif sensorType == x393_sensor.SENSOR_INTERFACE_BOSON:
pass
else:
raise ("Unknown sensor type: %s"%(sensorType))
......
py393/x393_sensor.py
View file @ 043d4849
This diff is collapsed.
py393/x393_tiff_verilog.py
View file @ 043d4849
......@@ -50,6 +50,7 @@ try:
outname = sys.argv[3]
except IndexError:
outname = fname.replace(".tiff",".dat")
print("Generating %s frm %s"%(outname, fname))
tif = Image.open(fname)
......@@ -59,6 +60,9 @@ f="%%0%dx"%(digits)
with open(outname,"w") as outfile:
print("//",file=outfile)
print("// autogenerated from %s"%(fname),file=outfile)
print("// GENERATOR = %s"%(sys.argv[0]),file=outfile)
print("// WIDTH = %d"%(image_array.shape[1]),file=outfile)
print("// HEIGHT = %d"%(image_array.shape[0]),file=outfile)
print("//",file=outfile)
for image_line in image_array:
for pixel in image_line:
......
sensor/boson_uart.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b> boson_uart
* @file boson_uart.v
* @date 2020-12-12
* @author eyesis
*
* @brief 921.6K8N1 UART to communicate with Boson
*
* @copyright Copyright (c) 2020 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* boson_uart.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* boson_uart.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
`include "system_defines.vh" // just for debugging histograms
module boson_uart #(
// parameter BOSON_BAUD = 921600,
parameter CLK_DIV = 217,
parameter RX_DEBOUNCE = 60
)(
input mrst, // @posedge mclk, sync reset
input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
output txd, // serial data out
input rxd, // serial data in
input [7:0] tx_byte, // transmit byte in
input tx_stb, // transmit strobe for byte in
output tx_busy, // transmit in progress
output tx_rdy, // ready to accept tx_stb
output [7:0] rx_byte, // received byte
output rx_stb // received data strobe (valid 1 cycle before and later for 1 bit)
);
localparam CLK_DIV_BITS = clogb2(CLK_DIV); // + 1);
localparam RX_DEBOUNCE_BITS = clogb2(RX_DEBOUNCE + 1);
reg [CLK_DIV_BITS-1:0] clk_div_cntr_rx;
reg [CLK_DIV_BITS-1:0] clk_div_cntr_tx;
reg [RX_DEBOUNCE_BITS-1:0] debounce_cntr;
reg rxd_r;
reg [9:0] rx_sr; // receive channel shift register, including start_stop
reg [9:0] tx_sr; // transmit channel shift register, including start_stop
reg [7:0] tx_r; // transmit channel data input register
reg [3:0] rx_bcntr; // read channel bit counter;
reg [3:0] tx_bcntr; // read channel bit counter;
reg rx_err;
reg rx_bit;
reg [1:0] tx_bit;
reg [1:0] rx_stb_r;
reg tx_busy_r;
reg tx_rq; // request to transmit
reg mrst_d;
reg tx_start;
reg tx_continue;
wire debounced;
wire rx_bitw;
wire tx_bitw;
wire mark;
wire rx_errw;
wire start_bit_rx;
wire stop_bit_rx;
wire stop_bit_tx;
wire tx_startw; // start next 10-bit transmission
wire tx_continuew;
assign debounced = (debounce_cntr == 0);
assign rx_bitw = (clk_div_cntr_rx == 0);
assign tx_bitw = (clk_div_cntr_tx == 0);
assign mark = &rx_sr; // all ones
assign start_bit_rx = (rx_bcntr == 0);
assign stop_bit_rx = (rx_bcntr == 9);
assign stop_bit_tx = (tx_bcntr == 9);
assign rx_errw = rxd_r ? start_bit_rx : stop_bit_rx; // 1 at start, 0 at stop
assign tx_startw = tx_bit[0] && stop_bit_tx && tx_rq;
assign tx_continuew = tx_bit[0] && !stop_bit_tx;
assign rx_byte = rx_sr[8:1];
assign rx_stb = rx_stb_r[1];
assign tx_rdy = tx_rq;
assign tx_busy = tx_busy_r || !tx_rq;
assign txd = tx_sr[0];
always @(posedge mclk) begin
if (mrst) rxd_r <= rxd;
else if (debounced) rxd_r <= rxd;
if (rxd_r == rxd) debounce_cntr <= RX_DEBOUNCE;
else if (!debounced) debounce_cntr <= debounce_cntr - 1;
if (mrst) clk_div_cntr_rx <= CLK_DIV - 2;
else if (rx_bit) clk_div_cntr_rx <= CLK_DIV - 2;
else if (debounced) clk_div_cntr_rx <= (CLK_DIV >> 1); // half interval
else clk_div_cntr_rx <= clk_div_cntr_rx - 1;
rx_bit <= rx_bitw;
if (mrst) rx_sr <= 10'h3ff; // inactive "1"
else if (rx_bit) rx_sr <= {rxd_r,rx_sr[9:1]}; // little endian as RX232
if (mark || rx_err || (rx_bit && stop_bit_rx)) rx_bcntr <= 0;
else if (rx_bit) rx_bcntr <= rx_bcntr + 1;
if (mark) rx_err <= 0;
else if (rx_bit && rx_errw) rx_err <= 1;
rx_stb_r <= {rx_stb_r[0], stop_bit_rx & rx_bit};
end
// Transmit path
always @(posedge mclk) begin
if (tx_stb) tx_r <= tx_byte;
mrst_d <= mrst;
tx_bit <= {tx_bit[0],tx_bitw};
if (mrst) clk_div_cntr_tx <= CLK_DIV - 3;
else if (tx_bit[1]) clk_div_cntr_tx <= CLK_DIV - 3;
else clk_div_cntr_tx <= clk_div_cntr_tx - 1;
if (mrst) tx_sr <= 10'h3ff;
else if (tx_start) tx_sr <= {1'b1, tx_r, 1'b0};
else if (tx_bit[1]) tx_sr <= {1'b1, tx_sr[9:1]};
if (mrst) tx_busy_r <= 0;
else if (tx_start) tx_busy_r <= 1;
else if (tx_bit[1] && stop_bit_tx) tx_busy_r <= 0;
if (mrst) tx_rq <= 0;
else if (mrst_d) tx_rq <= 1; // single-cycle turn-on after mrst
else if (tx_stb) tx_rq <= 0;
else if (tx_start) tx_rq <= 1;
if (mrst) tx_bcntr <= 0;
else if (tx_start) tx_bcntr <= 0;
else if (tx_continue) tx_bcntr <= tx_bcntr + 1;
tx_start <= tx_startw;
tx_continue <= tx_continuew;
end
function integer clogb2;
input [31:0] value;
begin
value = value - 1;
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin // SuppressThisWarning VEditor - VDT bug
value = value >> 1;
end
end
endfunction
endmodule
sensor/crc16_xmodem.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b> crc16_xmodem
* @file crc16_xmodem.v
* @date 2020-12-13
* @author eyesis
*
* @brief Calculate and insert/verify crc16 (both receive and transmit)
*
* @copyright Copyright (c) 2020 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* crc16_xmodem.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* crc16_xmodem.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module crc16_xmodem#(
parameter INITIAL_CRC16 = 16'h1d0f
)(
input mrst, // @posedge mclk, sync reset
input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
// Transmit channel
input tx_start, // initialize crc16
input [7:0] txd_in, // transmit payload
input tx_in_stb, // strobe for the txd_in
input tx_over, // payload data ended, should output crc16 (should be after the last tx_in_stb)
input tx_rdy, // stuffer is ready to accept next byte
output tx_in_rdy, // module ready to accept next byte
output [7:0] txd_out, // delayed txt_in, followed by the CRC16
output tx_out_stb, // load txd_out to stuffer
output tx_busy // does not include destuffer and uart
// implementing only transmit CRC16 as response is only needed for non-sequencer operation
/*
// receive channel
,input rx_start,
input [7:0] rxd_in, // byte input from stuffer
input rx_in_stb, // next byte from destuffer in rxd_in
input rx_over, // no more data from destuffer (last 2 bytes were crc16: msb, lsb)
output [7:0] rxd_out, // received chn, payload and crc data
output rx_out_stb, // received data output strobe
output rx_busy, // received channel busy
output rx_crc_good // valid with !rx_busy
*/
);
reg [7:0] txd_in_r;
reg tx_busy_r;
reg tx_stb_crc_m;
reg tx_stb_crc_l;
reg tx_stb_crc_l2; // next cycle after tx_stb_crc_l, same as last tx_out_stb
reg [15:0] tx_crc16_r;
reg [3:0] tx_crc16_s;
reg [7:0] crc16_addr;
reg [7:0] txd_out_r;
reg tx_pre_crc;
reg [1:0] tx_crc_out;
reg [1:0] tx_crc_out_d;
reg tx_in_rdy_r;
reg tx_dav_r;
reg tx_out_stb_r;
reg tx_out_stb_r2;
reg tx_gen_bsy;
wire tx_crc16_next; // calculate next CRC16
wire [15:0] crc16_table; // valid at tx_crc16_s[3]
wire [15:0] tx_crc16_w;
assign tx_crc16_next =tx_crc16_s[3];
assign tx_crc16_w = {tx_crc16_r[7:0] ^ crc16_table[15:8], crc16_table[7:0]};
assign tx_busy = tx_busy_r;
assign txd_out = txd_out_r;
assign tx_in_rdy = tx_in_rdy_r;
assign tx_out_stb = tx_out_stb_r;
always @(posedge mclk) begin
if (mrst) tx_in_rdy_r <= 0;
else if (tx_start || tx_crc16_s[0]) tx_in_rdy_r <= 1; // tx_crc16_next
else if (tx_in_stb || tx_over) tx_in_rdy_r <= 0;
if (mrst) tx_gen_bsy <= 0;
else if (tx_in_stb) tx_gen_bsy <= 1;
else if (tx_out_stb_r) tx_gen_bsy <= 0;
if (mrst) tx_pre_crc <= 0;
else if (tx_start) tx_pre_crc <= 0;
else if (tx_over) tx_pre_crc <= 1;
if (mrst) tx_crc_out[0] <= 0;
else if (tx_start) tx_crc_out[0] <= 0;
else if (tx_pre_crc && !tx_gen_bsy) tx_crc_out[0] <= 1;
if (mrst) tx_crc_out[1] <= 0;
else if (tx_start) tx_crc_out[1] <= 0;
else if (tx_crc_out[0] && tx_out_stb_r) tx_crc_out <= 2'h1;
tx_crc_out_d <= tx_crc_out;
if (mrst) tx_dav_r <= 0;
else if (tx_out_stb_r) tx_dav_r <= 0;
else if (tx_crc16_next || tx_stb_crc_m || tx_stb_crc_l) tx_dav_r <= 1;
tx_out_stb_r <= !tx_out_stb_r && !tx_out_stb_r2 && tx_dav_r && tx_rdy;
tx_out_stb_r2 <= tx_out_stb_r;
tx_stb_crc_m <= tx_crc_out[0] && !tx_crc_out[1] && !tx_crc_out_d[0]; // tx_crc_out[0] just 0->1
tx_stb_crc_l <= tx_crc_out[1] && !tx_crc_out_d[1]; // tx_crc_out[1] just 0->1
if (tx_crc16_next) txd_out_r <= txd_in_r;
else if (tx_stb_crc_m) txd_out_r <= tx_crc16_r[15:8];
else if (tx_stb_crc_l) txd_out_r <= tx_crc16_r[ 7:0];
if (mrst) tx_crc16_s <= 0;
else tx_crc16_s <= {tx_crc16_s[2:0],tx_in_stb};
if (tx_crc16_s[0]) crc16_addr <= tx_crc16_r[15:8] ^ txd_in_r;
if (tx_in_stb) txd_in_r <= txd_in;
tx_stb_crc_l2 <= tx_stb_crc_l;
if (mrst) tx_busy_r <= 0;
else if (tx_start) tx_busy_r <= 1;
else if (tx_stb_crc_l2) tx_busy_r <= 0;
if (tx_start) tx_crc16_r <= INITIAL_CRC16;
else if (tx_crc16_next) tx_crc16_r <= tx_crc16_w;
end
ram18_var_w_var_r #(
.REGISTERS (1),
.LOG2WIDTH_WR (4),
.LOG2WIDTH_RD (4),
.DUMMY (0)
`ifdef PRELOAD_BRAMS
, .INIT_00 (256'hF1EFE1CED1ADC18CB16BA14A9129810870E760C650A540843063204210210000)
, .INIT_01 (256'hE3DEF3FFC39CD3BDA35AB37B8318933962D672F7429452B52252327302101231)
, .INIT_02 (256'hD58DC5ACF5CFE5EE95098528B54BA56A548544A474C764E61401042034432462)
, .INIT_03 (256'hC7BCD79DE7FEF7DF87389719A77AB75B46B4569566F676D70630161126723653)
, .INIT_04 (256'hB92BA90A99698948F9AFE98ED9EDC9CC382328021861084078A7688658E548C4)
, .INIT_05 (256'hAB1ABB3B8B589B79EB9EFBBFCBDCDBFD2A123A330A501A716A967AB74AD45AF5)
, .INIT_06 (256'h9D498D68BD0BAD2ADDCDCDECFD8FEDAE1C410C603C032C225CC54CE47C876CA6)
, .INIT_07 (256'h8F789F59AF3ABF1BCFFCDFDDEFBEFF9F0E701E512E323E134EF45ED56EB67E97)
, .INIT_08 (256'h606770464025500420E330C200A11080E16FF14EC12DD10CA1EBB1CA81A99188)
, .INIT_09 (256'h725662775214423532D222F3129002B1F35EE37FD31CC33DB3DAA3FB939883B9)
, .INIT_0A (256'h4405542464477466048114A024C334E2C50DD52CE54FF56E858995A8A5CBB5EA)
, .INIT_0B (256'h563446157676665716B0069136F226D3D73CC71DF77EE75F97B88799B7FAA7DB)
, .INIT_0C (256'h28A3388208E118C06827780648655844A9ABB98A89E999C8E92FF90EC96DD94C)
, .INIT_0D (256'h3A922AB31AD00AF17A166A375A544A75BB9AABBB9BD88BF9FB1EEB3FDB5CCB7D)
, .INIT_0E (256'h0CC11CE02C833CA24C455C646C077C268DC99DE8AD8BBDAACD4DDD6CED0FFD2E)
, .INIT_0F (256'h1EF00ED13EB22E935E744E557E366E179FF88FD9BFBAAF9BDF7CCF5DFF3EEF1F)
`endif
) i_crc16 (
.rclk (mclk), // input
.raddr ({2'b0, crc16_addr[7:0]}), // input[8:0]
.ren (tx_crc16_s[1]), // input
.regen (tx_crc16_s[2]), // input
.data_out (crc16_table[15:0]), // output[15:0]
.wclk (1'b0), // input
.waddr (10'b0), // input[8:0]
.we (1'b0), // input
.web (4'b0), // input[3:0]
.data_in (16'b0) // input[15:0]
);
endmodule
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sensor/sens_103993_clock.v 0 → 100644
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sensor/sens_103993_deser10.v 0 → 100644
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/*!
* <b>Module:</b> sens_103993_deser10
* @file sens_103993_deser10.v
* @date 2020-12-16
* @author eyesis
*
* @brief 10:1 deserializer for 103993 (270MHz->27MHz)
*
* @copyright Copyright (c) 2020 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* sens_103993_deser10.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sens_103993_deser10.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module sens_103993_deser10(
input pclk10,
input pclk,
input din,
output [9:0] dout
);
reg [9:0] sr;
reg [9:0] dout_r;
assign dout = dout_r;
always @(posedge pclk10) begin
sr <= {sr[8:0], din};
end
always @(posedge pclk) begin
dout_r <= sr;
end
endmodule
sensor/sens_103993_din.v 0 → 100644
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/*!
* <b>Module:</b>sens_103993_din
* @file sens_hispi_din.v
* @date 2020-12-16
* @author Andrey Filippov
*
* @brief Input differential receivers for HiSPi lanes
*
* @copyright Copyright (c) 2015 Elphel, Inc .
*
* <b>License:</b>
*
* sens_103993_din.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sens_103993_din.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module sens_103993_din #(
parameter IODELAY_GRP = "IODELAY_SENSOR", // may need different for different channels?
parameter integer IDELAY_VALUE = 0,
parameter real REFCLK_FREQUENCY = 200.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter NUMLANES = 3,
parameter LVDS_CAPACITANCE = "DONT_CARE",
parameter LVDS_DIFF_TERM = "TRUE",
parameter LVDS_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter LVDS_DQS_BIAS = "TRUE",
parameter LVDS_IBUF_DELAY_VALUE = "0",
parameter LVDS_IBUF_LOW_PWR = "TRUE",
parameter LVDS_IFD_DELAY_VALUE = "AUTO",
parameter LVDS_IOSTANDARD = "DIFF_SSTL18_I" //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
)(
input mclk,
input mrst,
input [NUMLANES * 8-1:0] dly_data, // delay value (3 LSB - fine delay) - @posedge mclk
input [NUMLANES-1:0] set_idelay, // mclk synchronous load idelay value
input ld_idelay, // mclk synchronous set idealy value
input pclk, // 27 MHz
// input ipclk, // 165 MHz
input ipclk2x, // 330 MHz
// input irst, // reset @posedge iclk
input [NUMLANES-1:0] din_p,
input [NUMLANES-1:0] din_n,
output [NUMLANES * 10-1:0] dout
);
wire [NUMLANES-1:0] din;
wire [NUMLANES-1:0] din_dly;
generate
genvar i;
for (i=0; i < NUMLANES; i=i+1) begin: din_block
if (LVDS_UNTUNED_SPLIT == "TRUE") begin
ibufds_ibufgds_50 #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (din[i]), // output
.I (din_p[i]), // input
.IB (din_n[i]) // input
);
end else begin
ibufds_ibufgds #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (din[i]), // output
.I (din_p[i]), // input
.IB (din_n[i]) // input
);
end
idelay_nofine # (
.IODELAY_GRP (IODELAY_GRP),
.DELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE)
) pxd_dly_i(
.clk (mclk),
.rst (mrst),
.set (set_idelay[i]),
.ld (ld_idelay),
.delay (dly_data[3 + 8*i +: 5]),
.data_in (din[i]),
.data_out (din_dly[i])
);
sens_103993_deser10 sens_103993_deser10_i (
.pclk10 (ipclk2x), // input
.pclk (pclk), // input
.din (din_dly[i]), // input
.dout (dout[10*i +: 10]) // output[9:0]
);
end
endgenerate
endmodule
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sensor/sens_parallel12.v
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......@@ -68,12 +68,12 @@ module sens_parallel12 #(
parameter LINE_WIDTH_BITS = 16,
parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
parameter integer IDELAY_VALUE = 0,
parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_IOSTANDARD = "DEFAULT",
parameter PXD_SLEW = "SLOW",
parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
parameter integer IDELAY_VALUE = 0,
parameter real SENS_REFCLK_FREQUENCY = 300.0,
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
......
sensor/sensor_channel.v
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sensor/sensor_i2c.v
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sensor/sensor_i2c_io.v
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sensor/sensor_i2c_prot.v
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sensor/sensors393.v
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system_defines.vh
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util_modules/fifo_sameclock_control.v
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......@@ -4,7 +4,7 @@
* @date 2016-01-20
* @author Andrey Filippov
*
* @brief BRAM-based fifo control, uses BARM output registers
* @brief BRAM-based fifo control, uses BRAM output registers
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
......
util_modules/status_read.v
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x393.v
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x393_global.tcl
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x393_placement.tcl
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x393_timing.tcl
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