simulating image generation and debugging implementation

        self.dut =       dut

        #Open file to use as system memory

        try:

            self._memfile=open(mempath, 'r+') #keep old file if it exists already

            self._memfile=open(mempath, 'rb+') #keep old file if it exists already

        except:    

            self._memfile=open(mempath, 'w+') #create a new file if it does not exist

            self._memfile=open(mempath, 'wb+') #create a new file if it does not exist

            self.dut._log.info ("Created a new 'memory' file %s"%(mempath)) #

        #Extend to full size

        self._memfile.seek(self.memhigh-1)

            pass

        if not readOK:

            self._memfile.seek(self.memhigh-1)

            self._memfile.write(chr(0))

            self._memfile.write(b'\x00')#chr(0))

            self._memfile.flush()

            self.dut._log.info("Wrote to 0x%08x to extend file to full size"%(self.memhigh-1)) #

        except:

            self.logErrorTerminate("Socket seems to have died :-(")

        self.dut._log.debug("1.Received from socket: %s"%(line))

        yield self.executeCommand(line)

        yield self.executeCommand(line) ##

        self.dut._log.debug("3.Received from socket: %s"%(line))

    @cocotb.coroutine

  // Simulation signals

    wire        CLK;

    reg         RST;

    wire        RST_SIM_AXI; // was RST 

//    reg        RST_CLEAN  = 1;

/*

    wire [NUM_INTERRUPTS-1:0] IRQ_R =   {x393_i.sata_irq, x393_i.cmprs_irq[3:0], x393_i.frseq_irq[3:0]}; 

*/

    assign reset_out = RST || x393_i.arst;

    assign RST_SIM_AXI = reset_out; // was RST before 2021 

    x393 #(

// TODO: Are these parameters needed? They are included in x393 from the save x393_parameters.vh    

        .MCONTR_WR_MASK                    (MCONTR_WR_MASK),

        .VALID_DELAY   (4.0)

    ) simul_axi_master_rdaddr_i (

        .clk        (maxigp0aclk),//CLK),// input

        .reset      (RST),             // input

        .reset      (RST_SIM_AXI),             // input

        .arid_in    (dutm0_arid_w[11:0]),   // input[11:0] 

        .araddr_in  (dutm0_araddr_w[31:0]), // input[31:0] 

        .arlen_in   (dutm0_arlen_w[3:0]),   // input[3:0] 

        .VALID_DELAY   (4.0)

    ) simul_axi_master_wraddr_i (

        .clk        (maxigp0aclk),     // input

        .reset      (RST),             // input

        .reset      (RST_SIM_AXI),             // input

        .awid_in    (dutm0_awid_w[11:0]),   // input[11:0] 

        .awaddr_in  (dutm0_awaddr_w[31:0]), // input[31:0] 

        .awlen_in   (dutm0_awlen_w[3:0]),   // input[3:0] 

        .VALID_DELAY   (3.6)

    ) simul_axi_master_wdata_i (

        .clk        (maxigp0aclk),     // input

        .reset      (RST),             // input

        .reset      (RST_SIM_AXI),             // input

        .wid_in     (dutm0_wid_w[11:0]),    // input[11:0] 

        .wdata_in   (dutm0_wdata_w[31:0]),  // input[31:0] 

        .wstrb_in   (dutm0_wstb_w[3:0]),   // input[3:0] 

// Until then  dutm0_rready and dutm0_bready are outputs, not inputs

    simul_axi_slow_ready simul_axi_slow_ready_i (

        .clk        (maxigp0aclk),     // input

        .reset      (RST),             // input

        .reset      (RST_SIM_AXI),             // input

        .delay      (dutm0_xtra_rdlag),          // input[3:0] 

        .valid      (maxigp0rvalid),   // input

        .ready      (maxigp0rready)    // output

    simul_axi_slow_ready simul_axi_slow_ready_write_resp_i(

        .clk        (maxigp0aclk),     // input

        .reset      (RST),             // input

        .reset      (RST_SIM_AXI),             // input

        .delay      (dutm0_xtra_blag),           // input[3:0]

        .valid      (maxigp0bvalid),   // input

        .ready      (maxigp0bready)    // output

        .ADDRESS_WIDTH (SIMUL_AXI_READ_WIDTH)

    ) simul_axi_read_i (

        .clk        (maxigp0aclk),                                // input

        .reset      (RST),                                        // input

        .reset      (RST_SIM_AXI),                                        // input

        .last       (maxigp0rlast),                               // input

        .data_stb   (maxigp0rready & maxigp0rvalid),              // input

        .raddr      (dutm0_araddr_w[SIMUL_AXI_READ_WIDTH+1:2]),   // input[9:0] 

simul_axi_hp_rd #(

        .HP_PORT(0)

    ) simul_axi_hp_rd_i (

        .rst            (RST),                               // input

        .rst            (RST_SIM_AXI),                               // input

        .aclk           (x393_i.ps7_i.SAXIHP0ACLK),          // input

        .aresetn        (),                                  // output

        .araddr         (x393_i.ps7_i.SAXIHP0ARADDR[31:0]),  // input[31:0] 

simul_axi_hp_wr #(

        .HP_PORT(0)

    ) simul_axi_hp_wr_i (

        .rst            (RST),                               // input

        .rst            (RST_SIM_AXI),                               // input

        .aclk           (x393_i.ps7_i.SAXIHP0ACLK),          // input

        .aresetn        (),                                  // output

        .awaddr         (x393_i.ps7_i.SAXIHP0AWADDR),        // input[31:0] 

simul_axi_hp_wr #(

        .HP_PORT(1)

    ) simul_axi_hp1_wr_i (

        .rst            (RST),                               // input

        .rst            (RST_SIM_AXI),                               // input

        .aclk           (x393_i.ps7_i.SAXIHP1ACLK),          // input

        .aresetn        (),                                  // output

        .awaddr         (x393_i.ps7_i.SAXIHP1AWADDR),        // input[31:0] 

    // SAXI_GP0 - histograms to system memory

    simul_saxi_gp_wr simul_saxi_gp0_wr_i (

        .rst               (RST),                         // input

        .rst               (RST_SIM_AXI),                         // input

        .aclk              (saxi0_aclk),                  // input

        .aresetn           (), // output

        .awaddr            (x393_i.ps7_i.SAXIGP0AWADDR),  // input[31:0] 

    // SAXI_GP1 - event logger to system memory

    simul_saxi_gp_wr simul_saxi_gp1_wr_i (

        .rst               (RST),                         // input

        .rst               (RST_SIM_AXI),                         // input

        .aclk              (saxi0_aclk),                  // input

        .aresetn           (), // output

        .awaddr            (x393_i.ps7_i.SAXIGP1AWADDR),  // input[31:0] 

        .VSW           (BOSON_VSW)         // 7)  87)

    ) simul_boson640_1_i (

        .mrst          (sns1_dp[7]),       // input

        .single        (1'b0), // boson_single),     // input

        .single        (boson_single),     // input 1'b0), // 

        .ext_sync      (sns1_ctl),         // input

        .pxd           (boson_pxd1),       // output[15:0] 

        .pclk          (boson_pclk1),      // output

        .VSW           (BOSON_VSW)         // 7)  87)

    ) simul_boson640_2_i (

        .mrst          (sns2_dp[7]),       // input

        .single        (1'b0), // boson_single),     // input

        .single        (boson_single),     // input 1'b0), //

        .ext_sync      (sns2_ctl),         // input

        .pxd           (boson_pxd2),       // output[15:0] 

        .pclk          (boson_pclk2),      // output

#        self.log.debug ("SAXIWrSim.__init__(): super done")

        #Open file to use as system memory

        try:

            self._memfile=open(mempath, 'r+') #keep old file if it exists already

            self._memfile=open(mempath, 'rb+') #keep old file if it exists already

        except:    

            self._memfile=open(mempath, 'w+') #create a new file if it does not exist

            self._memfile=open(mempath, 'wb+') #create a new file if it does not exist

            self.log.info ("SAXIWrSim(%s): created a new 'memory' file %s"%(name,mempath)) #

        #Extend to full size

        self._memfile.seek(memhigh-1)

                bv = self.bus.wr_data.value

                bv.binstr = re.sub("[^1]","0",bv.binstr)

                data = bv.integer

            sdata=struct.pack(self._fmt,data).decode('iso-8859-1')

#            sdata=struct.pack(self._fmt,data).decode('iso-8859-1')

            sdata = data.to_bytes(self._data_bytes, byteorder='little') # byte array

            bv = self.bus.wr_data.value    

            bv.binstr= re.sub("[^0]","1",bv.binstr) # only 0 suppresses write to this byte

            while len(bv.binstr) < self._data_bytes: # very unlikely

            else:

                for i in range (self._data_bytes):

                    if bv.binstr[-1-i] != 0:

                       self._memfile.write(sdata[i])

                        self._memfile.write(sdata[i:i+1])

                    else:

                        self._memfile.seek(1,1)

            if self.autoflush:

                rs = None

            if not rs is None:

                try:

                    data = struct.unpack(self._fmt,rs)

#                   data = struct.unpack(self._fmt,rs)

                    data = int.from_bytes(rs, byteorder='little')

                except:

                    self.log.warning ("SAXIRdSim():Can not unpack memory data @ address 0x%08x"%(address))

                    data=None

    // parameters for the sensor-synchronous clock PLL

// ALL PARAMETERS HERE SHOULD BE DEFINED (for use in C-generator)    

`define TWEAKING_IOSTANDARD

//`define TWEAKING_IOSTANDARD

`ifdef HISPI

    parameter CLKIN_PERIOD_SENSOR =      3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps

    parameter CLKFBOUT_MULT_SENSOR =     3,      // 330 MHz --> 990 MHz

    parameter CLKFBOUT_PHASE_SENSOR =    0.000,  // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)

    parameter IPCLK_PHASE =              0.000,

    parameter IPCLK2X_PHASE =            0.000,

    `ifdef TWEAKING_IOSTANDARD

        parameter PXD_IOSTANDARD =           "LVCMOS25", // with 1.8 actually applied voltage

        parameter SENSI2C_IOSTANDARD =       "LVCMOS25", // with 1.8 actually applied voltage

    `else

        parameter PXD_IOSTANDARD =           "LVCMOS18",

        parameter SENSI2C_IOSTANDARD =       "LVCMOS18",

    `endif

`else

    parameter CLKIN_PERIOD_SENSOR =      10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps

//    parameter BUF_IPCLK =                "BUFMR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3

//    parameter BUF_IPCLK2X =              "BUFMR", //G", // "BUFR",

`ifdef BOSON

    parameter BUF_IPCLK_SENS0 =          "BUFR", // "BUFR2", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3

    parameter BUF_IPCLK2X_SENS0 =        "BUFR", // "BUFIO", /// "BUFR", //G", // "BUFR",

    parameter BUF_IPCLK_SENS1 =          "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3

    parameter BUF_IPCLK2X_SENS1 =        "BUFG", // "BUFR",

    parameter BUF_IPCLK_SENS2 =          "BUFR", // "BUFR2", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3

    parameter BUF_IPCLK2X_SENS2 =        "BUFR", // "BUFIO", ///"BUFR", //G", // "BUFR",

    parameter BUF_IPCLK_SENS3 =          "BUFG", // "BUFR2", ///"BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3

    parameter BUF_IPCLK2X_SENS3 =        "BUFG", // "BUFIO", ///"BUFG", // "BUFR",

`else

    parameter BUF_IPCLK_SENS0 =          "BUFR", // "BUFR2", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3

    parameter BUF_IPCLK2X_SENS0 =        "BUFIO", /// "BUFR", //G", // "BUFR",

    parameter BUF_IPCLK_SENS3 =          "BUFG", // "BUFR2", ///"BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3

    parameter BUF_IPCLK2X_SENS3 =        "BUFG", // "BUFIO", ///"BUFG", // "BUFR",

`endif

    parameter SENS_DIVCLK_DIVIDE =       1,            // Integer 1..106. Divides all outputs with respect to CLKIN

    parameter SENS_REF_JITTER1   =       0.010,        // Expected jitter on CLKIN1 (0.000..0.999)

    parameter SENS_REF_JITTER2   =       0.010,

//`ifdef HISPI

    parameter HISPI_MSB_FIRST =            0,

`ifdef BOSON

    parameter HISPI_NUMLANES =             3,

`else

    parameter HISPI_NUMLANES =             4,

`endif

    parameter HISPI_DELAY_CLK0=           "TRUE",

    parameter HISPI_DELAY_CLK1=           "TRUE",

    parameter HISPI_DELAY_CLK2=           "TRUE",

    parameter HISPI_DELAY_CLK3=           "TRUE",

    parameter HISPI_MMCM0 =               "TRUE",

    parameter HISPI_MMCM1 =               "FALSE",

    parameter HISPI_MMCM2 =               "TRUE",

    parameter HISPI_MMCM3 =               "FALSE",

    parameter HISPI_KEEP_IRST =           5,   // number of cycles to keep irst on after release of prst (small number - use 1 hot)

    parameter HISPI_WAIT_ALL_LANES =      4'h8, // number of output pixel cycles to wait after the earliest lane

    parameter HISPI_FIFO_DEPTH =          4,

//    parameter HISPI_IOSTANDARD =          "PPDS_25", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)

//    parameter HISPI_IOSTANDARD =          "DIFF_HSTL_II_18", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)

//`endif  DIFF_HSTL_II_18

//VivadoRoute: [Route 35-54] Net: sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/sr_reg[3]__0 is not completely routed. sensor_channel.v    /x393/sensor    line 42 Problem of the external builder

//VivadoRoute: [Route 35-54] Net: sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/sr_reg[3]__0 is not completely routed. sensor_channel.v    /x393/sensor    line 42 Problem of the external builder

`ifdef BOSON

    parameter HISPI_MMCM0 =               "TRUE",

    parameter HISPI_MMCM1 =               "TRUE",

    parameter HISPI_MMCM2 =               "TRUE",

    parameter HISPI_MMCM3 =               "TRUE",

`else

    parameter HISPI_MMCM0 =               "TRUE",

    parameter HISPI_MMCM1 =               "FALSE",

    parameter HISPI_MMCM2 =               "TRUE",

    parameter HISPI_MMCM3 =               "FALSE",

`endif

    parameter CMPRS_NUM_AFI_CHN =         1, // 2, // 1 - multiplex all 4 compressors to a single AXI_HP, 2 - split between to AXI_HP

    parameter CMPRS_GROUP_ADDR =          'h600, // total of 'h60