Switching 103993-> 10399A hardware (1153e80a) · Commits · Elphel / x393

cocotb/x393_dut.v

+64 −7

Original line number	Diff line number	Diff line
		@@ -2004,7 +2004,21 @@ simul_axi_hp_wr #(
		.uart_in (sns1_dp[4]), // input sns_txd
		.uart_out (sns1_dn[4]) // output sns_rxd
		);

		`ifdef BOSON_REVA // 103993 REVA board
		simul_103993A_serializer #(
		.PCLK_FREQ_MHZ(BOSON_FPS * 0.45) // 27.0)
		) simul_103993_serializer_1_i (
		.ta({2'b10, boson_pxd1[ 4: 0]}), // input[6:0]
		.tb({2'b10, boson_pxd1[ 9: 5]}), // input[6:0]
		.tc({2'b10, boson_pxd1[14:10]}), // input[6:0]
		.td({3'b100,boson_dvalid1, boson_vsync1,boson_hsync1,boson_pxd1[15]}), // input[6:0]
		.pclk(boson_pclk1), // input
		.dp(sns1_dp[3:0]), // output[3:0]
		.dn(sns1_dn[3:0]), // output[3:0]
		.clkp(sns1_clkp), // output
		.clkn(sns1_clkn) // output
		);
		`else
		simul_103993_serializer #(
		.PCLK_FREQ_MHZ(BOSON_FPS * 0.45) // 27.0)
		) simul_103993_serializer_1_i (
		@@ -2020,7 +2034,7 @@ simul_axi_hp_wr #(
		.clkp (sns1_clkp), // output
		.clkn (sns1_clkn) // output
		);

		`endif
		simul_boson640 #(
		.DATA_FILE (BOSON_DATA_FILE), // "/input_data/pattern_160_120_16.dat"),
		.WIDTH (BOSON_WIDTH), // 160), 640),
		@@ -2044,7 +2058,21 @@ simul_axi_hp_wr #(
		.uart_in (sns2_dp[4]), // input sns_txd
		.uart_out (sns2_dn[4]) // output sns_rxd
		);

		`ifdef BOSON_REVA // 103993 REVA board
		simul_103993A_serializer #(
		.PCLK_FREQ_MHZ(BOSON_FPS * 0.45) // 27.0)
		) simul_103993_serializer_2_i (
		.ta({2'b10, boson_pxd2[ 4: 0]}), // input[6:0]
		.tb({2'b10, boson_pxd2[ 9: 5]}), // input[6:0]
		.tc({2'b10, boson_pxd2[14:10]}), // input[6:0]
		.td({3'b100,boson_dvalid2, boson_vsync2,boson_hsync2,boson_pxd2[15]}), // input[6:0]
		.pclk(boson_pclk2), // input
		.dp(sns2_dp[3:0]), // output[3:0]
		.dn(sns2_dn[3:0]), // output[3:0]
		.clkp(sns2_clkp), // output
		.clkn(sns2_clkn) // output
		);
		`else
		simul_103993_serializer #(
		.PCLK_FREQ_MHZ(BOSON_FPS * 0.45) // 27.0)
		) simul_103993_serializer_2_i (
		@@ -2060,6 +2088,7 @@ simul_axi_hp_wr #(
		.clkp (sns2_clkp), // output
		.clkn (sns2_clkn) // output
		);
		`endif

		simul_boson640 #(
		.DATA_FILE (BOSON_DATA_FILE), // "/input_data/pattern_160_120_16.dat"),
		@@ -2085,6 +2114,21 @@ simul_axi_hp_wr #(
		.uart_out (sns3_dn[4]) // output sns_rxd
		);

		`ifdef BOSON_REVA // 103993 REVA board
		simul_103993A_serializer #(
		.PCLK_FREQ_MHZ(BOSON_FPS * 0.45) // 27.0)
		) simul_103993_serializer_3_i (
		.ta({2'b10, boson_pxd3[ 4: 0]}), // input[6:0]
		.tb({2'b10, boson_pxd3[ 9: 5]}), // input[6:0]
		.tc({2'b10, boson_pxd3[14:10]}), // input[6:0]
		.td({3'b100,boson_dvalid3, boson_vsync3,boson_hsync3,boson_pxd3[15]}), // input[6:0]
		.pclk(boson_pclk3), // input
		.dp(sns3_dp[3:0]), // output[3:0]
		.dn(sns3_dn[3:0]), // output[3:0]
		.clkp(sns3_clkp), // output
		.clkn(sns3_clkn) // output
		);
		`else
		simul_103993_serializer #(
		.PCLK_FREQ_MHZ(BOSON_FPS * 0.45) // 27.0)
		) simul_103993_serializer_3_i (
		@@ -2100,6 +2144,7 @@ simul_axi_hp_wr #(
		.clkp (sns3_clkp), // output
		.clkn (sns3_clkn) // output
		);
		`endif

		simul_boson640 #(
		.DATA_FILE (BOSON_DATA_FILE), // "/input_data/pattern_160_120_16.dat"),
		@@ -2124,7 +2169,21 @@ simul_axi_hp_wr #(
		.uart_in (sns4_dp[4]), // input sns_txd
		.uart_out (sns4_dn[4]) // output sns_rxd
		);

		`ifdef BOSON_REVA // 103993 REVA board
		simul_103993A_serializer #(
		.PCLK_FREQ_MHZ(BOSON_FPS * 0.45) // 27.0)
		) simul_103993_serializer_4_i (
		.ta({2'b10, boson_pxd4[ 4: 0]}), // input[6:0]
		.tb({2'b10, boson_pxd4[ 9: 5]}), // input[6:0]
		.tc({2'b10, boson_pxd4[14:10]}), // input[6:0]
		.td({3'b100,boson_dvalid4, boson_vsync4,boson_hsync4,boson_pxd4[15]}), // input[6:0]
		.pclk(boson_pclk4), // input
		.dp(sns4_dp[3:0]), // output[3:0]
		.dn(sns4_dn[3:0]), // output[3:0]
		.clkp(sns4_clkp), // output
		.clkn(sns4_clkn) // output
		);
		`else
		simul_103993_serializer #(
		.PCLK_FREQ_MHZ(BOSON_FPS * 0.45) // 27.0)
		) simul_103993_serializer_4_i (
		@@ -2140,9 +2199,7 @@ simul_axi_hp_wr #(
		.clkp (sns4_clkp), // output
		.clkn (sns4_clkn) // output
		);



		`endif
		`else

fpga_version.vh

+2 −1

Original line number	Diff line number	Diff line
		@@ -35,7 +35,8 @@
		* contains all the components and scripts required to completely simulate it
		* with at least one of the Free Software programs.
		*/
		parameter FPGA_VERSION = 32'h03934006; // Boson640, adjusted initial phase to 70.5 degrees (47 counts)
		parameter FPGA_VERSION = 32'h03934010; // Boson640, for 103993A
		// parameter FPGA_VERSION = 32'h03934006; // Boson640, adjusted initial phase to 70.5 degrees (47 counts)
		// parameter FPGA_VERSION = 32'h03934005; // Boson640, testing
		// parameter FPGA_VERSION = 32'h03934005; // Boson640, implementing DRP to control MMCME2/PLLE2 trying more BUFR
		// parameter FPGA_VERSION = 32'h03934004; // Boson640, implementing DRP to control MMCME2/PLLE2

includes/x393_parameters.vh

+12 −3

Original line number	Diff line number	Diff line
		@@ -727,12 +727,17 @@
		`endif
		`elsif BOSON
		parameter CLKIN_PERIOD_SENSOR = 37.037, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
		`ifdef BOSON_REVA
		parameter CLKFBOUT_MULT_SENSOR = 35, // 945 MHz 28, // 27 MHz --> 756 MHz
		`else
		parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz)
		`endif
		//MMCME2_ADV_i has a CLKFBOUT_PHASE value (-20.000) with CLKFBOUT_USE_FINE_PS set to FALSE. It should be a multiple of [45 / CLKFBOUT_MULT_F] = [45 / 30.000] = 1.500.
		`ifdef SIMULATION
		parameter CLKFBOUT_PHASE_SENSOR = 54.0, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
		`else
		parameter CLKFBOUT_PHASE_SENSOR = 70.5, // -22.5, // -21.0, // 19.5, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
		//It should be a multiple of [45 / CLKFBOUT_MULT_F] = [45 / 35.000] = 1.286
		parameter CLKFBOUT_PHASE_SENSOR = 0.0, // 70.5, // -22.5, // -21.0, // 19.5, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
		`endif
		parameter PCLK_PHASE = 0.000, // not used
		parameter IPCLK1X_PHASE = 0.000, // -3.000, // trying both ways (PCLK_PHASE inside sens_103993)
		@@ -850,7 +855,11 @@
		//`ifdef HISPI
		parameter HISPI_MSB_FIRST = 0,
		`ifdef BOSON
		`ifdef BOSON_REVA
		parameter HISPI_NUMLANES = 4,
		`else
		parameter HISPI_NUMLANES = 3,
		`endif
		`else
		parameter HISPI_NUMLANES = 4,
		`endif

py393/x393_sensor.py

+4 −3

Original line number	Diff line number	Diff line
		@@ -1951,7 +1951,8 @@ uart_print_packet 0 False False
		ClkReg1, ClkReg2 = self.drp_phase_addr(clk_out)
		data1 = self.drp_read_reg(num_sensor, ClkReg1)
		data2 = self.drp_read_reg(num_sensor, ClkReg2)
		phase = ((data1 >> 13) & 7) \| ((data2 & 0x1f) << 3)
		# phase = ((data1 >> 13) & 7) \| ((data2 & 0x1f) << 3)
		phase = ((data1 >> 13) & 7) \| ((data2 & 0x3f) << 3)
		return phase

		def drp_write_clock_phase(self,
		@@ -1967,9 +1968,9 @@ uart_print_packet 0 False False

		ClkReg1, ClkReg2 = self.drp_phase_addr(clk_out)
		data1 = (phase & 7) << 13
		data2 = (phase >> 3) & 0x1f
		data2 = (phase >> 3) & 0x3f
		self.drp_write_reg(num_sensor, addr=ClkReg1, data=data1, mask=0xe000)
		self.drp_write_reg(num_sensor, addr=ClkReg2, data=data2, mask=0x001f)
		self.drp_write_reg(num_sensor, addr=ClkReg2, data=data2, mask=0x003f)

		def jtag_get_tdo(self, chn):
		seq_num = ((self.get_status_sensor_io(num_sensor = chn) >> 26) + 1) & 0x3f

sensor/sens_103993.v

+76 −4

Original line number	Diff line number	Diff line
		@@ -118,7 +118,11 @@ module sens_103993 #(
		parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns

		// parameter LVDS_MSB_FIRST = 0,
		`ifdef BOSON_REVA
		parameter NUMLANES = 4,
		`else
		parameter NUMLANES = 3,
		`endif
		parameter LVDS_DELAY_CLK = "FALSE",
		parameter LVDS_MMCM = "TRUE",
		parameter LVDS_CAPACITANCE = "DONT_CARE",
		@@ -283,7 +287,11 @@ module sens_103993 #(
		wire senspgmin; // detect sensorboard
		// GP0..GP3 are not yet used, fake-use gp_comb to keep
		wire [3:0] gp;
		`ifdef BOSON_REVA
		wire [0:0] dummy; // to keep iostandard of unused pins in a bank
		`else
		wire [2:0] dummy; // to keep iostandard of unused pins in a bank
		`endif
		wire gp_comb = (^gp[3:0]) ^ (^dummy);
		reg test_patt;
		reg [7:0] perr_cntr;
		@@ -483,13 +491,76 @@ module sens_103993 #(
		wire clkin_pxd_stopped_mmcm1;
		wire clkfb_pxd_stopped_mmcm1;
		*/
		`ifdef USE_SERIALIZER_103993
		`ifdef BOSON_REVA
		sens_103993A_lanes #(
		.IODELAY_GRP (IODELAY_GRP),
		.IDELAY_VALUE (IDELAY_VALUE),
		.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
		.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
		.SENS_BANDWIDTH (SENS_BANDWIDTH),
		.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR), // 37.037),
		.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR), // (30),
		.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR), // (54.0),
		.PCLK_PHASE (PCLK_PHASE), // (0.000),
		.IPCLK1X_PHASE (IPCLK1X_PHASE), //(0.000), // not actually used
		.IPCLK2X_PHASE (IPCLK2X_PHASE), //(0.000),
		.BUF_PCLK (BUF_PCLK), // "BUFR"),
		.BUF_IPCLK1X (BUF_IPCLK1X),
		.BUF_IPCLK2X (BUF_IPCLK2X), // "BUFR"),
		.BUF_CLK_FB (BUF_CLK_FB),
		.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE), // 1),
		.SENS_REF_JITTER1 (SENS_REF_JITTER1), // 0.010),
		.SENS_REF_JITTER2 (SENS_REF_JITTER2), // 0.010),
		.SENS_SS_EN (SENS_SS_EN), // "FALSE"),
		.SENS_SS_MODE (SENS_SS_MODE), // "CENTER_HIGH"),
		.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD), // 10000),
		.NUMLANES (NUMLANES), // 3),
		.LVDS_DELAY_CLK (LVDS_DELAY_CLK), // "FALSE"),
		.LVDS_MMCM (LVDS_MMCM), // "TRUE"),
		.LVDS_CAPACITANCE (LVDS_CAPACITANCE), // "DONT_CARE"),
		.LVDS_DIFF_TERM (LVDS_DIFF_TERM), // "TRUE"),
		.LVDS_UNTUNED_SPLIT (LVDS_UNTUNED_SPLIT), // "FALSE"),
		.LVDS_DQS_BIAS (LVDS_DQS_BIAS), // "TRUE"),
		.LVDS_IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE), // "0"),
		.LVDS_IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR), // "TRUE"),
		.LVDS_IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE), // "AUTO"),
		.LVDS_IOSTANDARD (LVDS_IOSTANDARD), // "DIFF_SSTL18_I")
		.DEGLITCH_DVALID (1),
		.DEGLITCH_HSYNC (3),
		.DEGLITCH_VSYNC (7)
		) sens_103993_l3_i ( // same instance name
		.pclk (pclk), // output
		.prsts (prsts), // input,
		.sns_dp (sns_dp[3:0]), // input[3:0]
		.sns_dn (sns_dn[3:0]), // input[3:0]
		.sns_clkp (sns_clkp), // input
		.sns_clkn (sns_clkn), // input
		.pxd_out (pxd_w), // output[15:0]
		.vsync (vsync), // output
		.hsync (hsync), // output
		.dvalid (dvalid_w), // output
		.mclk (mclk), // input
		.mrst (mrst), // input
		.dly_data (data_r[31:0]), // input[31:0]
		.set_idelay ({NUMLANES{set_idelays}}),// input[2:0]
		.apply_idelay (ld_idelay), // input
		.set_clk_phase (set_iclk_phase), // input
		.rst_mmcm (rst_mmcm), // input
		.perr (perr), // output
		.test_out (test_out), // output[7:0] // should be 0x17
		.locked_pxd_mmcm (locked_pclk), // output
		.clkin_pxd_stopped_mmcm (clkin_pxd_stopped_mmcm), // output
		.clkfb_pxd_stopped_mmcm (clkfb_pxd_stopped_mmcm), // output
		.drp_cmd (drp_cmd), // input[1:0]
		.drp_bit (drp_bit), // output
		.drp_odd_bit (drp_odd_bit) // output
		);
		`elsif USE_SERIALIZER_103993
		sens_103993_lanes #(
		.IODELAY_GRP (IODELAY_GRP),
		.IDELAY_VALUE (IDELAY_VALUE),
		.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
		.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
		// .SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
		.SENS_BANDWIDTH (SENS_BANDWIDTH),
		.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR), // 37.037),
		.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR), // (30),
		@@ -767,7 +838,8 @@ module sens_103993 #(
		.T (1'b0) // input
		);
		*/

		`ifdef BOSON_REVA
		`else
		ibuf_ibufg #(
		.CAPACITANCE (PXD_CAPACITANCE),
		.IBUF_DELAY_VALUE("0"),
		@@ -788,7 +860,7 @@ module sens_103993 #(
		.O(dummy[2]), // output
		.I(sns_dp[3]) // input
		);

		`endif
		// end of dummy

		// pulldown to detect sensor presense

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