commands and status for LWIR/VOSPI, exported to C (691579c0) · Commits · Elphel / x393

includes/x393_parameters.vh

+45 −8

Original line number	Diff line number	Diff line
		@@ -35,6 +35,9 @@
		* contains all the components and scripts required to completely simulate it
		* with at least one of the Free Software programs.
		*/

		// All paremeters should be defined for all defines values - needed to export to C

		parameter MCONTR_WR_MASK = 'h3c00, // AXI write address mask for the 1Kx32 buffers command sequence memory
		parameter MCONTR_RD_MASK = 'h3c00, // AXI read address mask to generate busy

		@@ -533,7 +536,40 @@
		parameter SENSI2C_IBUF_LOW_PWR= "TRUE",
		parameter SENSI2C_SLEW = "SLOW",

		//`ifndef HISPI
		//`ifdef HISPI
		//`elsif LWIR
		parameter VOSPI_EN = 0,
		parameter VOSPI_EN_BITS = 2,
		parameter VOSPI_SEGM0_OK = 2,
		parameter VOSPI_SEGM0_OK_BITS = 2,
		parameter VOSPI_OUT_EN = 4,
		parameter VOSPI_OUT_EN_BITS = 2,
		parameter VOSPI_OUT_EN_SINGL = 6,
		parameter VOSPI_RESET_CRC = 7,
		parameter VOSPI_MRST = 8,
		parameter VOSPI_MRST_BITS = 2,
		parameter VOSPI_PWDN = 10,
		parameter VOSPI_PWDN_BITS = 2,
		parameter VOSPI_MCLK = 12,
		parameter VOSPI_MCLK_BITS = 2,
		parameter VOSPI_SPI_CLK = 14,
		parameter VOSPI_SPI_CLK_BITS = 2,
		parameter VOSPI_GPIO = 16,
		parameter VOSPI_GPIO_BITS = 8,
		parameter VOSPI_FAKE_OUT = 24, // to keep hardware
		parameter VOSPI_MOSI = 25, // not used
		parameter VOSPI_PACKET_WORDS = 80,
		parameter VOSPI_NO_INVALID = 1, // do not output invalid packets data
		parameter VOSPI_PACKETS_PER_LINE = 2,
		parameter VOSPI_SEGMENT_FIRST = 1,
		parameter VOSPI_SEGMENT_LAST = 4,
		parameter VOSPI_PACKET_FIRST = 0,
		parameter VOSPI_PACKET_LAST = 60,
		parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided
		parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT
		parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF

		//`else
		//sensor_fifo parameters
		parameter SENSOR_DATA_WIDTH = 12,
		parameter SENSOR_FIFO_2DEPTH = 4,
		@@ -927,6 +963,7 @@
		parameter MULTICLK_DIV_XCLK2X = 6, // 200 MHz for compressor (when MULTICLK_DIV_XCLK uses 100 MHz)
		`else
		parameter MULTICLK_DIV_XCLK = 5, // 240 MHz for compressor (12 for 100 MHz)
		parameter MULTICLK_DIV_XCLK2X = 6, // unused value
		`endif
		parameter MULTICLK_DIV_SYNC = 12, // 100 MHz for inter-camera synchronization and time keeping
		// Additional parameters for multi-clock PLL (phases and buffer types)

py393/vrlg.py

+299 −80

File changed.

Preview size limit exceeded, changes collapsed.

py393/x393_export_c.py

+47 −4

Original line number	Diff line number	Diff line
		@@ -322,7 +322,9 @@ class X393ExportC(object):
		frmt_spcs = frmt_spcs)

		stypedefs += self.get_typedef32(comment = "Sensor/multiplexer I/O pins status",
		data = [self._enc_status_sens_io(),self._enc_status_sens_io_hispi()],
		data = [self._enc_status_sens_io(),
		self._enc_status_sens_io_hispi(),
		self._enc_status_sens_io_vospi()],
		name = "x393_status_sens_io", typ="ro",
		frmt_spcs = frmt_spcs)

		@@ -431,7 +433,8 @@ class X393ExportC(object):

		stypedefs += self.get_typedef32(comment = "Sensor port I/O control",
		data = [self._enc_sensio_ctrl_par12(),
		self._enc_sensio_ctrl_hispi()],
		self._enc_sensio_ctrl_hispi(),
		self._enc_sensio_ctrl_vospi()],
		name = "x393_sensio_ctl", typ="wo",
		frmt_spcs = frmt_spcs)
		stypedefs += self.get_typedef32(comment = "Programming interface for multiplexer FPGA",
		@@ -1853,7 +1856,7 @@ class X393ExportC(object):
		dw.append(("hact_ext_alive", 14, 1,0, "HACT signal from the sensor is toggling (N/A for HiSPI)"))
		dw.append(("vact_alive", 15, 1,0, "VACT signal from the sensor is toggling (N/A for HiSPI)"))
		dw.append(("xfpgatdo_byte", 16, 8,0, "Multiplexer FPGA TDO output"))
		dw.append(("senspgmin", 24, 1,0, "senspgm pin state"))
		dw.append(("senspgmin", 24, 1,0, "senspgm pin state (0 means non-FPGA SFE is present)"))
		dw.append(("xfpgatdo", 25, 1,0, "Multiplexer FPGA TDO output"))
		dw.append(("seq_num", 26, 6,0, "Sequence number"))
		return dw
		@@ -1876,11 +1879,26 @@ class X393ExportC(object):
		# dw.append(("rel_sol", 18, 3,0, "When SOL active on the last lane @ipclk, latches all other lanes SOL"))
		# dw.append(("vact_alive", 15, 1,0, "VACT signal from the sensor is toggling (N/A for HiSPI)"))
		# dw.append(("xfpgatdo_byte", 16, 8,0, "Multiplexer FPGA TDO output"))
		dw.append(("senspgmin", 24, 1,0, "senspgm pin state"))
		dw.append(("senspgmin", 24, 1,0, "senspgm pin state (0 means non-FPGA SFE is present)"))
		dw.append(("xfpgatdo", 25, 1,0, "Multiplexer FPGA TDO output"))
		dw.append(("seq_num", 26, 6,0, "Sequence number"))
		return dw

		def _enc_status_sens_io_vospi(self):
		dw=[]
		dw.append(("segment_id", 0, 4,0, "ID of the last received segment: 1-4 for the good frame, 0 - for ITAR-skipped frames"))
		dw.append(("gpio_in", 4, 4,0, "Input from GPIO0-GPIO3, only GPIO3 may be used as segment ready"))
		dw.append(("in_busy", 8, 1,0, "Frame segments are waited for or received to FIFO"))
		dw.append(("out_busy", 9, 1,0, "received frame is being transferred to video memory"))
		dw.append(("crc_err", 10, 1,0, "At least 1 CRC error happened since reset by command bit"))
		dw.append(("fake in", 11, 1,0, "Just to keep hardware"))
		dw.append(("senspgmin", 24, 1,0, "senspgm pin state (0 means non-FPGA SFE is present)"))
		dw.append(("busy", 25, 1,0, "in_busy OR out_busy"))
		dw.append(("seq_num", 26, 6,0, "Sequence number"))
		return dw



		def _enc_status_sens_i2c(self):
		dw=[]
		dw.append(("i2c_fifo_dout", 0, 8,0, "I2c byte read from the device through FIFO"))
		@@ -2107,6 +2125,31 @@ class X393ExportC(object):
		dw.append(("gp1_set", vrlg.SENS_CTRL_GP1 + 2, 1, 0, "Set GP1 to 'gp1' value"))
		return dw

		def _enc_sensio_ctrl_vospi(self):
		dw=[]
		dw.append(("spi_en", vrlg.VOSPI_EN, 2, 0, "SPI Reset/enable: 0 - NOP, 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable"))
		dw.append(("segm_zero", vrlg.VOSPI_SEGM0_OK, 1, 0, "OK to input segment 0 (invalid, valid are 1,2,3,4)"))
		dw.append(("segm_zero_set",vrlg.VOSPI_SEGM0_OK + 1, 1, 0, "Enable setting of segm_zero"))
		dw.append(("out_en", vrlg.VOSPI_OUT_EN, 1, 0, "Enable output sensor data to memory"))
		dw.append(("out_en_set", vrlg.VOSPI_OUT_EN + 1, 1, 0, "Set enable sensor data to memory"))
		dw.append(("out_single", vrlg.VOSPI_OUT_EN_SINGL, 1, 0, "Enable single sensor frame to memory"))
		dw.append(("reset_crc", vrlg.VOSPI_RESET_CRC, 1, 0, "Reset CRC error status bit"))
		dw.append(("rst", vrlg.VOSPI_MRST, 1, 0, "RESET signal level to the sensor (0 - low(active), 1 - high (inactive)"))
		dw.append(("rst_set", vrlg.VOSPI_MRST + 1, 1, 0, "When set to 1, RESET is set to the 'rst' field value"))
		dw.append(("pwdn", vrlg.VOSPI_PWDN, 1, 0, "POWER DOWN signal level to the sensor (0 - low(active), 1 - high (inactive)"))
		dw.append(("pwdn_set", vrlg.VOSPI_PWDN + 1, 1, 0, "When set to 1, POWER DOWN is set to the 'pwdn' field value"))
		dw.append(("mclk", vrlg.VOSPI_MCLK, 1, 0, "Enable master clock (25MHz) to sensor"))
		dw.append(("mclk_set", vrlg.VOSPI_MCLK + 1, 1, 0, "When set to 1, MCLK enable is set to the 'mclk' field value"))
		dw.append(("spi_clk", vrlg.VOSPI_SPI_CLK, 1, 0, "Enable continuous SPI clock (0 - only when SPI CS is active)"))
		dw.append(("spi_clk_set", vrlg.VOSPI_SPI_CLK + 1, 1, 0, "When set to 1, SPI CLK enable is set to the 'spi_clk' field value"))
		dw.append(("gpio0", vrlg.VOSPI_GPIO , 2, 0, "Output control for GPIO0: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
		dw.append(("gpio1", vrlg.VOSPI_GPIO+2, 2, 0, "Output control for GPIO1: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
		dw.append(("gpio2", vrlg.VOSPI_GPIO+4, 2, 0, "Output control for GPIO2: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
		dw.append(("gpio3", vrlg.VOSPI_GPIO+6, 2, 0, "Output control for GPIO3: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
		dw.append(("fake", vrlg.VOSPI_FAKE_OUT, 1, 0, "Just to keep I/O ports from optimization"))
		dw.append(("mosi", vrlg.VOSPI_MOSI, 1, 0, "Just to keep I/O ports from optimization"))
		return dw

		def _enc_sensio_jtag(self):
		dw=[]
		dw.append(("tdi", vrlg.SENS_JTAG_TDI, 1, 0, "JTAG TDI level"))

sensor/sens_lepton3.v

+295 −51

Original line number	Diff line number	Diff line
		@@ -78,7 +78,6 @@ module sens_lepton3 #(
		parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",

		parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
		// parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
		parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"

		parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
		@@ -96,7 +95,39 @@ module sens_lepton3 #(
		parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
		parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
		parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
		parameter STATUS_ALIVE_WIDTH = 4
		parameter STATUS_ALIVE_WIDTH = 4,

		// mode bits
		parameter VOSPI_EN = 0,
		parameter VOSPI_EN_BITS = 2,
		parameter VOSPI_SEGM0_OK = 2,
		parameter VOSPI_SEGM0_OK_BITS = 2,
		parameter VOSPI_OUT_EN = 4,
		parameter VOSPI_OUT_EN_BITS = 2,
		parameter VOSPI_OUT_EN_SINGL = 6,
		parameter VOSPI_RESET_CRC = 7,
		parameter VOSPI_MRST = 8,
		parameter VOSPI_MRST_BITS = 2,
		parameter VOSPI_PWDN = 10,
		parameter VOSPI_PWDN_BITS = 2,
		parameter VOSPI_MCLK = 12,
		parameter VOSPI_MCLK_BITS = 2,
		parameter VOSPI_SPI_CLK = 14,
		parameter VOSPI_SPI_CLK_BITS = 2,
		parameter VOSPI_GPIO = 16,
		parameter VOSPI_GPIO_BITS = 8,
		parameter VOSPI_FAKE_OUT = 24, // to keep hardware
		parameter VOSPI_MOSI = 25, // pot used
		parameter VOSPI_PACKET_WORDS = 80,
		parameter VOSPI_NO_INVALID = 1, // do not output invalid packets data
		parameter VOSPI_PACKETS_PER_LINE = 2,
		parameter VOSPI_SEGMENT_FIRST = 1,
		parameter VOSPI_SEGMENT_LAST = 4,
		parameter VOSPI_PACKET_FIRST = 0,
		parameter VOSPI_PACKET_LAST = 60,
		parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided
		parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT
		parameter VOSPI_HACT_TO_HACT_EOF = 2 // minimal clock cycles from HACT to HACT or to EOF
		)(
		// programming interface
		input mrst, // @posedge mclk, sync reset
		@@ -138,34 +169,115 @@ module sens_lepton3 #(
		output sof, // @pclk
		output eof // @pclk
		);
		localparam VOSPI_STATUS_BITS = 14;
		// Status data (6 bits + 4)
		wire [VOSPI_STATUS_BITS-1:0] status;
		wire [ 3:0] segment_id;
		wire crc_err_w; // single-cycle CRC error
		reg crc_err_r; // at least one CRC error happened since reset
		wire in_busy;
		wire out_busy;
		wire [ 3:0] gpio_in; // none currently used
		wire fake_in;

		assign status = {
		fake_in,
		crc_err_r,
		out_busy,
		in_busy,
		gpio_in [3:0],
		segment_id [3:0],
		out_busy \| in_busy, senspgm_int
		};
		/*
		xfpgatdo_byte[7:0],
		vact_alive, hact_ext_alive, hact_alive, locked_pxd_mmcm,
		clkin_pxd_stopped_mmcm, clkfb_pxd_stopped_mmcm, xfpgadone,
		ps_rdy, ps_out,
		xfpgatdo, senspgmin}; // go to bits 24, 25 when read
		*/

		// mode register (4 bits + 8 + 1)
		/*
		bits 0,1: 0: nop
		1 - nreset=0 disable
		2 - nreset, disable
		3 - nreset, enable
		2,3: 0,1 - nop
		2 - disable invalid segments
		3 - enabl;e invalid segments
		4,5: 0,1 - nop
		2 - disable out_en
		3 - enabl;e out_en
		6: 0 - nop,
		1 - single frame out_en
		7: reset CRC error
		8,9: 0,1 - nop
		2 - lwir_mrst <= 0 (active reset)
		3 - lwir_mrst <= 1 (inactive)
		10,11: 0,1 - nop
		2 - lwir_pwdn <= 0 (active, disable sensor)
		3 - lwir_pwdn <= 1 (inactive)
		12,13: 0,1 - nop
		2 - disable sns_mclk (25 MHz clock to sensor)
		3 - enable sns_mclk
		14,15: 0,1 - nop
		2 - disable spi_clk (stop between CS acvtive)
		3 - enabl;e spi_clk (continuously run evenwhen CS is acvtive)
		16-23: GPIO[3:0] - use gpio_bit() and generate
		24 - fake_out
		25 - spi_mosi_int
		*/

		// then re-sync to pclk (and to sns_mclk)
		reg spi_nrst_mclk;
		reg spi_en_mclk;
		reg segm0_ok_mclk; // from mode register?
		reg out_en_mclk; // single paulse - single frame, level - continuous
		wire out_en_single_mclk;
		wire crc_reset_mclk;
		reg lwir_mrst_mclk;
		reg lwir_pwdn_mclk;
		reg sns_mclk_en_mclk;
		reg spi_clk_en_mclk;
		wire [ 3:0] gpio_out; // only [3] may be used
		wire [ 3:0] gpio_en; // none currently used

		// resynced to pclk
		reg [ 1:0] spi_nrst_pclk; // reset spi and frame immediately (will need to reset sensor too)
		reg [ 1:0] spi_en_pclk; // enable spi communications
		reg [ 1:0] segm0_ok_pclk; // allow illegal segments
		reg [ 1:0] out_en_pclk;
		reg [ 1:0] lwir_mrst_pclk;
		reg [ 1:0] lwir_pwdn_pclk;
		// reg [ 1:0] sns_mclk_en_pclk;
		reg [ 1:0] spi_clk_en_pclk;
		wire out_en_single_pclk;
		wire crc_reset_pclk;


		wire fake_out;
		wire fake_in;
		wire spi_mosi_int; // not used

		reg out_en_r; // single paulse - single frame, level - continuous

		wire [25:0] status; // added byte-wide xfpgatdo

		wire cmd_we;
		wire [2:0] cmd_a;
		wire [31:0] cmd_data;
		reg [31:0] data_r;
		reg set_ctrl_r;
		reg set_status_r;

		wire spi_clk_en_mclk;
		wire sns_mclk_en_mclk;

		reg [ 1:0] spi_clk_en_pclk;
		reg [ 1:0] sns_mclk_en_lwir_mclk;
		wire spi_clken; // from lower module, clock will be combined


		wire spi_miso_int;
		wire spi_cs_int;
		wire spi_mosi_int;
		wire [ 3:0] gpio_in; // only [3] may be used
		wire [ 3:0] gpio_out; // none currently used
		wire [ 3:0] gpio_en = 0; // none currently used
		wire lwir_mrst_int;
		wire lwir_pwdn_int;
		wire senspgm_int;
		wire sns_ctl_int;
		// not implemented in the sesnor, put dummy input buffer5s
		// not implemented in the sensor, put dummy input buffer5s
		wire mipi_dp_int;
		wire mipi_dn_int;
		wire mipi_clkp_int;
		@@ -173,28 +285,87 @@ module sens_lepton3 #(


		// temporary?
		assign fake_in = senspgm_int ^ sns_ctl_int ^ mipi_dp_int ^ mipi_dn_int ^ mipi_clkp_int ^ mipi_clkn_int;
		// assign fake_out = data_r[31];
		assign status[25] = fake_in;
		assign fake_in = sns_ctl_int ^ mipi_dp_int ^ mipi_dn_int ^ mipi_clkp_int ^ mipi_clkn_int;

		// bit assignment will change
		assign spi_clk_en_mclk = data_r[2];
		assign sns_mclk_en_mclk = data_r[3];
		assign out_en_single_mclk = set_ctrl_r && data_r[VOSPI_OUT_EN_SINGL] && !mrst;
		assign crc_reset_mclk = set_ctrl_r && data_r[VOSPI_RESET_CRC] && !mrst;
		assign fake_out = set_ctrl_r && data_r[VOSPI_FAKE_OUT];
		assign spi_mosi_int = set_ctrl_r && data_r[VOSPI_MOSI]; // not used

		assign prsts = prst \| lwir_mrst_pclk[1];

		always @(posedge mclk) begin
		if (mrst) data_r <= 0;
		else if (cmd_we) data_r <= cmd_data;
		end

		if (mrst) set_status_r <=0;
		else set_status_r <= cmd_we && (cmd_a== SENSIO_STATUS);

		if (mrst) set_ctrl_r <=0;
		else set_ctrl_r <= cmd_we && (cmd_a== SENSIO_CTRL);

		if (mrst) spi_nrst_mclk <= 0;
		else if (set_ctrl_r && \|data_r[VOSPI_EN +: VOSPI_EN_BITS]) spi_nrst_mclk <= data_r[VOSPI_EN + 1];

		if (mrst) spi_en_mclk <= 0;
		else if (set_ctrl_r && \|data_r[VOSPI_EN +: VOSPI_EN_BITS]) spi_en_mclk <= &data_r[VOSPI_EN +: 2];

		if (mrst) segm0_ok_mclk <= 0;
		else if (set_ctrl_r && data_r[VOSPI_SEGM0_OK + VOSPI_SEGM0_OK_BITS - 1]) segm0_ok_mclk <= data_r[VOSPI_SEGM0_OK];

		if (mrst) out_en_mclk <= 0;
		else if (set_ctrl_r && data_r[VOSPI_OUT_EN + VOSPI_OUT_EN_BITS - 1]) out_en_mclk <= data_r[VOSPI_OUT_EN];

		if (mrst) lwir_mrst_mclk <= 0;
		else if (set_ctrl_r && data_r[VOSPI_MRST + VOSPI_MRST_BITS - 1]) lwir_mrst_mclk <= data_r[VOSPI_MRST];

		if (mrst) lwir_pwdn_mclk <= 0;
		else if (set_ctrl_r && data_r[VOSPI_PWDN + VOSPI_PWDN_BITS - 1]) lwir_pwdn_mclk <= data_r[VOSPI_PWDN];

		if (mrst) sns_mclk_en_mclk <= 0;
		else if (set_ctrl_r && data_r[VOSPI_MCLK + VOSPI_MCLK_BITS - 1]) sns_mclk_en_mclk <= data_r[VOSPI_MCLK];

		if (mrst) spi_clk_en_mclk <= 0;
		else if (set_ctrl_r && data_r[VOSPI_SPI_CLK + VOSPI_SPI_CLK_BITS - 1]) spi_clk_en_mclk <= data_r[VOSPI_SPI_CLK];
		end
		// resync to pclk
		always @ (posedge pclk) begin
		spi_nrst_pclk[1:0] <= {spi_nrst_pclk[0], spi_nrst_mclk};
		spi_en_pclk[1:0] <= {spi_en_pclk[0], spi_en_mclk};
		segm0_ok_pclk[1:0] <= {segm0_ok_pclk[0], segm0_ok_mclk};
		out_en_pclk[1:0] <= {out_en_pclk[0], out_en_mclk};
		lwir_mrst_pclk[1:0] <= {lwir_mrst_pclk[0], lwir_mrst_mclk};
		lwir_pwdn_pclk[1:0] <= {lwir_pwdn_pclk[0], lwir_pwdn_mclk};
		spi_clk_en_pclk[1:0] <= {spi_clk_en_pclk[0], spi_clk_en_mclk};

		out_en_r <= out_en_single_pclk \| out_en_pclk[1];

		if (prst \|\| crc_reset_pclk) crc_err_r <= 0;
		else if (crc_err_w) crc_err_r <= 1;

		end

		always @(posedge sns_mclk) begin
		sns_mclk_en_lwir_mclk[1:0] <= {sns_mclk_en_lwir_mclk[0],sns_mclk_en_mclk};
		end

		pulse_cross_clock pulse_cross_clock_out_en_single_i (
		.rst (mrst), // input
		.src_clk (mclk), // input
		.dst_clk (pclk), // input
		.in_pulse (out_en_single_mclk), // input
		.out_pulse (out_en_single_pclk), // output
		.busy() // output
		);

		pulse_cross_clock pulse_cross_clock_crc_reset_i (
		.rst (mrst), // input
		.src_clk (mclk), // input
		.dst_clk (pclk), // input
		.in_pulse (crc_reset_mclk), // input
		.out_pulse (crc_reset_pclk), // output
		.busy() // output
		);

		// implement I/O ports, including fake ones, to be able to assign them I/O pads
		// generate clocka to sesnor output, controlled by control word bits
		@@ -207,7 +378,7 @@ module sens_lepton3 #(
		.SRTYPE ("SYNC")
		) spi_clk_i (
		.clk (pclk), // input
		.ce (spi_clk_en_pclk[1]), // input
		.ce (spi_clk_en_pclk[1] \| spi_clken), // input
		.rst (prst), // input
		.set (1'b0), // input
		.din (2'b01), // input[1:0]
		@@ -269,7 +440,16 @@ module sens_lepton3 #(

		generate // gpio[3:0]
		genvar i;
		for (i=0; i < 4; i=i+1) begin: gpio_block
		for (i=0; i < (VOSPI_GPIO_BITS / 2); i=i+1) begin: gpio_block
		gpio_bit gpio_bit_i (
		.clk (mclk), // input
		.srst (mrst), // input
		.we (set_ctrl_r), // input
		.d_in (data_r[VOSPI_GPIO + 2*i +: 2]), // input[1:0]
		.d_out (gpio_out[i]), // output
		.en_out (gpio_en[i]) // output
		);

		iobuf #(
		.DRIVE (PXD_DRIVE),
		.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
		@@ -285,6 +465,7 @@ module sens_lepton3 #(
		end
		endgenerate

		// for debug/test alive
		iobuf #( // lwir_mrst
		.DRIVE (PXD_DRIVE),
		.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
		@@ -293,7 +474,7 @@ module sens_lepton3 #(
		) lwir_mrst_i (
		.O (), // output - currently not used
		.IO (lwir_mrst), // inout I/O pad
		.I (lwir_mrst_int), // input
		.I (lwir_mrst_pclk[0]), // input
		.T (1'b0) // input - always on
		);

		@@ -305,7 +486,7 @@ module sens_lepton3 #(
		) lwir_pwdn_i (
		.O (), // output - currently not used
		.IO (lwir_pwdn), // inout I/O pad
		.I (lwir_pwdn_int), // input
		.I (lwir_pwdn_pclk[0]), // input
		.T (1'b0) // input - always on
		);

		@@ -382,6 +563,68 @@ module sens_lepton3 #(
		.T (1'b1) // input - always off
		);


		wire segment_done;
		wire discard_segment;
		reg start_segment;
		reg [ 3:0] exp_segment;
		reg spi_en_d;
		// first frame has to be good (only segments only 1..4), next can continue with 0-s
		reg segm0_ok_r;

		always @(posedge pclk) begin
		// spi_en_d <= spi_nrst_pclk[1];
		spi_en_d <= spi_en_pclk[1];


		if (!spi_en_d) exp_segment <= VOSPI_SEGMENT_FIRST;
		else if (segment_done && !discard_segment) exp_segment <= (exp_segment == VOSPI_SEGMENT_LAST) ?
		VOSPI_SEGMENT_FIRST :
		(exp_segment + 1);
		if (!spi_en_d) segm0_ok_r <= 0;
		else if (segment_done && !discard_segment && (exp_segment == VOSPI_SEGMENT_LAST)) segm0_ok_r <= segm0_ok_pclk[1];

		start_segment <= spi_en_d && !in_busy && !start_segment;


		end



		vospi_segment_61 #(
		.VOSPI_PACKET_WORDS (VOSPI_PACKET_WORDS), // 80
		.VOSPI_NO_INVALID (VOSPI_NO_INVALID), // 1
		.VOSPI_PACKETS_PER_LINE (VOSPI_PACKETS_PER_LINE), // 2
		.VOSPI_SEGMENT_FIRST (VOSPI_SEGMENT_FIRST), // 1
		.VOSPI_SEGMENT_LAST (VOSPI_SEGMENT_LAST), // 4
		.VOSPI_PACKET_FIRST (VOSPI_PACKET_FIRST), // 0
		.VOSPI_PACKET_LAST (VOSPI_PACKET_LAST), // 60
		.VOSPI_PACKET_TTT (VOSPI_PACKET_TTT), // 20
		.VOSPI_SOF_TO_HACT (VOSPI_SOF_TO_HACT), // 2
		.VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF) // 2
		) vospi_segment_61_i (
		.rst (!spi_nrst_pclk[1]), // input
		.clk (pclk), // input
		.start (start_segment), // input
		.exp_segment (exp_segment), // input[3:0]
		.segm0_ok (segm0_ok_r), // input
		.out_en (out_en_r), // input
		.spi_clken (spi_clken), // output
		.spi_cs (spi_cs_int), // output
		.miso (spi_miso_int), // input
		.in_busy (in_busy), // output
		.out_busy (out_busy), // output
		.segment_done (segment_done), // output reg
		.discard_segment (discard_segment), // output
		.dout (pxd), // output[15:0]
		.hact (hact), // output
		.sof (sof), // output
		.eof (eof), // output
		.crc_err (crc_err_w), // output
		.id (segment_id) // output[3:0]
		);


		cmd_deser #(
		.ADDR (SENSIO_ADDR),
		.ADDR_MASK (SENSIO_ADDR_MASK),
		@@ -401,7 +644,7 @@ module sens_lepton3 #(

		status_generate #(
		.STATUS_REG_ADDR(SENSIO_STATUS_REG),
		.PAYLOAD_BITS(26) // STATUS_PAYLOAD_BITS)
		.PAYLOAD_BITS(VOSPI_STATUS_BITS) // STATUS_PAYLOAD_BITS)
		) status_generate_sens_io_i (
		.rst (1'b0), // rst), // input
		.clk (mclk), // input
		@@ -415,7 +658,8 @@ module sens_lepton3 #(
		);


		// for debug/test alive
		// for debug/test alive kept for debug if it will be needed
		/*
		pulse_cross_clock pulse_cross_clock_vact_a_mclk_i (
		.rst (irst), // input
		.src_clk (ipclk), // input
		@@ -442,7 +686,7 @@ module sens_lepton3 #(
		.out_pulse (hact_a_mclk), // output
		.busy() // output
		);

		*/

		endmodule

sensor/sensor_channel.v

+110 −37

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