Commits · bf463e7639c01e5271ae35053f4d8337926420ba · Elphel / x393

02 Feb, 2021 1 commit
- v.202 for Boson - reset with OD · bf463e76
  Andrey Filippov authored Feb 02, 2021
  
  bf463e76
22 Jan, 2021 1 commit
- fixed hargs-boson to load correct bit file · df06bda0
  Andrey Filippov authored Jan 22, 2021
  
  df06bda0
21 Jan, 2021 1 commit
- adding boson · 6e111056
  Andrey Filippov authored Jan 21, 2021
  
  6e111056
20 Jan, 2021 1 commit
- added boson bit, generated for as if 2.5V · c4b3e834
  Andrey Filippov authored Jan 20, 2021
  
  c4b3e834
16 Jan, 2021 2 commits
- morte to the previous commit · a5738482
  Andrey Filippov authored Jan 16, 2021
  
  a5738482
- Debugging sequencer-based UART commands · 47f19c8b
  Andrey Filippov authored Jan 16, 2021
  
  47f19c8b
12 Jan, 2021 1 commit
- simulating image generation and debugging implementation · da24e724
  Andrey Filippov authored Jan 12, 2021
  
  da24e724
03 Jan, 2021 1 commit
- debugging receive uart, before adding packet separation · 98c7d0ea
  Andrey Filippov authored Jan 03, 2021
  
  98c7d0ea
01 Jan, 2021 2 commits
- more to ignore · b78d4000
  Andrey Filippov authored Jan 01, 2021
  
  b78d4000
- debugging uart transmit · a31012ed
  Andrey Filippov authored Jan 01, 2021
  
  a31012ed
26 Dec, 2020 2 commits
- removed lock file · 33c345ca
  Andrey Filippov authored Dec 26, 2020
  
  33c345ca
- working on boson implementaion, fixed old bug in python code · 043d4849
  Andrey Filippov authored Dec 26, 2020
  
  043d4849
03 Aug, 2020 1 commit
- converting to python3/cocotb · 28848f7a
  Andrey Filippov authored Aug 03, 2020
  
  28848f7a
21 May, 2019 1 commit
- fixed SFE detection in vospi mode - added pullup. v. 03930139 · ed8c5ddb
  Andrey Filippov authored May 21, 2019
  
  ed8c5ddb
07 May, 2019 1 commit
- 0x03930138 - trigger output from LWIR · b0a25b6a
  Andrey Filippov authored May 07, 2019
  
  b0a25b6a
04 May, 2019 1 commit
- adding rigger out from the sensors running i free mode · 8f05c2c2
  Andrey Filippov authored May 04, 2019
  
  8f05c2c2
03 May, 2019 1 commit
- implemented sync reset, fpga version 0x03930136 · ae33ff53
  Andrey Filippov authored May 03, 2019
  
  ae33ff53
30 Apr, 2019 2 commits
- update parallel sesnors bitstream, FPGA version 0x03930108 · 823ad682
  Andrey Filippov authored Apr 30, 2019
  
  823ad682
- Debugging vospi mode, fpga: 0x03930133 · 9b620b6b
  Andrey Filippov authored Apr 30, 2019
  
  9b620b6b
29 Apr, 2019 1 commit
- re=-arranged i2c pages for lepton sensor · 465135b4
  Andrey Filippov authored Apr 29, 2019
  
  465135b4
26 Apr, 2019 7 commits
- Merge branch 'lwir' of git.elphel.com:Elphel/x393 into lwir · 5e1584e8
  Andrey Filippov authored Apr 26, 2019
  
  5e1584e8
- implemented telemetry on/off, updated mode bits. FPGA version 0393012e · 36912bd3
  Andrey Filippov authored Apr 26, 2019
  
  36912bd3
- Merge branch 'lwir' of https://git.elphel.com/Elphel/x393 into lwir · 1434e8fb
  Oleg Dzhimiev authored Apr 26, 2019
  
  1434e8fb
- set timeout to 500 = 5sec · f3e1a3d2
  Oleg Dzhimiev authored Apr 26, 2019
  
  f3e1a3d2
- working with telemetry frame · c4db5df9
  Andrey Filippov authored Apr 26, 2019
  
  c4db5df9
- vospi debug, implemented packet synchronization by signature · 9d60666b
  Andrey Filippov authored Apr 26, 2019
  
  9d60666b
- module to synchronize · 6edd5fac
  Andrey Filippov authored Apr 26, 2019
```
 vospi packets
```
  6edd5fac
23 Apr, 2019 4 commits
- Merge branch 'lwir' of git.elphel.com:Elphel/x393 into lwir · abe4ce4b
  Andrey Filippov authored Apr 23, 2019
  
  abe4ce4b
- added debug output · 0aa9a5e2
  Andrey Filippov authored Apr 23, 2019
  
  0aa9a5e2
- reduced number of default poll tries to 3, normally 2 is enough · 9ad7c595
  Oleg Dzhimiev authored Apr 23, 2019
  
  9ad7c595
- added auto-setting of OEM bit when working with OEM/RAD modules · d0fcad21
  Oleg Dzhimiev authored Apr 23, 2019
  
  d0fcad21
22 Apr, 2019 1 commit
- i2c fucntions for FLIR Lepton 3.5 · b89b815a
  Oleg Dzhimiev authored Apr 22, 2019
  
  b89b815a
19 Apr, 2019 6 commits
- grounded unused mosi, fpga 03930121 (vospi) · 8f2f1a21
  Andrey Filippov authored Apr 19, 2019
  
  8f2f1a21
- bug fix, introduced by earlier edits · f8db9544
  Andrey Filippov authored Apr 19, 2019
  
  f8db9544
- fixed hargs-post-vospi · 9307584e
  Andrey Filippov authored Apr 19, 2019
  
  9307584e
- passed big endian in 16-bit mode from Python simulation/implementation script · a5c0516e
  Andrey Filippov authored Apr 19, 2019
  
  a5c0516e
- bitfile for lwir sensor · 05f323bf
  Andrey Filippov authored Apr 19, 2019
  
  05f323bf
- modifying for LWIR sesnor · 0be6290b
  Andrey Filippov authored Apr 19, 2019
  
  0be6290b
18 Apr, 2019 1 commit
- simulating/debugging LWIR sensor FPGA code · f35c087d
  Andrey Filippov authored Apr 18, 2019
  
  f35c087d
14 Apr, 2019 1 commit
- More development of the Verilog and Python code for LWIR sensors · 654584f3
  Andrey Filippov authored Apr 14, 2019
  
  654584f3