Commit df06bda0 authored by Andrey Filippov's avatar Andrey Filippov

fixed hargs-boson to load correct bit file

parent 6e111056
......@@ -3,8 +3,8 @@
-f /usr/local/verilog/x393_parameters.vh /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh
-l /usr/local/verilog/x393_cur_params_target.vh
-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
-c bitstream_set_path /usr/local/verilog/x393_vospi.bit
-c bitstream_set_path /usr/local/verilog/x393_boson.bit
-c setupSensorsPower "BOSON" all 0 0.1
-c measure_all "*DI"
-c setSensorClock 24.0 "2V5_LVDS"
-c setSensorClock 24.0 "1V8_LVDS"
-c set_rtc
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment