Commit 1434e8fb authored by Oleg Dzhimiev's avatar Oleg Dzhimiev

Merge branch 'lwir' of https://git.elphel.com/Elphel/x393 into lwir

parents f3e1a3d2 c4db5df9
This diff is collapsed.
......@@ -35,7 +35,18 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h03930122; // Added debug output
parameter FPGA_VERSION = 32'h0393012d; // debugging - working sync
// parameter FPGA_VERSION = 32'h0393012c; // debugging - working sync
// parameter FPGA_VERSION = 32'h0393012b; // debugging
// parameter FPGA_VERSION = 32'h0393012a; // debugging
// parameter FPGA_VERSION = 32'h03930129; // adding synchronization by discard packets
// parameter FPGA_VERSION = 32'h03930128; // output dbg_segment_stb on [7]
// parameter FPGA_VERSION = 32'h03930127; // output vsync_use, reduced sclk to 10MHz
// parameter FPGA_VERSION = 32'h03930126; // fast slew to sensor
// parameter FPGA_VERSION = 32'h03930125; // fast slew to sensor
// parameter FPGA_VERSION = 32'h03930124; // more hardware debug circuitry
// parameter FPGA_VERSION = 32'h03930123; // Implementing VSYNC/GPIO3 input
// parameter FPGA_VERSION = 32'h03930122; // Added debug output
// parameter FPGA_VERSION = 32'h03930121; // VOSPI setting MOSI to low, according to DS
// parameter FPGA_VERSION = 32'h03930120; // VOSPI
// parameter FPGA_VERSION = 32'h03930108; // parallel - in master branch
......
......@@ -559,13 +559,17 @@
parameter VOSPI_OUT_EN = 10,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 12,
parameter VOSPI_RESET_CRC = 13,
parameter VOSPI_RESET_ERR = 13,
parameter VOSPI_SPI_CLK = 14,
parameter VOSPI_SPI_CLK_BITS = 2,
parameter VOSPI_GPIO = 16,
parameter VOSPI_GPIO_BITS = 8,
parameter VOSPI_FAKE_OUT = 24, // to keep hardware
parameter VOSPI_MOSI = 25, // not used
parameter VOSPI_VSYNC = 24,
parameter VOSPI_VSYNC_BITS = 2,
parameter VOSPI_NORESYNC = 26, // disable re-sync
parameter VOSPI_NORESYNC_BITS = 2,
parameter VOSPI_DBG_SRC = 28,
parameter VOSPI_DBG_SRC_BITS = 4,
parameter VOSPI_PACKET_WORDS = 80,
parameter VOSPI_NO_INVALID = 1, // do not output invalid packets data
parameter VOSPI_PACKETS_PER_LINE = 2,
......@@ -616,6 +620,13 @@
parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_SLEW = "SLOW",
parameter integer VOSPI_DRIVE = 16, // 12, (4,8,12,16)
parameter VOSPI_IBUF_LOW_PWR = "TRUE",
parameter VOSPI_IOSTANDARD = "LVCMOS25",
parameter VOSPI_SLEW = "FAST", // "SLOW",
`ifdef use200Mhz
parameter real SENS_REFCLK_FREQUENCY = 300.0, // same as REFCLK_FREQUENCY
`else
......@@ -1017,8 +1028,8 @@
parameter CLKOUT_DIV_PCLK = 2, //480 MHz // 4, // 240 MHz
parameter CLKOUT_DIV_PCLK2X = 1, //9060 MHz // 2, // 480 MHz
`else
parameter CLKOUT_DIV_PCLK = 48, // 20 MHz
parameter CLKOUT_DIV_PCLK2X = 24, // 40 MHz
parameter CLKOUT_DIV_PCLK = 96, // 10MHz // 48, // 20 MHz
parameter CLKOUT_DIV_PCLK2X = 48, // 20 MHz // 24, // 40 MHz
`endif
`else
......
This diff is collapsed.
......@@ -1890,15 +1890,14 @@ class X393ExportC(object):
dw.append(("gpio_in", 4, 4,0, "Input from GPIO0-GPIO3, only GPIO3 may be used as segment ready"))
dw.append(("in_busy", 8, 1,0, "Frame segments are waited for or received to FIFO"))
dw.append(("out_busy", 9, 1,0, "received frame is being transferred to video memory"))
dw.append(("crc_err", 10, 1,0, "At least 1 CRC error happened since reset by command bit"))
dw.append(("fake_in", 11, 1,0, "Just to keep hardware"))
dw.append(("crc_err", 10, 1,0, "At least 1 CRC error happened since reset by the command bit"))
dw.append(("sync_err", 11, 1,0, "At least 1 synchronization error happened since reset by the command bit"))
dw.append(("fake_in", 12, 1,0, "Just to keep hardware"))
dw.append(("senspgmin", 24, 1,0, "senspgm pin state (0 means non-FPGA SFE is present)"))
dw.append(("busy", 25, 1,0, "in_busy OR out_busy"))
dw.append(("seq_num", 26, 6,0, "Sequence number"))
return dw
def _enc_status_sens_i2c(self):
dw=[]
dw.append(("i2c_fifo_dout", 0, 8,0, "I2c byte read from the device through FIFO"))
......@@ -2139,15 +2138,19 @@ class X393ExportC(object):
dw.append(("out_en", vrlg.VOSPI_OUT_EN, 1, 0, "Enable output sensor data to memory"))
dw.append(("out_en_set", vrlg.VOSPI_OUT_EN + 1, 1, 0, "Set enable sensor data to memory"))
dw.append(("out_single", vrlg.VOSPI_OUT_EN_SINGL, 1, 0, "Enable single sensor frame to memory"))
dw.append(("reset_crc", vrlg.VOSPI_RESET_CRC, 1, 0, "Reset CRC error status bit"))
dw.append(("reset_err", vrlg.VOSPI_RESET_ERR, 1, 0, "Reset CRC and synchronization error status bits"))
dw.append(("spi_clk", vrlg.VOSPI_SPI_CLK, 1, 0, "Enable continuous SPI clock (0 - only when SPI CS is active)"))
dw.append(("spi_clk_set", vrlg.VOSPI_SPI_CLK + 1, 1, 0, "When set to 1, SPI CLK enable is set to the 'spi_clk' field value"))
dw.append(("gpio0", vrlg.VOSPI_GPIO , 2, 0, "Output control for GPIO0: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
dw.append(("gpio1", vrlg.VOSPI_GPIO+2, 2, 0, "Output control for GPIO1: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
dw.append(("gpio2", vrlg.VOSPI_GPIO+4, 2, 0, "Output control for GPIO2: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
dw.append(("gpio3", vrlg.VOSPI_GPIO+6, 2, 0, "Output control for GPIO3: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
dw.append(("fake", vrlg.VOSPI_FAKE_OUT, 1, 0, "Just to keep I/O ports from optimization"))
dw.append(("mosi", vrlg.VOSPI_MOSI, 1, 0, "Just to keep I/O ports from optimization"))
dw.append(("vsync_use", vrlg.VOSPI_VSYNC, 1, 0, "Wait for the VSYNC (GPIO3). Should be enabled via i2c"))
dw.append(("vsync_use_set",vrlg.VOSPI_VSYNC+1, 1, 0, "Enable vsync_use set/reset"))
dw.append(("noresync", vrlg.VOSPI_NORESYNC, 1, 0, "Disable re-synchronization by discard packets"))
dw.append(("noresync_set", vrlg.VOSPI_NORESYNC+1, 1, 0, "Enable noresync set/reset"))
dw.append(("dbg_src", vrlg.VOSPI_DBG_SRC, 3, 0, "Hardware debug source:0-running,1-vsync_rdy[0],2-vsync_rdy[1],3-discard_segment,4-in_busy,5-out_busy,6-hact,7-sof"))
dw.append(("dbg_src_set", vrlg.VOSPI_DBG_SRC+3, 1, 0, "Enable write to dbg_src"))
return dw
def _enc_sensio_jtag(self):
......
......@@ -467,8 +467,9 @@ class X393Sensor(object):
gpio1 = None,
gpio2 = None,
gpio3 = None,
fake = None,
mosi = None):
vsync_use = None,
noresync = None,
dbg_src = None):
"""
Combine sensor I/O control parameters into a control word
@param mrst - True - activate MRST signal (low), False - deactivate MRST (high), None - no change
......@@ -484,8 +485,16 @@ class X393Sensor(object):
@param gpio1 = Output control for GPIO0: 1 - nop, 1 - set low, 2 - set high, 3 - input
@param gpio2 = Output control for GPIO0: 2 - nop, 1 - set low, 2 - set high, 3 - input
@param gpio3 = Output control for GPIO0: 3 - nop, 1 - set low, 2 - set high, 3 - input
@param fake = Do not use, just for keeping hardware portsNone,
@param mosi = Do not use, just for keeping hardware portsNone,
@param vsync_use = Wait for VSYNC (should be enabled over i2c) before reading each segment
@param noresync = Disable resynchronization by discard packets
@param dbg_src = source of the hardware debug output: 0 - dbg_running
1 - vsync_rdy[0]
2 - vsync_rdy[1]
3 - discard_segment
4 - in_busy
5 - out_busy
6 - hact
7 - sof
@return VOSPI sensor i/o control word
"""
rslt = 0
......@@ -504,7 +513,7 @@ class X393Sensor(object):
if out_single:
rslt |= 1 << vrlg.VOSPI_OUT_EN_SINGL
if reset_crc:
rslt |= 1 << vrlg.VOSPI_RESET_CRC
rslt |= 1 << vrlg.VOSPI_RESET_ERR
if not spi_clk is None:
rslt |= (2,3)[spi_clk] << vrlg.VOSPI_SPI_CLK
if not gpio0 is None:
......@@ -515,10 +524,20 @@ class X393Sensor(object):
rslt |= (gpio2 & 3) << (vrlg.VOSPI_GPIO + 4)
if not gpio3 is None:
rslt |= (gpio3 & 3) << (vrlg.VOSPI_GPIO + 6)
if fake:
rslt |= 1 << vrlg.VOSPI_FAKE_OUT
if fake:
mosi |= 1 << vrlg.VOSPI_MOSI
if not vsync_use is None:
rslt |= (2,3)[vsync_use] << vrlg.VOSPI_VSYNC
if not noresync is None:
rslt |= (2,3)[noresync] << vrlg.VOSPI_NORESYNC
if not dbg_src is None:
rslt |= ((dbg_src & (( 1 << (vrlg.VOSPI_DBG_SRC_BITS - 1)) -1 )) |
(1 << (vrlg.VOSPI_DBG_SRC_BITS - 1))) << vrlg.VOSPI_DBG_SRC
pass
# .VOSPI_DBG_SRC (VOSPI_DBG_SRC), // = 26, // source of the debug output
# .VOSPI_DBG_SRC_BITS (VOSPI_DBG_SRC_BITS), // = 4,
return rslt
......@@ -1056,8 +1075,10 @@ class X393Sensor(object):
gpio1 = None,
gpio2 = None,
gpio3 = None,
fake = None,
mosi = None):
vsync_use = None,
noresync = None,
dbg_src = None):
"""
Combine sensor I/O control parameters into a control word
@param mrst - True - activate MRST signal (low), False - deactivate MRST (high), None - no change
......@@ -1073,9 +1094,16 @@ class X393Sensor(object):
@param gpio1 = Output control for GPIO0: 1 - nop, 1 - set low, 2 - set high, 3 - input
@param gpio2 = Output control for GPIO0: 2 - nop, 1 - set low, 2 - set high, 3 - input
@param gpio3 = Output control for GPIO0: 3 - nop, 1 - set low, 2 - set high, 3 - input
@param fake = Do not use, just for keeping hardware portsNone,
@param mosi = Do not use, just for keeping hardware portsNone,
@return VOSPI sensor i/o control word
@param vsync_use = Wait for VSYNC (should be enabled over i2c) before reading each segment
@param noresync = Disable resynchronization by discard packets
@param dbg_src = source of the hardware debug output: 0 - dbg_running
1 - vsync_rdy[0]
2 - vsync_rdy[1]
3 - discard_segment
4 - in_busy
5 - out_busy
6 - hact
7 - sof
"""
try:
if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
......@@ -1094,8 +1122,9 @@ class X393Sensor(object):
gpio1 = gpio1,
gpio2 = gpio2,
gpio3 = gpio3,
fake = fake,
mosi = mosi)
vsync_use = vsync_use,
noresync = noresync,
dbg_src = dbg_src)
return
except:
pass
......@@ -1113,8 +1142,9 @@ class X393Sensor(object):
gpio1 = gpio1,
gpio2 = gpio2,
gpio3 = gpio3,
fake = fake,
mosi = mosi)
vsync_use = vsync_use,
noresync = noresync,
dbg_src = dbg_src)
reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + vrlg.SENSIO_RADDR + vrlg.SENSIO_CTRL;
self.x393_axi_tasks.write_control_register(reg_addr, data)
......
This diff is collapsed.
......@@ -155,10 +155,14 @@ module sensor_channel#(
parameter SENS_LENS_POST_SCALE = 'h6a, // 01101010
parameter SENS_LENS_POST_SCALE_MASK = 'hff,
parameter SENSIO_RADDR = 8, //'h408 .. 'h40f
parameter SENSIO_ADDR_MASK = 'h7f8,
// sens_parallel12 registers
parameter SENSIO_RADDR = 8, //'h408 .. 'h40f
parameter SENSIO_ADDR_MASK = 'h7f8,
`ifdef LWIR
parameter SENSIO_CTRL = 'h0,
parameter SENSIO_STATUS = 'h1,
`else
// sens_parallel12 registers
parameter SENSIO_CTRL = 'h0,
// SENSIO_CTRL register bits
parameter SENS_CTRL_MRST = 0, // 1: 0
parameter SENS_CTRL_ARST = 2, // 3: 2
......@@ -202,7 +206,7 @@ module sensor_channel#(
parameter SENSOR_TIMING_TO = 10, // select to 0 - sof, 1 - sol, 2 - eof, 3 eol
`endif
`endif
`endif
// 4 of 8-bit delays per register
// sensor_i2c_io command/data write registers s (relative to SENSOR_BASE_ADDR)
parameter SENSI2C_ABS_RADDR = 'h10, // 'h410..'h41f
......@@ -229,6 +233,11 @@ module sensor_channel#(
`ifdef HISPI
`elsif LWIR
parameter integer VOSPI_DRIVE = 16, // 12, (4,8,12,16)
parameter VOSPI_IBUF_LOW_PWR = "TRUE",
parameter VOSPI_IOSTANDARD = "LVCMOS25",
parameter VOSPI_SLEW = "FAST", // "SLOW",
parameter VOSPI_MRST = 0,
parameter VOSPI_MRST_BITS = 2,
parameter VOSPI_PWDN = 2,
......@@ -242,13 +251,17 @@ module sensor_channel#(
parameter VOSPI_OUT_EN = 10,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 12,
parameter VOSPI_RESET_CRC = 13,
parameter VOSPI_RESET_ERR = 13,
parameter VOSPI_SPI_CLK = 14,
parameter VOSPI_SPI_CLK_BITS = 2,
parameter VOSPI_GPIO = 16,
parameter VOSPI_GPIO_BITS = 8,
parameter VOSPI_FAKE_OUT = 24, // to keep hardware
parameter VOSPI_MOSI = 25, // not used
parameter VOSPI_VSYNC = 24,
parameter VOSPI_VSYNC_BITS = 2,
parameter VOSPI_NORESYNC = 26, // disable re-sync
parameter VOSPI_NORESYNC_BITS = 2,
parameter VOSPI_DBG_SRC = 28, // source of the debug output
parameter VOSPI_DBG_SRC_BITS = 4,
parameter VOSPI_PACKET_WORDS = 80,
parameter VOSPI_NO_INVALID = 1, // do not output invalid packets data
parameter VOSPI_PACKETS_PER_LINE = 2,
......@@ -259,18 +272,22 @@ module sensor_channel#(
parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided
parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
parameter VOSPI_MCLK_HALFDIV = 4 // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
`else
//sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4,
parameter [3:0] SENSOR_FIFO_DELAY = 5, // 7,
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4,
parameter [3:0] SENSOR_FIFO_DELAY = 5 // 7,
`endif
// start with comma!
`ifdef LWIR
,parameter SENSI2C_IOSTANDARD = "LVCMOS25"
`else
// sens_parallel12 other parameters
parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
,parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
parameter integer IDELAY_VALUE = 0,
parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE",
......@@ -316,6 +333,9 @@ module sensor_channel#(
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000 // integer 4000-40000 - SS modulation period in ns
`endif
`ifdef HISPI
,parameter HISPI_MSB_FIRST = 0,
......@@ -981,10 +1001,13 @@ module sensor_channel#(
.SENSIO_ADDR_MASK (SENSIO_ADDR_MASK),
.SENSIO_CTRL (SENSIO_CTRL),
.SENSIO_STATUS (SENSIO_STATUS),
/*
.SENSIO_JTAG (SENSIO_JTAG),
.SENSIO_WIDTH (SENSIO_WIDTH),
.SENSIO_DELAYS (SENSIO_DELAYS),
*/
.SENSIO_STATUS_REG (SENSIO_STATUS_REG),
/*
.SENS_JTAG_PGMEN (SENS_JTAG_PGMEN),
.SENS_JTAG_PROG (SENS_JTAG_PROG),
.SENS_JTAG_TCK (SENS_JTAG_TCK),
......@@ -1024,6 +1047,11 @@ module sensor_channel#(
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.STATUS_ALIVE_WIDTH (STATUS_ALIVE_WIDTH),
*/
.VOSPI_DRIVE (VOSPI_DRIVE),
.VOSPI_IBUF_LOW_PWR (VOSPI_IBUF_LOW_PWR),
.VOSPI_IOSTANDARD (VOSPI_IOSTANDARD),
.VOSPI_SLEW (VOSPI_SLEW),
.VOSPI_MRST (VOSPI_MRST), // 0,
.VOSPI_MRST_BITS (VOSPI_MRST_BITS), // 2,
.VOSPI_PWDN (VOSPI_PWDN), // 2,
......@@ -1037,13 +1065,17 @@ module sensor_channel#(
.VOSPI_OUT_EN (VOSPI_OUT_EN), // 10,
.VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2,
.VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 12,
.VOSPI_RESET_CRC (VOSPI_RESET_CRC), // 13,
.VOSPI_RESET_ERR (VOSPI_RESET_ERR), // 13,
.VOSPI_SPI_CLK (VOSPI_SPI_CLK), // 14,
.VOSPI_SPI_CLK_BITS (VOSPI_SPI_CLK_BITS), // 2,
.VOSPI_GPIO (VOSPI_GPIO), // 16,
.VOSPI_GPIO_BITS (VOSPI_GPIO_BITS), // 8,
.VOSPI_FAKE_OUT (VOSPI_FAKE_OUT), // 24, // to keep hardware
.VOSPI_MOSI (VOSPI_MOSI), // 25, // pot used
.VOSPI_VSYNC (VOSPI_VSYNC), // 24,
.VOSPI_VSYNC_BITS (VOSPI_VSYNC_BITS), // 2,
.VOSPI_NORESYNC (VOSPI_NORESYNC), // 26,
.VOSPI_NORESYNC_BITS (VOSPI_NORESYNC_BITS), // 2,
.VOSPI_DBG_SRC (VOSPI_DBG_SRC), // = 28, // source of the debug output
.VOSPI_DBG_SRC_BITS (VOSPI_DBG_SRC_BITS), // = 4,
.VOSPI_PACKET_WORDS (VOSPI_PACKET_WORDS),// 80,
.VOSPI_NO_INVALID (VOSPI_NO_INVALID), // 1,
.VOSPI_PACKETS_PER_LINE (VOSPI_PACKETS_PER_LINE), // 2,
......
This diff is collapsed.
......@@ -48,11 +48,14 @@ module vospi_packet_80#(
output spi_clken, // enable clock on spi_clk
output spi_cs, // active low
input miso, // input from the sensor
input will_sync, // discard packet detected, sync_end will follow (from resync module)
output [15:0] dout, // 16-bit data received,valid at dv and 15 cycles after
output dv, // data valid strobe
output packet_done, // packet received,
output packet_busy, // packet busy (same as spi_clken, !spi_cs)
output crc_err, // crc error, valid with packet_done
output sync_err, // synchronization error, valid with packet_done
output [15:0] id, // packet ID (0x*f** - invlaid, if packet index = 20, 4 MSb - segment (- 0 invalid)
output packet_invalid, // set early, valid with packet done
output reg id_stb // id, packet invalid are set
......@@ -66,6 +69,7 @@ module vospi_packet_80#(
reg [1:0] cs_r;
wire pre_last_w;
reg last_r;
reg [ 2:0] packet_end;
reg set_id_r;
reg set_crc_r;
......@@ -81,6 +85,11 @@ module vospi_packet_80#(
reg [15:0] id_r;
wire [15:0] dmask;
reg packet_invalid_r;
reg will_sync_d;
wire sync_end; // last bit in a packet (turn off CS/spi_clken) (from resync module)
reg sync_err_r;
assign sync_end = !will_sync && will_sync_d; // trailing edge, so will fire if disabled
assign packet_busy = cs_r[0]; // clk_en_r;
assign spi_clken = cs_r[0]; // clk_en_r;
......@@ -93,29 +102,37 @@ module vospi_packet_80#(
assign dmask = packet_header[1] ? (packet_header[0] ? 16'h0fff: 16'h0) : 16'hffff ;
assign crc_err = packet_end[2] && (crc_r != crc_w);
assign sync_err = packet_end[2] && sync_err_r;
assign dv = dv_r;
assign dout = d_r;
assign packet_invalid = packet_invalid_r;
always @ (posedge clk) begin
if (rst || packet_end[0]) cs_r[0] <= 0;
else if (start) cs_r[0] <= 1;
will_sync_d <= will_sync;
/// if (rst || packet_end[0]) cs_r[0] <= 0;
if (rst || packet_end[0] || sync_end) cs_r[0] <= 0;
else if (start) cs_r[0] <= 1;
cs_r[1] <= cs_r[0];
if (rst || !cs_r[0] || packet_end[0]) bcntr <= 0;
else bcntr <= bcntr + 1;
else bcntr <= bcntr + 1; // keep running even for sync
if (rst || !cs_r[0] || packet_end[0]) lsb_r <= 0;
else lsb_r <= pre_lsb_w;
else lsb_r <= pre_lsb_w; // generate even for sync
copy_word <= !rst && lsb_r;
if (rst || !cs_r[0] || packet_end[0]) wcntr <= 0;
else if (lsb_r) wcntr <= wcntr + 1;
else if (lsb_r) wcntr <= wcntr + 1; // keep running even for sync
if (rst || !cs_r[0] ) packet_end[1:0] <= 0;
else packet_end[1:0] <= {packet_end[0], pre_last_w};
/// else packet_end[1:0] <= {packet_end[0], pre_last_w};
else packet_end[1:0] <= {packet_end[0] | sync_end, pre_last_w & ~will_sync}; // do not generate premature if running sync
if (rst) packet_end[2] <= 0;
else packet_end[2] <= packet_end[1];
......@@ -138,10 +155,18 @@ module vospi_packet_80#(
dv_r <= set_d_r && !(packet_invalid_r && VOSPI_NO_INVALID);
if (rst || start) packet_invalid_r <= 0;
else if (set_id_r) packet_invalid_r <= (d_sr[11:8] == 4'hf);
if (rst || start) packet_invalid_r <= 0;
else if (will_sync) packet_invalid_r <= 1; // Will_sync disqualifies even started (erroneously) a good packet
else if (set_id_r) packet_invalid_r <= (d_sr[11:8] == 4'hf);
last_r <= pre_last_w;
if (rst || start) sync_err_r <= 0;
else if (sync_end && ! last_r) sync_err_r <= 1;
id_stb <= set_id_r;
if (rst || start || packet_done) packet_header <= 2'b11;
else if (copy_word) packet_header <= {packet_header[0], 1'b0};
......
/*!
* <b>Module:</b> vospi_resync
* @file vospi_resync.v
* @date 2019-04-24
* @author eyesis
*
* @brief Resynchronize vospi packets by discard packets signature
* First word starts with 0 bit, then 3 variable bits, then 0xfff
* CRC word is also 0xffff. Then ? zero words, group of 5 variable words and
* more zeros.
*
* @copyright Copyright (c) 2019 Elphel, Inc.
*
* <b>License </b>
*
* vospi_resync.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* vospi_resync.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module vospi_resync#(
parameter VOSPI_PACKET_WORDS = 80,
parameter VOSPI_RESYNC_ZEROS = 11 // number of 16-bit words of 0 to follow (14.6)
)(
input rst,
input clk,
input spi_clken, // enable clock on spi_clk
input spi_cs, // active low
input miso, // input from the sensor
// output sync_end, // last bit in a packet (turn off CS/spi_clken)
output will_sync, // discard packet detected, sync_end will follow
output [4:0] dbg_state
);
wire clken = spi_clken && !spi_cs;
reg [4:0] state;
reg [4:0] count_ones;
reg [8:0] count_zeros;
reg [10:0] count_tail;
// reg [1:0] ending;
wire [4:0] state_set;
wire [4:0] state_reset;
wire set_ending;
assign will_sync = state[4];
// assign sync_end = ending[0];
assign set_ending = state[4] && (count_tail == 0);
assign state_set[4] = state[3] && (count_zeros == 0) && !rst;
assign state_set[3] = state[2] && !miso && (count_ones[4:2] == 0) && !rst;
assign state_set[2] = miso && (state[1] || (state[3] && (count_zeros != 0))) && !rst;
assign state_set[1] = !miso && (state[0] || (state[2] && (count_ones[4:2] != 0)) ) && !rst;
assign state_set[0] = rst ||
(state[2] && miso && (count_ones[4:0] == 0)) || // too many ones
set_ending;
/*
assign state_reset = {state_set[0] | rst, // state[4]
state_set[4] | state_set[2] | rst, // state[3]
state_set[3] | state_set[0] | state_set[1] | rst, // state[2]
state_set[2] | rst, // state[1]
state_set[1]};
*/
assign state_reset = {|state_set[3:0] | rst, // state[4]
state_set[4] | |state_set[2:0] | rst, // state[3]
|state_set[4:3] | |state_set[1:0] | rst, // state[2]
|state_set[4:2] | state_set[0] | rst, // state[1]
|state_set[4:1]};
assign dbg_state = state;
always @ (posedge clk) if (clken) begin
if (state[2]) count_ones <= count_ones - 1;
else count_ones <= 5'h1e;
if (state[3]) count_zeros <= count_zeros - 1;
else count_zeros <= (VOSPI_RESYNC_ZEROS << 4) - 2; // 14 for VOSPI_RESYNC_ZEROS==1
if (state[4]) count_tail <= count_tail - 1;
else count_tail <= ((VOSPI_PACKET_WORDS - VOSPI_RESYNC_ZEROS) << 4) - 2; //
// if (rst) ending <= 0;
// else ending <= {ending[0], set_ending};
// if (rst) state <= 1;
// else state <= state_set | (state & ~state_reset);
end
always @ (posedge clk) begin
if (rst) state <= 1;
else if (clken) state <= state_set | (state & ~state_reset);
end
endmodule
This diff is collapsed.
......@@ -48,6 +48,7 @@ module simul_lwir160x120_vospi # (
parameter FRAME_PERIOD = 946969, // 26.4 fps @25 MHz
parameter SEGMENT_PERIOD = 5100, // min 05063? // 10000, // 236742, // 26.4 fps @25 MHz
parameter SEGMENTS_SEQ = 8, // 12 With ITAR
parameter SEGMENT_START = 7, // 0,
parameter FRAME_DELAY = 100, // mclk period to start first frame 1
parameter MS_PERIOD = 25 // ahould actually be 25000
......@@ -275,16 +276,26 @@ module simul_lwir160x120_vospi # (
`endif
`endif
integer i;
localparam DISCARD_GAP = 14;
initial begin
// $readmemh({`ROOTPATH,"/input_data/sensor_16.dat"},sensor_data);
$readmemh(DATA_FILE,sensor_data,0);
// reg [OUT_BITS-1:0] packet_bad [0: PACKET_WORDS-1];
packet_bad[0] = 'h0f00;
packet_bad[1] = 'h5220; // calculate and put crc?
// packet_bad[0] = 'h0f00;
// packet_bad[1] = 'h5220; // calculate and put crc?
packet_bad[0] = 'h0fff;
packet_bad[1] = 'hffff; // calculate and put crc?
for (i = 2; i < PACKET_WORDS; i = i+1) begin
packet_bad[i] = 0;
if (i == (DISCARD_GAP + 0)) packet_bad[i] = 16'h0137;
else if (i == (DISCARD_GAP + 1)) packet_bad[i] = 16'hb7c2;
else if (i == (DISCARD_GAP + 2)) packet_bad[i] = 16'ha004;
else if (i == (DISCARD_GAP + 3)) packet_bad[i] = 16'hdd9d;
else if (i == (DISCARD_GAP + 4)) packet_bad[i] = 16'h0001;
else if (i == (DISCARD_GAP + 5)) packet_bad[i] = 16'h0001;
else packet_bad[i] = 0;
end
packet_bad[1] = 'h5220; // calculate and put crc?
// packet_bad[1] = 'h5220; // calculate and put crc?
end
always @ (posedge mclk) begin
if (rst || (ms_cntr == 0)) ms_cntr <= MS_PERIOD -1;
......@@ -350,7 +361,7 @@ always @ (posedge mclk) begin
if (segment_run) packed_data[copy_wa_full] <= copy_din; // copy_d;
if (rst) segments_cntr <= 0;
if (rst) segments_cntr <= SEGMENT_START;
else if (segment_done) segments_cntr <= (segments_cntr == (SEGMENTS_SEQ - 1)) ? 0: (segments_cntr + 1);
......
......@@ -1788,26 +1788,28 @@ assign axi_grst = axi_rst_pre;
.SENS_LENS_POST_SCALE_MASK (SENS_LENS_POST_SCALE_MASK),
.SENSIO_RADDR (SENSIO_RADDR),
.SENSIO_ADDR_MASK (SENSIO_ADDR_MASK),
`ifdef LWIR
`else
.SENSIO_CTRL (SENSIO_CTRL),
.SENS_CTRL_MRST (SENS_CTRL_MRST),
.SENS_CTRL_ARST (SENS_CTRL_ARST),
.SENS_CTRL_ARO (SENS_CTRL_ARO),
.SENS_CTRL_RST_MMCM (SENS_CTRL_RST_MMCM),
`ifdef HISPI
`ifdef HISPI
.SENS_CTRL_IGNORE_EMBED (SENS_CTRL_IGNORE_EMBED),
`else
`else
.SENS_CTRL_EXT_CLK (SENS_CTRL_EXT_CLK),
`endif
`endif
.SENS_CTRL_LD_DLY (SENS_CTRL_LD_DLY),
`ifdef HISPI
`ifdef HISPI
.SENS_CTRL_GP0 (SENS_CTRL_GP0),
.SENS_CTRL_GP1 (SENS_CTRL_GP1),
`else
`else
.SENS_CTRL_QUADRANTS (SENS_CTRL_QUADRANTS),
.SENS_CTRL_ODD (SENS_CTRL_ODD),
.SENS_CTRL_QUADRANTS_WIDTH (SENS_CTRL_QUADRANTS_WIDTH),
.SENS_CTRL_QUADRANTS_EN (SENS_CTRL_QUADRANTS_EN),
`endif
`endif
.SENSIO_STATUS (SENSIO_STATUS),
.SENSIO_JTAG (SENSIO_JTAG),
.SENS_JTAG_PGMEN (SENS_JTAG_PGMEN),
......@@ -1815,10 +1817,11 @@ assign axi_grst = axi_rst_pre;
.SENS_JTAG_TCK (SENS_JTAG_TCK),
.SENS_JTAG_TMS (SENS_JTAG_TMS),
.SENS_JTAG_TDI (SENS_JTAG_TDI),
`ifndef HISPI
`ifndef HISPI
.SENSIO_WIDTH (SENSIO_WIDTH),
`endif
`endif
.SENSIO_DELAYS (SENSIO_DELAYS),
`endif
.SENSI2C_ABS_RADDR (SENSI2C_ABS_RADDR),
.SENSI2C_REL_RADDR (SENSI2C_REL_RADDR),
.SENSI2C_ADDR_MASK (SENSI2C_ADDR_MASK),
......@@ -1836,6 +1839,10 @@ assign axi_grst = axi_rst_pre;
.SENSI2C_SLEW (SENSI2C_SLEW),
`ifdef HISPI
`elsif LWIR
.VOSPI_DRIVE (VOSPI_DRIVE),
.VOSPI_IBUF_LOW_PWR (VOSPI_IBUF_LOW_PWR),
.VOSPI_IOSTANDARD (VOSPI_IOSTANDARD),
.VOSPI_SLEW (VOSPI_SLEW),
.VOSPI_MRST (VOSPI_MRST), // 0,
.VOSPI_MRST_BITS (VOSPI_MRST_BITS), // 2,
.VOSPI_PWDN (VOSPI_PWDN), // 2,
......@@ -1849,13 +1856,17 @@ assign axi_grst = axi_rst_pre;
.VOSPI_OUT_EN (VOSPI_OUT_EN), // 10,
.VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2,
.VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 12,
.VOSPI_RESET_CRC (VOSPI_RESET_CRC), // 13,
.VOSPI_RESET_ERR (VOSPI_RESET_ERR), // 13,
.VOSPI_SPI_CLK (VOSPI_SPI_CLK), // 14,
.VOSPI_SPI_CLK_BITS (VOSPI_SPI_CLK_BITS), // 2,
.VOSPI_GPIO (VOSPI_GPIO), // 16,
.VOSPI_GPIO_BITS (VOSPI_GPIO_BITS), // 8,
.VOSPI_FAKE_OUT (VOSPI_FAKE_OUT), // 24, // to keep hardware
.VOSPI_MOSI (VOSPI_MOSI), // 25, // not used
.VOSPI_VSYNC (VOSPI_VSYNC), // 24,
.VOSPI_VSYNC_BITS (VOSPI_VSYNC_BITS), // 2,
.VOSPI_NORESYNC (VOSPI_NORESYNC), // 26,
.VOSPI_NORESYNC_BITS (VOSPI_NORESYNC_BITS), // 2,
.VOSPI_DBG_SRC (VOSPI_DBG_SRC), // = 28, // source of the debug output
.VOSPI_DBG_SRC_BITS (VOSPI_DBG_SRC_BITS), // = 4,
.VOSPI_PACKET_WORDS (VOSPI_PACKET_WORDS),// 80,