Commits · bd64002a46b6b40e590e29967755f9b6b979ad12 · Elphel / x393

31 Mar, 2021 1 commit
- 103993-rev0 with DRP MMCM/PLL control · ad1c2b04
  Andrey Filippov authored 4 years ago
  
  ad1c2b04
21 Mar, 2021 1 commit
- fixing delay setup for par12 and hispi, ran for par12 · 44928b65
  Andrey Filippov authored 4 years ago
  
  44928b65
04 Mar, 2021 1 commit
- multiple updates, fpga version 0393021f · a7d6e9ea
  Andrey Filippov authored 4 years ago
  
  a7d6e9ea
13 Feb, 2021 1 commit
- fixing recover from broken frames by optional disabling of pending frame starts, other debug · 2cb5c0b4
  Andrey Filippov authored 4 years ago
  
  2cb5c0b4
08 Feb, 2021 1 commit
- got images from Boson640 · a6df0611
  Andrey Filippov authored 4 years ago
  
  a6df0611
02 Feb, 2021 1 commit
- v.202 for Boson - reset with OD · bf463e76
  Andrey Filippov authored 4 years ago
  
  bf463e76
20 Jan, 2021 1 commit
- added boson bit, generated for as if 2.5V · c4b3e834
  Andrey Filippov authored 4 years ago
  
  c4b3e834
16 Jan, 2021 1 commit
- Debugging sequencer-based UART commands · 47f19c8b
  Andrey Filippov authored 4 years ago
  
  47f19c8b
12 Jan, 2021 1 commit
- simulating image generation and debugging implementation · da24e724
  Andrey Filippov authored 4 years ago
  
  da24e724
03 Jan, 2021 1 commit
- debugging receive uart, before adding packet separation · 98c7d0ea
  Andrey Filippov authored 4 years ago
  
  98c7d0ea
01 Jan, 2021 1 commit
- debugging uart transmit · a31012ed
  Andrey Filippov authored 4 years ago
  
  a31012ed
26 Dec, 2020 1 commit
- working on boson implementaion, fixed old bug in python code · 043d4849
  Andrey Filippov authored 4 years ago
  
  043d4849
21 May, 2019 1 commit
- fixed SFE detection in vospi mode - added pullup. v. 03930139 · ed8c5ddb
  Andrey Filippov authored 5 years ago
  
  ed8c5ddb
04 May, 2019 1 commit
- adding rigger out from the sensors running i free mode · 8f05c2c2
  Andrey Filippov authored 5 years ago
  
  8f05c2c2
03 May, 2019 1 commit
- implemented sync reset, fpga version 0x03930136 · ae33ff53
  Andrey Filippov authored 5 years ago
  
  ae33ff53
30 Apr, 2019 1 commit
- Debugging vospi mode, fpga: 0x03930133 · 9b620b6b
  Andrey Filippov authored 5 years ago
  
  9b620b6b
26 Apr, 2019 4 commits
- implemented telemetry on/off, updated mode bits. FPGA version 0393012e · 36912bd3
  Andrey Filippov authored 5 years ago
  
  36912bd3
- working with telemetry frame · c4db5df9
  Andrey Filippov authored 5 years ago
  
  c4db5df9
- vospi debug, implemented packet synchronization by signature · 9d60666b
  Andrey Filippov authored 5 years ago
  
  9d60666b
- module to synchronize · 6edd5fac
  Andrey Filippov authored 5 years ago
```
 vospi packets
```
  6edd5fac
23 Apr, 2019 1 commit
- added debug output · 0aa9a5e2
  Andrey Filippov authored 5 years ago
  
  0aa9a5e2
19 Apr, 2019 2 commits
- grounded unused mosi, fpga 03930121 (vospi) · 8f2f1a21
  Andrey Filippov authored 5 years ago
  
  8f2f1a21
- modifying for LWIR sesnor · 0be6290b
  Andrey Filippov authored 5 years ago
  
  0be6290b
18 Apr, 2019 1 commit
- simulating/debugging LWIR sensor FPGA code · f35c087d
  Andrey Filippov authored 5 years ago
  
  f35c087d
12 Apr, 2019 1 commit
- more code for LWIR sensor · 37190574
  Andrey Filippov authored 5 years ago
  
  37190574
11 Apr, 2019 1 commit
- commands and status for LWIR/VOSPI, exported to C · 691579c0
  Andrey Filippov authored 5 years ago
  
  691579c0
10 Apr, 2019 3 commits
- cosmetic · b28b105f
  Andrey Filippov authored 5 years ago
  
  b28b105f
- connecting LWIR sensors to FPGA code · 4714de19
  Andrey Filippov authored 5 years ago
  
  4714de19
- New modules for LWIR sensor · eb7ba9a4
  Andrey Filippov authored 5 years ago
  
  eb7ba9a4
25 Mar, 2019 2 commits
- fixed initialization (multiframe), added related debug waveforms · bf8f63c5
  Andrey Filippov authored 6 years ago
  
  bf8f63c5
- fixed initialization (multiframe), added related debug waveforms · 955c964c
  Andrey Filippov authored 6 years ago
  
  955c964c
05 Apr, 2018 1 commit
- added inverted trigger for GPI1 (GPI0-still active low) · 6b373aa8
  Andrey Filippov authored 7 years ago
  
  6b373aa8
16 Mar, 2018 2 commits
- fixed timing measurement with the same start/end signal. v.03930102 · 0fc224f6
  Andrey Filippov authored 7 years ago
  
  0fc224f6
- Added measurement of HISPI cycles between SOF, EOF, SOL, EOL. Version · 722e3aca
  Andrey Filippov authored 7 years ago
```
03930101
```
  722e3aca
01 Mar, 2018 1 commit
- hispi v03930100, 1704, added SOF mask to disable while setting up · 5a9a6342
  Andrey Filippov authored 7 years ago
```
interface
```
  5a9a6342
21 Feb, 2018 1 commit
- FPGA version 039300fd (hispi), changed lanes alignment report mode · 2be629f5
  Andrey Filippov authored 7 years ago
  
  2be629f5
16 Feb, 2018 1 commit
- added skip lines, diff lanes phase adjust, bitstream fc · 07e41034
  Andrey Filippov authored 7 years ago
  
  07e41034
12 Feb, 2018 1 commit
- HISPI: added per-lane line-sync monitoring, TRIG as programmable option · 429b228d
  Andrey Filippov authored 7 years ago
```
for GP0 and GP1
```
  429b228d
07 Feb, 2018 1 commit
- Increased latency in lens_flat393 to fix timing for hispi, generated · c4bd1f1f
  Andrey Filippov authored 7 years ago
```
parallel 039300f4 and hispi 039300f9 bitstreams
```
  c4bd1f1f
04 Feb, 2018 1 commit
- debugging upgrade from 15.3 to 17.4 · dadbda68
  Andrey Filippov authored 7 years ago
  
  dadbda68