Commits · c4b3e8342ee7275e0aab0061724c8dc80728daff · Elphel / x393

18 Apr, 2019 1 commit
- simulating/debugging LWIR sensor FPGA code · f35c087d
  Andrey Filippov authored 5 years ago
  
  f35c087d
14 Apr, 2019 1 commit
- More development of the Verilog and Python code for LWIR sensors · 654584f3
  Andrey Filippov authored 5 years ago
  
  654584f3
28 Mar, 2019 1 commit
- Generated first bitstream with raw mode bypassing compressor · fb273d85
  Andrey Filippov authored 6 years ago
  
  fb273d85
27 Mar, 2019 1 commit
- Simulating/debugging raw mode · aeb5b749
  Andrey Filippov authored 6 years ago
  
  aeb5b749
24 Mar, 2019 4 commits
- Introducing new parameters and other changes to implement raw data out. · d30c9b6a
  Andrey Filippov authored 6 years ago
  
  d30c9b6a
- Compressor bypass for raw (uncompressed) data · b482a8ea
  Andrey Filippov authored 6 years ago
  
  b482a8ea
- stuffer with alternative input for raw (uncompressed) data · 596bdb62
  Andrey Filippov authored 6 years ago
  
  596bdb62
- stuffer/trailer generator with alternative input for raw data · b8430129
  Andrey Filippov authored 6 years ago
  
  b8430129
19 Mar, 2019 1 commit
- started modifications for tiff images and lwir sensors · 58ed96d6
  Andrey Filippov authored 6 years ago
  
  58ed96d6
04 Feb, 2018 1 commit
- debugging upgrade from 15.3 to 17.4 · dadbda68
  Andrey Filippov authored 7 years ago
  
  dadbda68
17 Nov, 2016 1 commit
- corrected memsensor/memcompressor line comparison · 0ad0b4a8
  Andrey Filippov authored 8 years ago
  
  0ad0b4a8
14 Nov, 2016 1 commit
- added more simulation images, more fixing of JPEG tail · 87900556
  Andrey Filippov authored 8 years ago
  
  87900556
11 Nov, 2016 1 commit
- more work on JPEG tail, version 0x039300ca · a17b36ec
  Andrey Filippov authored 8 years ago
  
  a17b36ec
10 Nov, 2016 2 commits
- more fixing jpeg tail · 4b42ed42
  Andrey Filippov authored 8 years ago
  
  4b42ed42
- version c8, trying to fix 'premature end...' in JPEG data · bd5fb565
  Andrey Filippov authored 8 years ago
  
  bd5fb565
07 Sep, 2016 1 commit
- synchromized molre frame parameter transitions · 9a7406b4
  Andrey Filippov authored 8 years ago
  
  9a7406b4
06 Sep, 2016 1 commit
- channels/compressor synchronization · 4bb4f227
  Andrey Filippov authored 8 years ago
  
  4bb4f227
04 Sep, 2016 1 commit
- working on memory channels synchronization · 51d9d5ad
  Andrey Filippov authored 8 years ago
  
  51d9d5ad
18 Jul, 2016 1 commit
- bug fixrd in DCT and other places · 6ed7aef1
  Andrey Filippov authored 8 years ago
  
  6ed7aef1
17 Jun, 2016 1 commit
- minor formatting · 74d3a555
  Andrey Filippov authored 8 years ago
  
  74d3a555
13 Jun, 2016 1 commit
- Switched to new implementation of 8x8 DCT, generated documentation · 530030f6
  Andrey Filippov authored 8 years ago
  
  530030f6
12 Jun, 2016 1 commit
- working on DSP-based 8x8 DCT implementing Chen algorithm · 2d4c00bf
  Andrey Filippov authored 8 years ago
  
  2d4c00bf
09 Jun, 2016 1 commit
- removed unused file · 116c9ce2
  Andrey Filippov authored 8 years ago
  
  116c9ce2
05 Jun, 2016 1 commit
- Modified headers to work with doxverilog2.5/doxygen1.7.0 · 00e7a575
  Andrey Filippov authored 8 years ago
  
  00e7a575
02 Jun, 2016 1 commit
- typo · a0f7305c
  Andrey Filippov authored 8 years ago
  
  a0f7305c
18 May, 2016 1 commit
- suppressed last warnings of unused signals · 6b0a6bd2
  Andrey Filippov authored 8 years ago
  
  6b0a6bd2
07 May, 2016 1 commit
- added interrupts simulation, fixing circbuf pointers rollover bug · 880f7615
  Andrey Filippov authored 8 years ago
  
  880f7615
05 May, 2016 2 commits
- changed user name to full name · 374d7837
  Andrey Filippov authored 8 years ago
  
  374d7837
- multiple changes, synchronizing simulation with hardware · 82e11ec7
  Andrey Filippov authored 8 years ago
  
  82e11ec7
16 Mar, 2016 2 commits
- added x393_sata project · a06aacce
  Andrey Filippov authored 9 years ago
  
  a06aacce
- fixed axi simulation modules, added IRQ support · 500cf616
  Andrey Filippov authored 9 years ago
  
  500cf616
15 Nov, 2015 1 commit
- debugging JP4 mode, got correct JP4 image · 78d2e067
  Andrey Filippov authored 9 years ago
  
  78d2e067
11 Nov, 2015 1 commit
- got first images from mt9f002 · 81da483f
  Andrey Filippov authored 9 years ago
  
  81da483f
08 Nov, 2015 3 commits
- Typo in file headers · 72d1c082
  Andrey Filippov authored 9 years ago
  
  72d1c082
- More file headers editing · 691ae8a4
  Andrey Filippov authored 9 years ago
  
  691ae8a4
- added 'Additional permission under GNU GPL version 3 section 7' to each file header · 1392ef16
  Andrey Filippov authored 9 years ago
  
  1392ef16
06 Nov, 2015 1 commit
- just added TODO for thre future · 9c457ded
  Andrey Filippov authored 9 years ago
  
  9c457ded
03 Nov, 2015 1 commit
- testing and simulating, improving timing · db53f38f
  Andrey Filippov authored 9 years ago
  
  db53f38f
01 Nov, 2015 2 commits
- Made several modifications to fix all timing violations to run compressor... · 4ca48f7b
  Andrey Filippov authored 9 years ago
```
Made several modifications to fix all timing violations to run compressor @250MHz - 1.0 Gigapixel/sec in JP4 mode
```
  4ca48f7b
- Added modified xdct393 module to increase clock frequency · ba35eb7a
  Andrey Filippov authored 9 years ago
  
  ba35eb7a