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Elphel
x393
Commits
00e7a575
Commit
00e7a575
authored
Jun 05, 2016
by
Andrey Filippov
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Plain Diff
Modified headers to work with doxverilog2.5/doxygen1.7.0
parent
1df762e6
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274 changed files
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3607 additions
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2149 deletions
+3607
-2149
.gitignore
.gitignore
+5
-1
axibram_read.v
axi/axibram_read.v
+14
-10
axibram_write.v
axi/axibram_write.v
+12
-7
cmprs_afi_mux.v
axi/cmprs_afi_mux.v
+12
-7
cmprs_afi_mux_ptr.v
axi/cmprs_afi_mux_ptr.v
+12
-7
cmprs_afi_mux_ptr_wresp.v
axi/cmprs_afi_mux_ptr_wresp.v
+12
-7
cmprs_afi_mux_status.v
axi/cmprs_afi_mux_status.v
+12
-7
histogram_saxi.v
axi/histogram_saxi.v
+12
-7
macros393.v
axi/macros393.v
+0
-51
membridge.v
axi/membridge.v
+12
-7
mul_saxi_wr_chn.v
axi/mul_saxi_wr_chn.v
+12
-7
mult_saxi_wr.v
axi/mult_saxi_wr.v
+13
-8
mult_saxi_wr_inbuf.v
axi/mult_saxi_wr_inbuf.v
+12
-7
mult_saxi_wr_pointers.v
axi/mult_saxi_wr_pointers.v
+12
-7
cmd_mux.v
cmd_mux.v
+12
-7
cmd_readback.v
cmd_readback.v
+12
-7
bit_stuffer_27_32.v
compressor_jp/bit_stuffer_27_32.v
+12
-7
bit_stuffer_escape.v
compressor_jp/bit_stuffer_escape.v
+12
-7
bit_stuffer_metadata.v
compressor_jp/bit_stuffer_metadata.v
+14
-7
cmprs_buf_average.v
compressor_jp/cmprs_buf_average.v
+12
-7
cmprs_cmd_decode.v
compressor_jp/cmprs_cmd_decode.v
+12
-7
cmprs_frame_sync.v
compressor_jp/cmprs_frame_sync.v
+12
-7
cmprs_macroblock_buf_iface.v
compressor_jp/cmprs_macroblock_buf_iface.v
+12
-7
cmprs_out_fifo.v
compressor_jp/cmprs_out_fifo.v
+12
-7
cmprs_out_fifo32.v
compressor_jp/cmprs_out_fifo32.v
+12
-7
cmprs_pixel_buf_iface.v
compressor_jp/cmprs_pixel_buf_iface.v
+12
-7
cmprs_status.v
compressor_jp/cmprs_status.v
+12
-7
cmprs_tile_mode2_decode.v
compressor_jp/cmprs_tile_mode2_decode.v
+12
-7
cmprs_tile_mode_decode.v
compressor_jp/cmprs_tile_mode_decode.v
+12
-7
compressor393.v
compressor_jp/compressor393.v
+12
-7
csconvert.v
compressor_jp/csconvert.v
+12
-7
csconvert18a.v
compressor_jp/csconvert18a.v
+38
-27
csconvert_jp4.v
compressor_jp/csconvert_jp4.v
+12
-7
csconvert_jp4diff.v
compressor_jp/csconvert_jp4diff.v
+12
-7
csconvert_mono.v
compressor_jp/csconvert_mono.v
+12
-7
dcc_sync393.v
compressor_jp/dcc_sync393.v
+12
-7
encoderDCAC393.v
compressor_jp/encoderDCAC393.v
+37
-25
focus_sharp393.v
compressor_jp/focus_sharp393.v
+39
-27
huff_fifo393.v
compressor_jp/huff_fifo393.v
+38
-26
huffman393.v
compressor_jp/huffman393.v
+39
-26
huffman_merge_code_literal.v
compressor_jp/huffman_merge_code_literal.v
+12
-7
huffman_snglclk.v
compressor_jp/huffman_snglclk.v
+38
-26
huffman_stuffer_meta.v
compressor_jp/huffman_stuffer_meta.v
+19
-8
jp_channel.v
compressor_jp/jp_channel.v
+12
-7
quantizer393.v
compressor_jp/quantizer393.v
+38
-26
stuffer393.v
compressor_jp/stuffer393.v
+40
-26
varlen_encode393.v
compressor_jp/varlen_encode393.v
+43
-31
varlen_encode_snglclk.v
compressor_jp/varlen_encode_snglclk.v
+38
-26
fpga_version.vh
fpga_version.vh
+11
-7
tasks_tests_memory.vh
includes/tasks_tests_memory.vh
+11
-7
x393_cur_params_target.vh
includes/x393_cur_params_target.vh
+13
-8
x393_localparams.vh
includes/x393_localparams.vh
+11
-7
x393_mcontr_encode_cmd.vh
includes/x393_mcontr_encode_cmd.vh
+11
-7
x393_parameters.vh
includes/x393_parameters.vh
+11
-7
x393_simulation_parameters.vh
includes/x393_simulation_parameters.vh
+11
-7
x393_tasks01.vh
includes/x393_tasks01.vh
+11
-7
x393_tasks_afi.vh
includes/x393_tasks_afi.vh
+11
-7
x393_tasks_mcntrl_buffers.vh
includes/x393_tasks_mcntrl_buffers.vh
+11
-7
x393_tasks_mcntrl_en_dis_priority.vh
includes/x393_tasks_mcntrl_en_dis_priority.vh
+11
-7
x393_tasks_mcntrl_timing.vh
includes/x393_tasks_mcntrl_timing.vh
+11
-7
x393_tasks_pio_sequences.vh
includes/x393_tasks_pio_sequences.vh
+11
-7
x393_tasks_ps_pio.vh
includes/x393_tasks_ps_pio.vh
+12
-8
x393_tasks_status.vh
includes/x393_tasks_status.vh
+11
-7
buf_xclk_mclk16_393.v
logger/buf_xclk_mclk16_393.v
+12
-7
event_logger.v
logger/event_logger.v
+12
-7
imu_exttime393.v
logger/imu_exttime393.v
+12
-7
imu_message393.v
logger/imu_message393.v
+17
-14
imu_spi393.v
logger/imu_spi393.v
+12
-7
imu_timestamps393.v
logger/imu_timestamps393.v
+12
-7
logger_arbiter393.v
logger/logger_arbiter393.v
+12
-7
nmea_decoder393.v
logger/nmea_decoder393.v
+12
-7
rs232_rcv393.v
logger/rs232_rcv393.v
+12
-7
cmd_encod_4mux.v
memctrl/cmd_encod_4mux.v
+12
-7
cmd_encod_linear_mux.v
memctrl/cmd_encod_linear_mux.v
+12
-7
cmd_encod_linear_rd.v
memctrl/cmd_encod_linear_rd.v
+12
-7
cmd_encod_linear_rw.v
memctrl/cmd_encod_linear_rw.v
+12
-7
cmd_encod_linear_wr.v
memctrl/cmd_encod_linear_wr.v
+12
-7
cmd_encod_tiled_32_rd.v
memctrl/cmd_encod_tiled_32_rd.v
+12
-7
cmd_encod_tiled_32_rw.v
memctrl/cmd_encod_tiled_32_rw.v
+12
-7
cmd_encod_tiled_32_wr.v
memctrl/cmd_encod_tiled_32_wr.v
+12
-7
cmd_encod_tiled_mux.v
memctrl/cmd_encod_tiled_mux.v
+12
-7
cmd_encod_tiled_rd.v
memctrl/cmd_encod_tiled_rd.v
+17
-9
cmd_encod_tiled_rw.v
memctrl/cmd_encod_tiled_rw.v
+12
-7
cmd_encod_tiled_wr.v
memctrl/cmd_encod_tiled_wr.v
+17
-9
ddr_refresh.v
memctrl/ddr_refresh.v
+12
-7
mcntrl393.v
memctrl/mcntrl393.v
+12
-7
mcntrl393_test01.v
memctrl/mcntrl393_test01.v
+12
-7
mcntrl_1kx32r.v
memctrl/mcntrl_1kx32r.v
+12
-7
mcntrl_1kx32w.v
memctrl/mcntrl_1kx32w.v
+12
-7
mcntrl_buf_rd.v
memctrl/mcntrl_buf_rd.v
+12
-7
mcntrl_buf_wr.v
memctrl/mcntrl_buf_wr.v
+12
-7
mcntrl_linear_rw.v
memctrl/mcntrl_linear_rw.v
+12
-7
mcntrl_ps_pio.v
memctrl/mcntrl_ps_pio.v
+12
-7
mcntrl_tiled_rw.v
memctrl/mcntrl_tiled_rw.v
+12
-7
memctrl16.v
memctrl/memctrl16.v
+12
-7
byte_lane.v
memctrl/phy/byte_lane.v
+12
-7
cmd_addr.v
memctrl/phy/cmd_addr.v
+12
-7
cmda_single.v
memctrl/phy/cmda_single.v
+12
-7
dm_single.v
memctrl/phy/dm_single.v
+12
-7
dq_single.v
memctrl/phy/dq_single.v
+12
-7
dqs_single.v
memctrl/phy/dqs_single.v
+12
-7
dqs_single_nofine.v
memctrl/phy/dqs_single_nofine.v
+12
-7
mcontr_sequencer.v
memctrl/phy/mcontr_sequencer.v
+12
-7
phy_cmd.v
memctrl/phy/phy_cmd.v
+12
-7
phy_top.v
memctrl/phy/phy_top.v
+12
-7
scheduler16.v
memctrl/scheduler16.v
+12
-7
x393_export_c.py
py393/x393_export_c.py
+4
-4
lens_flat393.v
sensor/lens_flat393.v
+12
-7
pxd_clock.v
sensor/pxd_clock.v
+12
-7
pxd_single.v
sensor/pxd_single.v
+12
-7
sens_10398.v
sensor/sens_10398.v
+12
-7
sens_gamma.v
sensor/sens_gamma.v
+12
-7
sens_hispi12l4.v
sensor/sens_hispi12l4.v
+12
-7
sens_hispi_clock.v
sensor/sens_hispi_clock.v
+12
-7
sens_hispi_din.v
sensor/sens_hispi_din.v
+12
-7
sens_hispi_fifo.v
sensor/sens_hispi_fifo.v
+12
-7
sens_hispi_lane.v
sensor/sens_hispi_lane.v
+12
-7
sens_histogram.v
sensor/sens_histogram.v
+12
-7
sens_histogram_mux.v
sensor/sens_histogram_mux.v
+12
-7
sens_histogram_snglclk.v
sensor/sens_histogram_snglclk.v
+12
-7
sens_parallel12.v
sensor/sens_parallel12.v
+12
-7
sens_sync.v
sensor/sens_sync.v
+12
-7
sensor_channel.v
sensor/sensor_channel.v
+12
-7
sensor_fifo.v
sensor/sensor_fifo.v
+12
-7
sensor_i2c.v
sensor/sensor_i2c.v
+12
-7
sensor_i2c_io.v
sensor/sensor_i2c_io.v
+12
-7
sensor_i2c_prot.v
sensor/sensor_i2c_prot.v
+15
-10
sensor_i2c_scl_sda.v
sensor/sensor_i2c_scl_sda.v
+12
-7
sensor_membuf.v
sensor/sensor_membuf.v
+12
-7
sensors393.v
sensor/sensors393.v
+12
-7
par12_hispi_psp4l.v
simulation_modules/par12_hispi_psp4l.v
+12
-7
sim_clk_div.v
simulation_modules/sim_clk_div.v
+12
-7
sim_frac_clk_delay.v
simulation_modules/sim_frac_clk_delay.v
+12
-7
sim_soc_interrupts.v
simulation_modules/sim_soc_interrupts.v
+12
-7
simul_axi_fifo_out.v
simulation_modules/simul_axi_fifo_out.v
+39
-7
simul_axi_hp_rd.v
simulation_modules/simul_axi_hp_rd.v
+12
-7
simul_axi_hp_wr.v
simulation_modules/simul_axi_hp_wr.v
+12
-7
simul_axi_master_rdaddr.v
simulation_modules/simul_axi_master_rdaddr.v
+12
-7
simul_axi_master_wdata.v
simulation_modules/simul_axi_master_wdata.v
+12
-7
simul_axi_master_wraddr.v
simulation_modules/simul_axi_master_wraddr.v
+12
-7
simul_axi_read.v
simulation_modules/simul_axi_read.v
+12
-7
simul_axi_slow_ready.v
simulation_modules/simul_axi_slow_ready.v
+12
-7
simul_clk.v
simulation_modules/simul_clk.v
+12
-7
simul_clk_div_mult.v
simulation_modules/simul_clk_div_mult.v
+12
-7
simul_clk_mult.v
simulation_modules/simul_clk_mult.v
+12
-7
simul_clk_mult_div.v
simulation_modules/simul_clk_mult_div.v
+12
-7
simul_fifo.v
simulation_modules/simul_fifo.v
+12
-7
simul_saxi_gp_wr.v
simulation_modules/simul_saxi_gp_wr.v
+12
-7
simul_sensor12bits.v
simulation_modules/simul_sensor12bits.v
+12
-7
status_read.v
status_read.v
+12
-7
system_defines.vh
system_defines.vh
+13
-7
camsync393.v
timing/camsync393.v
+12
-7
rtc393.v
timing/rtc393.v
+12
-7
timestamp_fifo.v
timing/timestamp_fifo.v
+14
-8
timestamp_snapshot.v
timing/timestamp_snapshot.v
+12
-7
timestamp_to_parallel.v
timing/timestamp_to_parallel.v
+12
-7
timestamp_to_serial.v
timing/timestamp_to_serial.v
+12
-7
timing393.v
timing/timing393.v
+12
-7
IBUFG.v
unisims_extra/IBUFG.v
+12
-7
IBUFGDS.v
unisims_extra/IBUFGDS.v
+12
-7
axi_hp_clk.v
util_modules/axi_hp_clk.v
+12
-7
clk_to_clk2x.v
util_modules/clk_to_clk2x.v
+12
-7
clocks393.v
util_modules/clocks393.v
+12
-7
clocks393m.v
util_modules/clocks393m.v
+13
-8
cmd_deser.v
util_modules/cmd_deser.v
+12
-7
cmd_frame_sequencer.v
util_modules/cmd_frame_sequencer.v
+12
-7
cmd_seq_mux.v
util_modules/cmd_seq_mux.v
+12
-7
debug_master.v
util_modules/debug_master.v
+12
-7
debug_slave.v
util_modules/debug_slave.v
+12
-7
dly01_16.v
util_modules/dly01_16.v
+12
-7
dly_16.v
util_modules/dly_16.v
+12
-7
dual_clock_source.v
util_modules/dual_clock_source.v
+12
-7
elastic_cross_clock.v
util_modules/elastic_cross_clock.v
+13
-7
fifo_1cycle.v
util_modules/fifo_1cycle.v
+14
-8
fifo_2regs.v
util_modules/fifo_2regs.v
+12
-7
fifo_cross_clocks.v
util_modules/fifo_cross_clocks.v
+12
-7
fifo_same_clock.v
util_modules/fifo_same_clock.v
+12
-7
fifo_same_clock_fill.v
util_modules/fifo_same_clock_fill.v
+12
-7
fifo_sameclock_control.v
util_modules/fifo_sameclock_control.v
+12
-7
frame_num_sync.v
util_modules/frame_num_sync.v
+12
-7
gpio393.v
util_modules/gpio393.v
+13
-8
index_max_16.v
util_modules/index_max_16.v
+12
-7
level_cross_clocks.v
util_modules/level_cross_clocks.v
+12
-7
masked_max_reg.v
util_modules/masked_max_reg.v
+12
-7
mcont_common_chnbuf_reg.v
util_modules/mcont_common_chnbuf_reg.v
+12
-7
mcont_from_chnbuf_reg.v
util_modules/mcont_from_chnbuf_reg.v
+12
-7
mcont_to_chnbuf_reg.v
util_modules/mcont_to_chnbuf_reg.v
+12
-7
multipulse_cross_clock.v
util_modules/multipulse_cross_clock.v
+13
-7
pri1hot16.v
util_modules/pri1hot16.v
+12
-7
pulse_cross_clock.v
util_modules/pulse_cross_clock.v
+12
-7
resync_data.v
util_modules/resync_data.v
+12
-7
round_robin.v
util_modules/round_robin.v
+12
-7
status_generate.v
util_modules/status_generate.v
+13
-8
status_router16.v
util_modules/status_router16.v
+12
-7
status_router2.v
util_modules/status_router2.v
+12
-7
status_router4.v
util_modules/status_router4.v
+12
-7
status_router8.v
util_modules/status_router8.v
+12
-7
sync_resets.v
util_modules/sync_resets.v
+12
-7
table_ad_receive.v
util_modules/table_ad_receive.v
+12
-7
table_ad_transmit.v
util_modules/table_ad_transmit.v
+12
-7
dci_reset.v
wrap/dci_reset.v
+12
-7
ddr3_wrap.v
wrap/ddr3_wrap.v
+12
-7
ibuf_ibufg.v
wrap/ibuf_ibufg.v
+12
-7
ibufds_ibufgds.v
wrap/ibufds_ibufgds.v
+12
-7
ibufg.v
wrap/ibufg.v
+12
-7
ibufgds.v
wrap/ibufgds.v
+12
-7
idelay_ctrl.v
wrap/idelay_ctrl.v
+12
-7
idelay_fine_pipe.v
wrap/idelay_fine_pipe.v
+12
-7
idelay_nofine.v
wrap/idelay_nofine.v
+13
-7
iobuf.v
wrap/iobuf.v
+12
-7
iserdes_mem.v
wrap/iserdes_mem.v
+12
-7
latch_g_ce.v
wrap/latch_g_ce.v
+12
-7
mmcm_adv.v
wrap/mmcm_adv.v
+12
-7
mmcm_phase_cntr.v
wrap/mmcm_phase_cntr.v
+12
-7
mpullup.v
wrap/mpullup.v
+12
-7
obuf.v
wrap/obuf.v
+12
-7
obufds.v
wrap/obufds.v
+12
-7
oddr.v
wrap/oddr.v
+12
-7
oddr_ds.v
wrap/oddr_ds.v
+12
-7
oddr_ss.v
wrap/oddr_ss.v
+12
-7
odelay_fine_pipe.v
wrap/odelay_fine_pipe.v
+12
-7
odelay_pipe.v
wrap/odelay_pipe.v
+12
-7
oserdes_mem.v
wrap/oserdes_mem.v
+12
-7
pll_base.v
wrap/pll_base.v
+12
-7
ram18_var_w_var_r.v
wrap/ram18_var_w_var_r.v
+12
-7
ram18p_var_w_var_r.v
wrap/ram18p_var_w_var_r.v
+10
-4
ram18t_var_w_var_r.v
wrap/ram18t_var_w_var_r.v
+12
-7
ram18tp_var_w_var_r.v
wrap/ram18tp_var_w_var_r.v
+12
-7
ram_1kx32_1kx32.v
wrap/ram_1kx32_1kx32.v
+12
-3
ram_1kx32w_512x64r.v
wrap/ram_1kx32w_512x64r.v
+12
-3
ram_512x64w_1kx32r.v
wrap/ram_512x64w_1kx32r.v
+12
-3
ram_var_w_var_r.v
wrap/ram_var_w_var_r.v
+12
-4
ramp_var_w_var_r.v
wrap/ramp_var_w_var_r.v
+12
-4
ramt_var_w_var_r.v
wrap/ramt_var_w_var_r.v
+12
-7
ramt_var_wb_var_r.v
wrap/ramt_var_wb_var_r.v
+12
-7
ramtp_var_w_var_r.v
wrap/ramtp_var_w_var_r.v
+12
-7
select_clk_buf.v
wrap/select_clk_buf.v
+12
-7
x393.v
x393.v
+12
-7
ahci_ctrl_stat.v
x393_sata/ahci/ahci_ctrl_stat.v
+12
-7
ahci_dma.v
x393_sata/ahci/ahci_dma.v
+12
-7
ahci_dma_rd_fifo.v
x393_sata/ahci/ahci_dma_rd_fifo.v
+12
-7
ahci_dma_rd_stuff.v
x393_sata/ahci/ahci_dma_rd_stuff.v
+12
-7
ahci_dma_wr_fifo.v
x393_sata/ahci/ahci_dma_wr_fifo.v
+12
-7
ahci_fis_receive.v
x393_sata/ahci/ahci_fis_receive.v
+12
-7
ahci_fis_transmit.v
x393_sata/ahci/ahci_fis_transmit.v
+12
-7
ahci_fsm.v
x393_sata/ahci/ahci_fsm.v
+12
-7
ahci_sata_layers.v
x393_sata/ahci/ahci_sata_layers.v
+12
-7
ahci_top.v
x393_sata/ahci/ahci_top.v
+12
-7
axi_ahci_regs.v
x393_sata/ahci/axi_ahci_regs.v
+12
-7
axi_hp_abort.v
x393_sata/ahci/axi_hp_abort.v
+12
-7
freq_meter.v
x393_sata/ahci/freq_meter.v
+12
-7
sata_ahci_top.v
x393_sata/ahci/sata_ahci_top.v
+12
-7
oob_dev.v
x393_sata/device/oob_dev.v
+14
-9
sata_phy_dev.v
x393_sata/device/sata_phy_dev.v
+14
-9
action_decoder.v
x393_sata/generated/action_decoder.v
+8
-6
condition_mux.v
x393_sata/generated/condition_mux.v
+8
-6
crc.v
x393_sata/host/crc.v
+12
-7
drp_other_registers.v
x393_sata/host/drp_other_registers.v
+12
-7
elastic1632.v
x393_sata/host/elastic1632.v
+12
-7
gtx_10x8dec.v
x393_sata/host/gtx_10x8dec.v
+12
-7
gtx_8x10enc.v
x393_sata/host/gtx_8x10enc.v
+12
-7
gtx_comma_align.v
x393_sata/host/gtx_comma_align.v
+12
-7
gtx_elastic.v
x393_sata/host/gtx_elastic.v
+12
-7
gtx_wrap.v
x393_sata/host/gtx_wrap.v
+12
-7
link.v
x393_sata/host/link.v
+12
-7
oob.v
x393_sata/host/oob.v
+12
-7
oob_ctrl.v
x393_sata/host/oob_ctrl.v
+12
-7
sata_phy.v
x393_sata/host/sata_phy.v
+12
-7
scrambler.v
x393_sata/host/scrambler.v
+12
-7
system_defines.vh
x393_sata/system_defines.vh
+39
-0
top_tmp.v
x393_sata/top_tmp.v
+13
-7
GTXE2_GPL.v
x393_sata/wrapper/GTXE2_GPL.v
+12
-7
clock_inverter.v
x393_sata/wrapper/clock_inverter.v
+12
-7
gtxe2_channel_wrapper.v
x393_sata/wrapper/gtxe2_channel_wrapper.v
+12
-7
No files found.
.gitignore
View file @
00e7a575
...
...
@@ -18,8 +18,12 @@ x393.prj
*.bad
*.pyc
*.pickle
*.tmp
py393/dbg*
debug
debug/*
html/*
man/*
includes/x393_cur_params_sim.vh
includes/x393_cur_params_target_*.vh
py393/exp_gpio.py
...
...
axi/axibram_read.v
View file @
00e7a575
/*******************************************************************************
* Module: axibram_read
* Date:2014-03-18
* Author: Andrey Filippov
* Description: Read block RAM memory over AXI PS Master GP0
/*!
* <b>Module:</b>axibram_read
* @file axibram_read.v
* @date 2014-03-18
* @author Andrey Filippov
*
* @brief Read block RAM memory over AXI PS Master GP0
*
* @copyright Copyright (c) 2014 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2014 Elphel, Inc.
* axibram_read.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
...
...
@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
// Check that this fix did not break anything:
`include
"system_defines.vh"
`define
USE_SHORT_REN_REGEN
...
...
@@ -227,8 +232,7 @@ module axibram_read #(
assign
bram_reg_re_w
=
dev_ready
&&
read_in_progress_or
&&
(
!
rvalid
||
rready
)
;
// slower/simplier
// assign bram_reg_re_w= rready? read_in_progress : bram_reg_re_0; // faster - more verification
assign
last_in_burst_w
=
bram_reg_re_w
&&
(
read_left
==
4'b0
)
;
// slower/simplier
assign
last_in_burst_w
=
bram_reg_re_w
&&
(
read_left
==
4'b0
)
;
// slower/simplier
// assign last_in_burst_w=rready? (read_in_progress && (read_left==4'b0)): (bram_reg_re_0 && (read_left==4'b0));
// assign last_in_burst_w=rready? last_in_burst_1: last_in_burst_0; // faster (unfinished) - more verification
...
...
@@ -250,7 +254,7 @@ module axibram_read #(
// assign start_read_burst_w= ar_nempty && (rready?start_read_burst_1:start_read_burst_0);
fifo_same_clock
#(
.
DATA_WIDTH
(
ADDRESS_BITS
+
20
)
,.
DATA_DEPTH
(
4
))
raddr_i
(
raddr_i
(
.
rst
(
1'b0
)
,
.
clk
(
aclk
)
,
.
sync_rst
(
arst
)
,
...
...
axi/axibram_write.v
View file @
00e7a575
/*******************************************************************************
* Module: axibram_write
* Date:2014-03-18
* Author: Andrey Filippov
* Description: Read block RAM memory (or memories?) over AXI PS Master GP0
/*!
* <b>Module:</b>axibram_write
* @file axibram_write.v
* @date 2014-03-18
* @author Andrey Filippov
*
* @brief Read block RAM memory (or memories?) over AXI PS Master GP0
* Memory is supposed to be fast enough
*
* Copyright (c) 2014 Elphel, Inc.
* @copyright Copyright (c) 2014 Elphel, Inc.
*
* <b>License:</b>
*
* axibram_write.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
...
...
@@ -31,7 +36,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
//`define DEBUG_FIFO 1
`include
"system_defines.vh"
`ifdef
DEBUG_FIFO
...
...
axi/cmprs_afi_mux.v
View file @
00e7a575
/*******************************************************************************
* Module: cmprs_afi_mux
* Date:2015-06-26
* Author: Andrey Filippov
* Description: Writes comressor data from up to 4 channels to system memory over AXI_HP
/*!
* <b>Module:</b>cmprs_afi_mux
* @file cmprs_afi_mux.v
* @date 2015-06-26
* @author Andrey Filippov
*
* @brief Writes comressor data from up to 4 channels to system memory over AXI_HP
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* cmprs_afi_mux.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
...
...
@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
module
cmprs_afi_mux
#(
...
...
axi/cmprs_afi_mux_ptr.v
View file @
00e7a575
/*******************************************************************************
* Module: cmprs_afi_mux_ptr
* Date:2015-06-28
* Author: Andrey Filippov
* Description: Maintain 4-channel chunk pointers (before AXI)
/*!
* <b>Module:</b>cmprs_afi_mux_ptr
* @file cmprs_afi_mux_ptr.v
* @date 2015-06-28
* @author Andrey Filippov
*
* @brief Maintain 4-channel chunk pointers (before AXI)
* Advance 32-byte chunk pointers for each AXI burst and each frame (4*2=8 pointers)
*
* Copyright (c) 2015 Elphel, Inc.
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* cmprs_afi_mux_ptr.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
...
...
@@ -31,7 +36,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
module
cmprs_afi_mux_ptr
(
...
...
axi/cmprs_afi_mux_ptr_wresp.v
View file @
00e7a575
/*******************************************************************************
* Module: cmprs_afi_mux_ptr_wresp
* Date:2015-06-28
* Author: Andrey Filippov
* Description: Maintain 4-channel chunk pointers for wrirte response
/*!
* <b>Module:</b>cmprs_afi_mux_ptr_wresp
* @file cmprs_afi_mux_ptr_wresp.v
* @date 2015-06-28
* @author Andrey Filippov
*
* @brief Maintain 4-channel chunk pointers for wrirte response
* Advance 32-byte chunk pointers for each AXI burst and each frame (4*2=8 pointers)
*
* Copyright (c) 2015 Elphel, Inc.
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* cmprs_afi_mux_ptr_wresp.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
...
...
@@ -31,7 +36,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
module
cmprs_afi_mux_ptr_wresp
(
...
...
axi/cmprs_afi_mux_status.v
View file @
00e7a575
/*******************************************************************************
* Module: cmprs_afi_mux_status
* Date:2015-06-28
* Author: Andrey Filippov
* Description: prepare and send per-channel chunk pointer information as status
/*!
* <b>Module:</b>cmprs_afi_mux_status
* @file cmprs_afi_mux_status.v
* @date 2015-06-28
* @author Andrey Filippov
*
* @brief prepare and send per-channel chunk pointer information as status
* Using 4 consecutive locations. Each channel can provide one of the 4 pointers:
* frame pointer in the write channel, current chunk pointer in the write channel
* and the same for the write response channel (confirmed written to the system
* memory
*
* Copyright (c) 2015 Elphel, Inc.
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* cmprs_afi_mux_status.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
...
...
@@ -34,7 +39,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
module
cmprs_afi_mux_status
#(
...
...
axi/histogram_saxi.v
View file @
00e7a575
/*******************************************************************************
* Module: histogram_saxi
* Date:2015-06-04
* Author: Andrey Filippov
* Description: Histograms transfer to the system memory over S_AXI
/*!
* <b>Module:</b>histogram_saxi
* @file histogram_saxi.v
* @date 2015-06-04
* @author Andrey Filippov
*
* @brief Histograms transfer to the system memory over S_AXI
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* histogram_saxi.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
...
...
@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
// Number of histograms per sensor is now statically defined by NUM_FRAME_BITS
// It may be modified to both reduce this number (by masking) or increase ( by
...
...
axi/macros393.v
deleted
100644 → 0
View file @
1df762e6
/*
** -----------------------------------------------------------------------------**
** macros353.v
**
** temporary, modules to be moved
**
** Copyright (C) 2002 Elphel, Inc
**
** -----------------------------------------------------------------------------**
** This file is part of X353
** X353 is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
*/
module
ram_WxD
#(
parameter
integer
DATA_WIDTH
=
16
,
parameter
integer
DATA_DEPTH
=
4
,
parameter
integer
DATA_2DEPTH
=
(
1
<<
DATA_DEPTH
)
-
1
)
(
input
[
DATA_WIDTH
-
1
:
0
]
D
,
input
WE
,
input
clk
,
input
[
DATA_DEPTH
-
1
:
0
]
AW
,
input
[
DATA_DEPTH
-
1
:
0
]
AR
,
output
[
DATA_WIDTH
-
1
:
0
]
QW
,
output
[
DATA_WIDTH
-
1
:
0
]
QR
)
;
reg
[
DATA_WIDTH
-
1
:
0
]
ram
[
0
:
DATA_2DEPTH
]
;
always
@
(
posedge
clk
)
if
(
WE
)
ram
[
AW
]
<=
D
;
assign
QW
=
ram
[
AW
]
;
assign
QR
=
ram
[
AR
]
;
endmodule
axi/membridge.v
View file @
00e7a575
/*******************************************************************************
* Module: membridge
* Date:2015-04-26
* Author: Andrey Filippov
* Description: bi-directional bridge between system and video memory over axi_hp
/*!
* <b>Module:</b>membridge
* @file membridge.v
* @date 2015-04-26
* @author Andrey Filippov
*
* @brief bi-directional bridge between system and video memory over axi_hp
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* membridge.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
...
...
@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
//`define MEMBRIDGE_DEBUG_READ 1
module
membridge
#(
...
...
axi/mul_saxi_wr_chn.v
View file @
00e7a575
/*******************************************************************************
* Module: mul_saxi_wr_chn
* Date:2015-07-10
* Author: Andrey Filippov
* Description: One channel of the mult_saxi_wr (read/write common buffer)
/*!
* <b>Module:</b>mul_saxi_wr_chn
* @file mul_saxi_wr_chn.v
* @date 2015-07-10
* @author Andrey Filippov
*
* @brief One channel of the mult_saxi_wr (read/write common buffer)
*
* @copyright Copyright (c) 2015 Elphel, Inc .
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc .
* mul_saxi_wr_chn.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
...
...
@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
module
mult_saxi_wr_chn
#(
...
...
axi/mult_saxi_wr.v
View file @
00e7a575
/*******************************************************************************
* Module: mult_saxi_wr
* Date:2015-07-08
* Author: Andrey Filippov
* Description: send data from up to 4 sources to the system memory over S_AXI.
/*!
* <b>Module:</b>mult_saxi_wr
* @file mult_saxi_wr.v
* @date 2015-07-08
* @author Andrey Filippov
*
* @brief send data from up to 4 sources to the system memory over S_AXI.
* Each source should have a 32-bit wide buffer running at the same clock (mclk).
* Buffer should contain at least burst size (4,8,16,32,64 bytes)
* Burst size parameter-configurable (per-port)
*
* Copyright (c) 2015 Elphel, Inc .
* @copyright Copyright (c) 2015 Elphel, Inc .
*
* <b>License:</b>
*
* mult_saxi_wr.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
...
...
@@ -33,7 +38,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
module
mult_saxi_wr
#(
...
...
@@ -181,7 +186,7 @@ module mult_saxi_wr #(
else
if
(
we_ctrl
&&
!
cmd_a
[
0
])
mode_reg
<=
cmd_data
[
7
:
0
]
;
end
// Arbiter requests on copying from one of t
eh
input channels to the internal buffer
// Arbiter requests on copying from one of t
he
input channels to the internal buffer
mult_saxi_wr_chn
#(
.
MULT_SAXI_HALF_BRAM
(
MULT_SAXI_HALF_BRAM
)
,
...
...
axi/mult_saxi_wr_inbuf.v
View file @
00e7a575
/*******************************************************************************
* Module: mult_saxi_wr_inbuf
* Date:2015-07-11
* Author: Andrey Filippov
* Description: Channel buffer with width conversion to 32 to use with mult_saxi_wr
/*!
* <b>Module:</b>mult_saxi_wr_inbuf
* @file mult_saxi_wr_inbuf.v
* @date 2015-07-11
* @author Andrey Filippov
*
* @brief Channel buffer with width conversion to 32 to use with mult_saxi_wr
*
* @copyright Copyright (c) 2015 Elphel, Inc .
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc .
* mult_saxi_wr_inbuf.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
...
...
@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
module
mult_saxi_wr_inbuf
#(
...
...
axi/mult_saxi_wr_pointers.v
View file @
00e7a575
/*******************************************************************************
* Module: mult_saxi_wr_pointers
* Date:2015-07-10
* Author: Andrey Filippov
* Description: Process pointers for mult_saxi_wr
/*!
* <b>Module:</b>mult_saxi_wr_pointers
* @file mult_saxi_wr_pointers.v
* @date 2015-07-10
* @author Andrey Filippov
*
* @brief Process pointers for mult_saxi_wr
*
* @copyright Copyright (c) 2015 Elphel, Inc .
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc .
* mult_saxi_wr_pointers.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
...
...
@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
module
mult_saxi_wr_pointers
#(
...
...
cmd_mux.v
View file @
00e7a575
/*******************************************************************************
* Module: cmd_mux
* Date:2015-01-11
* Author: Andrey Filippov
* Description: Command multiplexer between AXI and frame-based command sequencer
/*!
* <b>Module:</b>cmd_mux
* @file cmd_mux.v
* @date 2015-01-11
* @author Andrey Filippov
*
* @brief Command multiplexer between AXI and frame-based command sequencer
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* cmd_mux.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
...
...
@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
module
cmd_mux
#(
...
...
cmd_readback.v
View file @
00e7a575
/*******************************************************************************
* Module: cmd_readback
* Date:2015-05-05
* Author: Andrey Filippov
* Description: Store control register data and readback
/*!
* <b>Module:</b>cmd_readback
* @file cmd_readback.v
* @date 2015-05-05
* @author Andrey Filippov
*
* @brief Store control register data and readback
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* cmd_readback.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
...
...
@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
module
cmd_readback
#(
...
...
compressor_jp/bit_stuffer_27_32.v
View file @
00e7a575
/*******************************************************************************
* Module: bit_stuffer_27_32
* Date:2015-10-23
* Author: Andrey Filippov
* Description: Aggregate MSB aligned variable-length (1..27) data to 32-bit words
/*!
* <b>Module:</b>bit_stuffer_27_32
* @file bit_stuffer_27_32.v
* @date 2015-10-23
* @author Andrey Filippov
*
* @brief Aggregate MSB aligned variable-length (1..27) data to 32-bit words
*
* @copyright Copyright (c) 2015 Elphel, Inc .
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc .
* bit_stuffer_27_32.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
...
...
@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
module
bit_stuffer_27_32
#(
...
...
compressor_jp/bit_stuffer_escape.v
View file @
00e7a575
/*******************************************************************************
* Module: bit_stuffer_escape
* Date:2015-10-24
* Author: Andrey Filippov
* Description: Escapes each 0xff with 0x00, 32-bit input and output
/*!
* <b>Module:</b>bit_stuffer_escape
* @file bit_stuffer_escape.v
* @date 2015-10-24
* @author Andrey Filippov
*
* @brief Escapes each 0xff with 0x00, 32-bit input and output
*
* @copyright Copyright (c) 2015 Elphel, Inc .
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc .
* bit_stuffer_escape.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
...
...
@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
module
bit_stuffer_escape
(
...
...
compressor_jp/bit_stuffer_metadata.v
View file @
00e7a575
/*******************************************************************************
* Module: bit_stuffer_metadata
* Date:2015-10-25
* Author: Andrey Filippov
* Description:
/*!
* <b>Module:</b>bit_stuffer_metadata
* @file bit_stuffer_metadata.v
* @date 2015-10-25
* @author Andrey Filippov
*
* @brief Bit stuffer combines variable length fragments (up to 16 bits long)
* from the Huffman encoder to a byte stream, escapes every 0xff byte with
* 0x00 and adds file length and timestamp metadata
*
* @copyright Copyright (c) 2015 Elphel, Inc .
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc .
* bit_stuffer_metadata.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
...
...
@@ -30,7 +37,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
module
bit_stuffer_metadata
(
...
...
compressor_jp/cmprs_buf_average.v
View file @
00e7a575
/*******************************************************************************
* Module: cmprs_buf_average
* Date:2015-06-14
* Author: Andrey Filippov
* Description: Saves Y and C components to buffers, caculates averages
/*!
* <b>Module:</b>cmprs_buf_average
* @file cmprs_buf_average.v
* @date 2015-06-14
* @author Andrey Filippov
*
* @brief Saves Y and C components to buffers, caculates averages
* during write, then subtracts them during read and provides to
* the after DCT to restore DC
*
* Copyright (c) 2015 Elphel, Inc.
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* cmprs_buf_average.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
