Commit db53f38f authored by Andrey Filippov's avatar Andrey Filippov
Browse files

testing and simulating, improving timing

parent 4ca48f7b

.gitignore

+2 −0
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@@ -10,6 +10,8 @@ x393.prj 
*DEBUG_VDT*

*DEBUG_VDT*

*.kate-swp

*.kate-swp

*.old

*.old

*.new

*.bad

*.pyc

*.pyc

*.pickle

*.pickle

py393/dbg*

py393/dbg*

.project

+9 −9
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@@ -62,42 +62,42 @@ 
		<link>

		<link>

			<name>vivado_logs/VivadoBitstream.log</name>

			<name>vivado_logs/VivadoBitstream.log</name>

			<type>1</type>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151031232832558.log</location>

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		</link>

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		<link>

		<link>

			<name>vivado_logs/VivadoOptPhys.log</name>

			<name>vivado_logs/VivadoOptPhys.log</name>

			<type>1</type>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151031232832558.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151103114104932.log</location>

		</link>

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		<link>

		<link>

			<name>vivado_logs/VivadoOptPower.log</name>

			<name>vivado_logs/VivadoOptPower.log</name>

			<type>1</type>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151031232832558.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151103114104932.log</location>

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			<name>vivado_logs/VivadoPlace.log</name>

			<name>vivado_logs/VivadoPlace.log</name>

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			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151031232832558.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151103114104932.log</location>

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			<name>vivado_logs/VivadoRoute.log</name>

			<name>vivado_logs/VivadoRoute.log</name>

			<type>1</type>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151031232832558.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151103114104932.log</location>

		</link>

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		<link>

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			<name>vivado_logs/VivadoSynthesis.log</name>

			<name>vivado_logs/VivadoSynthesis.log</name>

			<type>1</type>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151031232335810.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151103114104932.log</location>

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			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>

			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>

			<type>1</type>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151031232832558.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151103114104932.log</location>

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			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
@@ -107,7 +107,7 @@ 
		<link>

		<link>

			<name>vivado_logs/VivadoTimingReportImplemented.log</name>

			<name>vivado_logs/VivadoTimingReportImplemented.log</name>

			<type>1</type>

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			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150904164653967.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20151101221627109.log</location>

		</link>

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		<link>

		<link>

			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>

			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>

.settings/com.elphel.vdt.VivadoRoute.prefs

+2 −1
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VivadoRoute_122_SkipSnapshotRoute=true

VivadoRoute_122_SkipSnapshotRoute=true

VivadoRoute_123_SkipSnapshotRoute=true

VivadoRoute_123_SkipSnapshotRoute=true

com.elphel.store.context.VivadoRoute=VivadoRoute_122_SkipSnapshotRoute<-@\#\#@->VivadoRoute_123_SkipSnapshotRoute<-@\#\#@->

VivadoRoute_125_directive_route=MoreGlobalIterations

com.elphel.store.context.VivadoRoute=VivadoRoute_122_SkipSnapshotRoute<-@\#\#@->VivadoRoute_123_SkipSnapshotRoute<-@\#\#@->VivadoRoute_125_directive_route<-@\#\#@->

eclipse.preferences.version=1
 
eclipse.preferences.version=1

compressor_jp/csconvert18a.v

+66 −34
Original line number Original line Diff line number Diff line
@@ -249,7 +249,7 @@ module csconvert18a( 




  wire        ystrt,nxtline;

  wire        ystrt,nxtline;

  reg	[7:0] yaddr_r; // address for the external buffer memory to write 16x16x8bit Y data

  reg	[7:0] yaddr_r; // address for the external buffer memory to write 16x16x8bit Y data

  reg         ywe_r;	 // wrire enable of Y data

  reg         ywe_r;	 // write enable of Y data

  reg   [6:0] caddr_r; // address for the external buffer memory 2x8x8x8bit Cb+Cr data (MSB=0 - Cb, 1 - Cr)

  reg   [6:0] caddr_r; // address for the external buffer memory 2x8x8x8bit Cb+Cr data (MSB=0 - Cb, 1 - Cr)

  reg         cwe_r;	 // write enable for CbCr data 

  reg         cwe_r;	 // write enable for CbCr data 

  reg         odd_pix;  // odd pixel (assumes even number of pixels in a line

  reg         odd_pix;  // odd pixel (assumes even number of pixels in a line
@@ -267,10 +267,10 @@ module csconvert18a( 
  assign n000 =     n000_r;

  assign n000 =     n000_r;

  assign n255 =     n255_r;

  assign n255 =     n255_r;

  assign signed_y = signed_y_r;     //  - now signed char, -128(black) to +127 (white)

  assign signed_y = signed_y_r;     //  - now signed char, -128(black) to +127 (white)

  assign yaddr =    yaddr_r;

  assign yaddr =    yaddr_r2;

  assign ywe =      ywe_r;

  assign ywe =      ywe_r2;

  assign caddr =    caddr_r;

  assign caddr =    caddr_r2;

  assign cwe =      cwe_r;

  assign cwe =      cwe_r2;

  

  

    dly_16 #(.WIDTH(1)) i_strt_dly0 (.clk(CLK),.rst(1'b0), .dly(4'd15), .din(pre_first_in), .dout(strt_dly[0]));

    dly_16 #(.WIDTH(1)) i_strt_dly0 (.clk(CLK),.rst(1'b0), .dly(4'd15), .din(pre_first_in), .dout(strt_dly[0]));

    dly_16 #(.WIDTH(1)) i_strt_dly1 (.clk(CLK),.rst(1'b0), .dly(4'd15), .din(strt_dly[0]),  .dout(strt_dly[1]));

    dly_16 #(.WIDTH(1)) i_strt_dly1 (.clk(CLK),.rst(1'b0), .dly(4'd15), .din(strt_dly[0]),  .dout(strt_dly[1]));
@@ -532,20 +532,28 @@ Y[1,1]=(0x96*P[1,1]+ 0x1d*((P[1,0]+P[1,2])/2 + 0x4d*((P[0,1] + 




  reg   [7:0] y;

  reg   [7:0] y;

//  reg   [7:0] y0;	// bypass in monochrome mode

//  reg   [7:0] y0;	// bypass in monochrome mode

  wire  [7:0] y0 = pdc;

//  wire  [7:0] y0 = pdc;

  reg  [7:0] y0_r;

//  wire   [7:0] y0;	// bypass in monochrome mode

//  wire   [7:0] y0;	// bypass in monochrome mode

  reg   [15:0] y1,y2,y3;

  reg   [15:0] y1,y2,y3;

  wire	[15:0] y_sum =y1+y2+y3;

  

// TODO: insert register to ease mm1..3 -> y (OK to delay all outputs). Or is it not using DSP at all?   

//  wire	[15:0] y_sum =y1+y2+y3;

  reg   [15:0] y_sum_r;

//  always @ (posedge CLK) y0 <= pd1_dly; // m1; // equivalent

//  always @ (posedge CLK) y0 <= pd1_dly; // m1; // equivalent

  always @ (posedge CLK) y1 <= mm1;

//  wire   [7:0] pre_y= mono ? y0 : (y_sum[15:8]+y_sum[7]);

  always @ (posedge CLK) y2 <= mm2;

  wire   [7:0] pre_y= mono ? y0_r : (y_sum_r[15:8]+y_sum_r[7]);

  always @ (posedge CLK) y3 <= mm3;

// making y output signed -128..+127

// making y output signed -128..+127

  wire   [7:0] pre_y= mono ? y0 : (y_sum[15:8]+y_sum[7]);



  always @ (posedge CLK) y[7:0] <= pre_y[7:0];





  always @ (posedge CLK) signed_y_r[7:0] <= {~pre_y[7], pre_y[6:0]};

  always @ (posedge CLK) begin

      y1 <= mm1;

      y2 <= mm2;

      y3 <= mm3;

      y0_r <= pdc;

      y_sum_r <= y1+y2+y3;

      y[7:0] <= pre_y[7:0];

      signed_y_r[7:0] <= {~pre_y[7], pre_y[6:0]};

  end









// Try easier and hope better algorithm of color extractions that should perform better on gradients.

// Try easier and hope better algorithm of color extractions that should perform better on gradients.
@@ -575,12 +583,21 @@ reg sub_y; // output accumulator/subtractor. 0 - load new data, 
wire        cwe0;          // preliminary cwe_r (to be modulated by odd/even pixels)

wire        cwe0;          // preliminary cwe_r (to be modulated by odd/even pixels)

reg         cstrt;         //ystrt dealyed by 1

reg         cstrt;         //ystrt dealyed by 1

reg         cnxt;          // nxtline delayed by 1

reg         cnxt;          // nxtline delayed by 1

reg         pre_sel_cbcrmult1;

// delaying, for now uing "old" ywe,cwe, yaddr,caddr - registering them on the output

 

always @ (posedge CLK) begin

always @ (posedge CLK) begin

  if (~(ywe_r || ystrt || nxtline)) sel_cbcrmult1 <= ~(bayer_phase[1] ^ bayer_phase[0] ^ odd_line);

//  if (~(ywe_r || ystrt || nxtline)) sel_cbcrmult1 <= ~(bayer_phase[1] ^ bayer_phase[0] ^ odd_line);

  else      sel_cbcrmult1 <= ~sel_cbcrmult1;

//  else      sel_cbcrmult1 <= ~sel_cbcrmult1;

  if (~(ywe_r || ystrt || nxtline)) pre_sel_cbcrmult1 <= ~(bayer_phase[1] ^ bayer_phase[0] ^ odd_line);

  else      pre_sel_cbcrmult1 <= ~pre_sel_cbcrmult1;

  

  sel_cbcrmult1 <=pre_sel_cbcrmult1;

  

  sub_y <= ~sel_cbcrmult1;

  sub_y <= ~sel_cbcrmult1;

  cbcrmult1 <= sel_cbcrmult1?y[7:0]:pdc[7:0];

//  cbcrmult1 <= sel_cbcrmult1?y[7:0]:pdc[7:0];

  cbcrmult1 <= sel_cbcrmult1?y[7:0]:pdc[7:0];

  cbcrmult1 <= sel_cbcrmult1?y[7:0]:y0_r[7:0]; // delayed by 1 clock

  

  if (~ywe_r) use_cr <= ~(bayer_phase[1] ^ odd_line);

  if (~ywe_r) use_cr <= ~(bayer_phase[1] ^ odd_line);

end

end

assign      cbcrmult2 = use_cr?m_cr:m_cb;  // maybe will need a register? (use_cr will still be good as it is valid early)

assign      cbcrmult2 = use_cr?m_cr:m_cb;  // maybe will need a register? (use_cr will still be good as it is valid early)
@@ -601,23 +618,38 @@ end 
dly_16 #(.WIDTH(1)) i_cwe0 (.clk(CLK),.rst(1'b0), .dly(4'd1), .din(ywe_r), .dout(cwe0));

dly_16 #(.WIDTH(1)) i_cwe0 (.clk(CLK),.rst(1'b0), .dly(4'd1), .din(ywe_r), .dout(cwe0));

//SRL16 i_cwe0    (.D(ywe_r ),  .Q(cwe0), .A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CLK(CLK)); // dly=2=1+1

//SRL16 i_cwe0    (.D(ywe_r ),  .Q(cwe0), .A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CLK(CLK)); // dly=2=1+1









    always @ (posedge CLK) begin

    always @ (posedge CLK) begin

        cstrt <= ystrt;

        cstrt <= ystrt;

        cnxt  <= nxtline;

        cnxt  <= nxtline;

      cwe_r <= cwe0 && sub_y; 

//        cwe_r <= cwe0 && sub_y;

        cwe_r <= cwe0 && !sel_cbcrmult1;

        caddr_r[2:0]<= cwe0?(caddr_r[2:0]+cwe_r):3'b0;

        caddr_r[2:0]<= cwe0?(caddr_r[2:0]+cwe_r):3'b0;

        if (cstrt)     caddr_r[6] <= ~bayer_phase[1];

        if (cstrt)     caddr_r[6] <= ~bayer_phase[1];

        else if (cnxt) caddr_r[6] <= ~caddr_r[6];

        else if (cnxt) caddr_r[6] <= ~caddr_r[6];

        if (cstrt)     caddr_r[5:3] <=3'b0;

        if (cstrt)     caddr_r[5:3] <=3'b0;

        else if (cnxt) caddr_r[5:3] <=(bayer_phase[1]^caddr_r[6])? caddr_r[5:3]:(caddr_r[5:3]+1);

        else if (cnxt) caddr_r[5:3] <=(bayer_phase[1]^caddr_r[6])? caddr_r[5:3]:(caddr_r[5:3]+1);

    end

    end

// extra signals delayed by 1 clock

    reg ywe_r2, cwe_r2;

    reg [6:0] caddr_r2;

    reg [7:0] yaddr_r2;

    always @ (posedge CLK) begin

        ywe_r2 <= ywe_r;

        cwe_r2 <= cwe_r;

        yaddr_r2 <= yaddr_r;

        caddr_r2 <= caddr_r;

    end





  always @ (posedge CLK) begin

  always @ (posedge CLK) begin

    y_eq_0   <= (y0[7:0] == 8'h0);

    y_eq_0   <= (y0_r[7:0] == 8'h0);

    y_eq_255 <= (y0[7:0] == 8'hff);

    y_eq_255 <= (y0_r[7:0] == 8'hff);

    if (strt) n000_r[7:0] <= 8'h0;

    if (strt) n000_r[7:0] <= 8'h0;

    else if ((n000_r[7:0]!=8'hff) && y_eq_0 && ywe_r) n000_r[7:0] <= n000_r[7:0]+1;

    else if ((n000_r[7:0]!=8'hff) && y_eq_0 && ywe_r2) n000_r[7:0] <= n000_r[7:0]+1;

    if (strt) n255_r[7:0] <= 8'h0;

    if (strt) n255_r[7:0] <= 8'h0;

    else if ((n255_r[7:0]!=8'hff) && y_eq_255 && ywe_r) n255_r[7:0] <= n255_r[7:0]+1;

    else if ((n255_r[7:0]!=8'hff) && y_eq_255 && ywe_r2) n255_r[7:0] <= n255_r[7:0]+1;

  end

  end

ddr3/ddr3.v

+14 −1
Original line number Original line Diff line number Diff line
@@ -85,7 +85,7 @@ 
* 1.69  SPH      03/19/13    Update tZQCS, tZQinit, tZQoper timing parameters

* 1.69  SPH      03/19/13    Update tZQCS, tZQinit, tZQoper timing parameters

* 1.70  SPH      04/08/14    Update tRFC to PRECARGE check

* 1.70  SPH      04/08/14    Update tRFC to PRECARGE check

*****************************************************************************************/

*****************************************************************************************/

`define den4096Mb 1

`include "system_defines.vh" 

// DO NOT CHANGE THE TIMESCALE

// DO NOT CHANGE THE TIMESCALE

// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION

// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION

`timescale 1ps / 1ps

`timescale 1ps / 1ps
@@ -121,6 +121,19 @@ module ddr3 ( 
    //       to select the correct component density before continuing

    //       to select the correct component density before continuing

    ERROR: You must specify component density with +define+den____Mb.

    ERROR: You must specify component density with +define+den____Mb.

`endif

`endif

    initial begin

        $display ("TCK_MIN = %d", TCK_MIN);

`ifdef sg15E

        $display ("sg15E = `sg15E");

`endif  

    

`ifdef sg093                              // sg093  is equivalent to the JEDEC DDR3-2133 (14-14-14) speed bin

        $display ("sg093");

`elsif sg15E

        $display ("sg15E");

`endif          

    end

    

    parameter check_strict_mrbits = 1;

    parameter check_strict_mrbits = 1;

    parameter check_strict_timing = 1;

    parameter check_strict_timing = 1;

    parameter feature_pasr = 1;

    parameter feature_pasr = 1;