testing and simulating, improving timing

.gitignore

@@ -10,6 +10,8 @@ x393.prj
 *DEBUG_VDT*
 *.kate-swp
 *.old
+*.new
+*.bad
 *.pyc
 *.pickle
 py393/dbg*

.project

@@ -62,42 +62,42 @@
 		<link>
 			<name>vivado_logs/VivadoBitstream.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151031232832558.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151103114104932.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOpt.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151031232832558.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151103114104932.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPhys.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151031232832558.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151103114104932.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPower.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151031232832558.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151103114104932.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoPlace.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151031232832558.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151103114104932.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoRoute.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151031232832558.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151103114104932.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151031232335810.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151103114104932.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151031232832558.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151103114104932.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
@@ -107,7 +107,7 @@
 		<link>
 			<name>vivado_logs/VivadoTimingReportImplemented.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150904164653967.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20151101221627109.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>

.settings/com.elphel.vdt.VivadoRoute.prefs

 VivadoRoute_122_SkipSnapshotRoute=true
 VivadoRoute_123_SkipSnapshotRoute=true
-com.elphel.store.context.VivadoRoute=VivadoRoute_122_SkipSnapshotRoute<-@\#\#@->VivadoRoute_123_SkipSnapshotRoute<-@\#\#@->
+VivadoRoute_125_directive_route=MoreGlobalIterations
+com.elphel.store.context.VivadoRoute=VivadoRoute_122_SkipSnapshotRoute<-@\#\#@->VivadoRoute_123_SkipSnapshotRoute<-@\#\#@->VivadoRoute_125_directive_route<-@\#\#@->
 eclipse.preferences.version=1

compressor_jp/csconvert18a.v

@@ -249,7 +249,7 @@ module csconvert18a(
 
   wire        ystrt,nxtline;
   reg	[7:0] yaddr_r; // address for the external buffer memory to write 16x16x8bit Y data
-  reg         ywe_r;	 // wrire enable of Y data
+  reg         ywe_r;	 // write enable of Y data
   reg   [6:0] caddr_r; // address for the external buffer memory 2x8x8x8bit Cb+Cr data (MSB=0 - Cb, 1 - Cr)
   reg         cwe_r;	 // write enable for CbCr data 
   reg         odd_pix;  // odd pixel (assumes even number of pixels in a line
@@ -267,10 +267,10 @@ module csconvert18a(
   assign n000 =     n000_r;
   assign n255 =     n255_r;
   assign signed_y = signed_y_r;     //  - now signed char, -128(black) to +127 (white)
-  assign yaddr =    yaddr_r;
-  assign ywe =      ywe_r;
-  assign caddr =    caddr_r;
-  assign cwe =      cwe_r;
+  assign yaddr =    yaddr_r2;
+  assign ywe =      ywe_r2;
+  assign caddr =    caddr_r2;
+  assign cwe =      cwe_r2;
   
     dly_16 #(.WIDTH(1)) i_strt_dly0 (.clk(CLK),.rst(1'b0), .dly(4'd15), .din(pre_first_in), .dout(strt_dly[0]));
     dly_16 #(.WIDTH(1)) i_strt_dly1 (.clk(CLK),.rst(1'b0), .dly(4'd15), .din(strt_dly[0]),  .dout(strt_dly[1]));
@@ -532,20 +532,28 @@ Y[1,1]=(0x96*P[1,1]+   0x1d*((P[1,0]+P[1,2])/2 +                 0x4d*((P[0,1] +
 
   reg   [7:0] y;
 //  reg   [7:0] y0;	// bypass in monochrome mode
-  wire  [7:0] y0 = pdc;
+//  wire  [7:0] y0 = pdc;
+  reg  [7:0] y0_r;
 //  wire   [7:0] y0;	// bypass in monochrome mode
-  reg   [15:0] y1,y2,y3; 
-  wire	[15:0] y_sum =y1+y2+y3;
+  reg   [15:0] y1,y2,y3;
+  
+// TODO: insert register to ease mm1..3 -> y (OK to delay all outputs). Or is it not using DSP at all?   
+//  wire	[15:0] y_sum =y1+y2+y3;
+  reg   [15:0] y_sum_r;
 //  always @ (posedge CLK) y0 <= pd1_dly; // m1; // equivalent
-  always @ (posedge CLK) y1 <= mm1;
-  always @ (posedge CLK) y2 <= mm2;
-  always @ (posedge CLK) y3 <= mm3;
+//  wire   [7:0] pre_y= mono ? y0 : (y_sum[15:8]+y_sum[7]);
+  wire   [7:0] pre_y= mono ? y0_r : (y_sum_r[15:8]+y_sum_r[7]);
 // making y output signed -128..+127
-  wire   [7:0] pre_y= mono ? y0 : (y_sum[15:8]+y_sum[7]);
-
-  always @ (posedge CLK) y[7:0] <= pre_y[7:0];
 
-  always @ (posedge CLK) signed_y_r[7:0] <= {~pre_y[7], pre_y[6:0]};
+  always @ (posedge CLK) begin
+      y1 <= mm1;
+      y2 <= mm2;
+      y3 <= mm3;
+      y0_r <= pdc;
+      y_sum_r <= y1+y2+y3;
+      y[7:0] <= pre_y[7:0];
+      signed_y_r[7:0] <= {~pre_y[7], pre_y[6:0]};
+  end
 
 
 // Try easier and hope better algorithm of color extractions that should perform better on gradients.
@@ -574,13 +582,22 @@ reg         use_cr;        // in this line cr is calculated. Valid during ywe_r
 reg         sub_y;         // output accumulator/subtractor. 0 - load new data, 1 - subtract. Walid 2 cycles after ywe_r
 wire        cwe0;          // preliminary cwe_r (to be modulated by odd/even pixels)
 reg         cstrt;         //ystrt dealyed by 1
-reg         cnxt;          // nxtline delayed by 1 
+reg         cnxt;          // nxtline delayed by 1
+reg         pre_sel_cbcrmult1;
+// delaying, for now uing "old" ywe,cwe, yaddr,caddr - registering them on the output
+ 
 always @ (posedge CLK) begin
-  if (~(ywe_r || ystrt || nxtline)) sel_cbcrmult1 <= ~(bayer_phase[1] ^ bayer_phase[0] ^ odd_line);
-  else      sel_cbcrmult1 <= ~sel_cbcrmult1;
+//  if (~(ywe_r || ystrt || nxtline)) sel_cbcrmult1 <= ~(bayer_phase[1] ^ bayer_phase[0] ^ odd_line);
+//  else      sel_cbcrmult1 <= ~sel_cbcrmult1;
+  if (~(ywe_r || ystrt || nxtline)) pre_sel_cbcrmult1 <= ~(bayer_phase[1] ^ bayer_phase[0] ^ odd_line);
+  else      pre_sel_cbcrmult1 <= ~pre_sel_cbcrmult1;
+  
+  sel_cbcrmult1 <=pre_sel_cbcrmult1;
+  
   sub_y <= ~sel_cbcrmult1;
-  cbcrmult1 <= sel_cbcrmult1?y[7:0]:pdc[7:0];
-  cbcrmult1 <= sel_cbcrmult1?y[7:0]:pdc[7:0];
+//  cbcrmult1 <= sel_cbcrmult1?y[7:0]:pdc[7:0];
+  cbcrmult1 <= sel_cbcrmult1?y[7:0]:y0_r[7:0]; // delayed by 1 clock
+  
   if (~ywe_r) use_cr <= ~(bayer_phase[1] ^ odd_line);
 end
 assign      cbcrmult2 = use_cr?m_cr:m_cb;  // maybe will need a register? (use_cr will still be good as it is valid early)
@@ -601,23 +618,38 @@ end
 dly_16 #(.WIDTH(1)) i_cwe0 (.clk(CLK),.rst(1'b0), .dly(4'd1), .din(ywe_r), .dout(cwe0));
 //SRL16 i_cwe0    (.D(ywe_r ),  .Q(cwe0), .A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CLK(CLK)); // dly=2=1+1
 
-always @ (posedge CLK) begin
-      cstrt <= ystrt;
-      cnxt  <= nxtline;
-      cwe_r <= cwe0 && sub_y; 
-      caddr_r[2:0]<= cwe0?(caddr_r[2:0]+cwe_r):3'b0;
-      if (cstrt)     caddr_r[6] <= ~bayer_phase[1];
-      else if (cnxt) caddr_r[6] <= ~caddr_r[6];
-      if (cstrt)     caddr_r[5:3] <=3'b0;
-      else if (cnxt) caddr_r[5:3] <=(bayer_phase[1]^caddr_r[6])? caddr_r[5:3]:(caddr_r[5:3]+1);
-end
+
+
+    always @ (posedge CLK) begin
+        cstrt <= ystrt;
+        cnxt  <= nxtline;
+//        cwe_r <= cwe0 && sub_y;
+        cwe_r <= cwe0 && !sel_cbcrmult1;
+        caddr_r[2:0]<= cwe0?(caddr_r[2:0]+cwe_r):3'b0;
+        if (cstrt)     caddr_r[6] <= ~bayer_phase[1];
+        else if (cnxt) caddr_r[6] <= ~caddr_r[6];
+        if (cstrt)     caddr_r[5:3] <=3'b0;
+        else if (cnxt) caddr_r[5:3] <=(bayer_phase[1]^caddr_r[6])? caddr_r[5:3]:(caddr_r[5:3]+1);
+    end
+// extra signals delayed by 1 clock
+    reg ywe_r2, cwe_r2;
+    reg [6:0] caddr_r2;
+    reg [7:0] yaddr_r2;
+    always @ (posedge CLK) begin
+        ywe_r2 <= ywe_r;
+        cwe_r2 <= cwe_r;
+        yaddr_r2 <= yaddr_r;
+        caddr_r2 <= caddr_r;
+    end
+
+
   always @ (posedge CLK) begin
-    y_eq_0   <= (y0[7:0] == 8'h0);
-    y_eq_255 <= (y0[7:0] == 8'hff);
+    y_eq_0   <= (y0_r[7:0] == 8'h0);
+    y_eq_255 <= (y0_r[7:0] == 8'hff);
     if (strt) n000_r[7:0] <= 8'h0;
-    else if ((n000_r[7:0]!=8'hff) && y_eq_0 && ywe_r) n000_r[7:0] <= n000_r[7:0]+1;
+    else if ((n000_r[7:0]!=8'hff) && y_eq_0 && ywe_r2) n000_r[7:0] <= n000_r[7:0]+1;
     if (strt) n255_r[7:0] <= 8'h0;
-    else if ((n255_r[7:0]!=8'hff) && y_eq_255 && ywe_r) n255_r[7:0] <= n255_r[7:0]+1;
+    else if ((n255_r[7:0]!=8'hff) && y_eq_255 && ywe_r2) n255_r[7:0] <= n255_r[7:0]+1;
   end
 
 

ddr3/ddr3.v

@@ -85,7 +85,7 @@
 * 1.69  SPH      03/19/13    Update tZQCS, tZQinit, tZQoper timing parameters
 * 1.70  SPH      04/08/14    Update tRFC to PRECARGE check
 *****************************************************************************************/
-`define den4096Mb 1
+`include "system_defines.vh" 
 // DO NOT CHANGE THE TIMESCALE
 // MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION
 `timescale 1ps / 1ps
@@ -121,6 +121,19 @@ module ddr3 (
     //       to select the correct component density before continuing
     ERROR: You must specify component density with +define+den____Mb.
 `endif
+    initial begin
+        $display ("TCK_MIN = %d", TCK_MIN);
+`ifdef sg15E
+        $display ("sg15E = `sg15E");
+`endif  
+    
+`ifdef sg093                              // sg093  is equivalent to the JEDEC DDR3-2133 (14-14-14) speed bin
+        $display ("sg093");
+`elsif sg15E
+        $display ("sg15E");
+`endif          
+    end
+    
     parameter check_strict_mrbits = 1;
     parameter check_strict_timing = 1;
     parameter feature_pasr = 1;

fpga_version.vh

-      parameter FPGA_VERSION =          32'h0393005c; // 250MHz ???
+      parameter FPGA_VERSION =          32'h03930065; // (same rev) all met,  using "old" (non-inverted) phase - OK (full phase range)
+//      parameter FPGA_VERSION =          32'h03930065; // switch phy_top.v (all met) - OK with inverted phase control (reduced phase range)
+//      parameter FPGA_VERSION =          32'h03930064; // switch mcomtr_sequencer.v  (xclk not met) - wrong!
+//      parameter FPGA_VERSION =          32'h03930063; // switch mcntrl_linear_rw.v (met) good, worse mem valid phases 
+//      parameter FPGA_VERSION =          32'h03930062; // (met)debugging - what was broken (using older versions of some files) - mostly OK (some glitches)
+//      parameter FPGA_VERSION =          32'h03930061; // restored bufr instead of bufio for memory high speed clock
+//      parameter FPGA_VERSION =          32'h03930060; // moving CLK1..3 in memory controller MMCM, keeping CLK0 and FB. Stuck at memory calib 
+//      parameter FPGA_VERSION =          32'h0393005f; // restored mclk back to 200KHz, registers added to csconvert18a
+//      parameter FPGA_VERSION =          32'h0393005e; // trying mclk = 225 MHz (was 200MHz) define MCLK_VCO_MULT 18
+//      parameter FPGA_VERSION =          32'h0393005d; // trying mclk = 250 MHz (was 200MHz) define MCLK_VCO_MULT 20
+//      parameter FPGA_VERSION =          32'h0393005c; // 250MHz OK, no timing violations
 //    parameter FPGA_VERSION =          32'h0393005b; // 250MHz Not tested, timing violation in bit_stuffer_escape: xclk -0.808 -142.047 515
 //    parameter FPGA_VERSION =          32'h0393005a; // Trying xclk = 250MHz - timing viloations in xdct393, but particular hardware works
 //    parameter FPGA_VERSION =          32'h03930059; // 'new' (no pclk2x, no xclk2x  clocks) sensor/converter w/o debug - OK

includes/x393_parameters.vh

@@ -138,7 +138,11 @@
     parameter real REFCLK_FREQUENCY = 200.0, // 300.0,
     parameter HIGH_PERFORMANCE_MODE = "FALSE",
     parameter CLKIN_PERIOD =        20, // 10, //ns >1.25, 600<Fvco<1200 // Hardware 150MHz , change to             | 6.667
+`ifdef MCLK_VCO_MULT    
+    parameter CLKFBOUT_MULT =       `MCLK_VCO_MULT ,
+`else    
     parameter CLKFBOUT_MULT =       16,   // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE  | 16
+`endif    
     parameter CLKFBOUT_MULT_REF =   16,   // 18,   // 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE  | 6
     parameter CLKFBOUT_DIV_REF =    4, // 200Mhz 3, // To get 300MHz for the reference clock
 `else
@@ -150,11 +154,12 @@
     parameter CLKFBOUT_DIV_REF =    3, // To get 300MHz for the reference clock
 `endif    
     parameter DIVCLK_DIVIDE=        1,
+    parameter CLKFBOUT_USE_FINE_PS= 0, //1, // 0 - old, 1 - new 
     parameter CLKFBOUT_PHASE =      0.000,
     parameter SDCLK_PHASE =         0.000,
-    parameter CLK_PHASE =           0.000,
+    parameter CLK_PHASE =           0.000, //11.25, /// 0.000,
     parameter CLK_DIV_PHASE =       0.000,
-    parameter MCLK_PHASE =          90.000,
+    parameter MCLK_PHASE =          90.000, //78.75, // 90.000,
     parameter REF_JITTER1 =         0.010,
     parameter SS_EN =              "FALSE",
     parameter SS_MODE =      "CENTER_HIGH",

includes/x393_tasks_mcntrl_timing.vh

@@ -193,11 +193,19 @@
 
     task axi_set_phase;
         input [PHASE_WIDTH-1:0] phase;
+        reg   [PHASE_WIDTH-1:0] inverted_phase;
         begin
-            $display("SET CLOCK PHASE to 0x%x @ %t",phase,$time);
-            write_contol_register(LD_DLY_PHASE, {{(32-PHASE_WIDTH){1'b0}},phase}); // control regiter address
+            if (CLKFBOUT_USE_FINE_PS) begin
+                inverted_phase = -phase;
+                $display("SET CLOCK INVERTED PHASE (0x%x) to 0x%x @ %t",phase,inverted_phase,$time);
+                write_contol_register(LD_DLY_PHASE, {{(32-PHASE_WIDTH){1'b0}},inverted_phase}); // control regiter address
+                target_phase <= inverted_phase;
+            end else begin
+                $display("SET CLOCK PHASE to 0x%x @ %t",phase,$time);
+                write_contol_register(LD_DLY_PHASE, {{(32-PHASE_WIDTH){1'b0}},phase}); // control regiter address
+                target_phase <= phase;
+            end
             write_contol_register(DLY_SET,0);
-            target_phase <= phase;
         end
     endtask
  

memctrl/mcntrl393.v

@@ -153,6 +153,7 @@ module  mcntrl393 #(
     parameter CLKFBOUT_DIV_REF =    3, // To get 300MHz for the reference clock
 `endif    
     parameter DIVCLK_DIVIDE=        1,
+    parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new 
     parameter CLKFBOUT_PHASE =      0.000,
     parameter SDCLK_PHASE =         0.000,
     parameter CLK_PHASE =           0.000,
@@ -1816,6 +1817,7 @@ module  mcntrl393 #(
         .CLKFBOUT_MULT_REF     (CLKFBOUT_MULT_REF),
         .CLKFBOUT_DIV_REF      (CLKFBOUT_DIV_REF),
         .DIVCLK_DIVIDE         (DIVCLK_DIVIDE),
+        .CLKFBOUT_USE_FINE_PS  (CLKFBOUT_USE_FINE_PS),
         .CLKFBOUT_PHASE        (CLKFBOUT_PHASE),
         .SDCLK_PHASE           (SDCLK_PHASE),
         .CLK_PHASE             (CLK_PHASE),

memctrl/mcntrl_linear_rw.v

@@ -177,6 +177,7 @@ module  mcntrl_linear_rw #(
     reg   [FRAME_HEIGHT_BITS-1:0] line_unfinished_r;
     
     wire                          pre_want;
+    reg                           pre_want_r1;
     wire                    [1:0] status_data;
     wire                    [3:0] cmd_a; 
     wire                   [31:0] cmd_data; 
@@ -324,8 +325,9 @@ module  mcntrl_linear_rw #(
     assign frame_done=  frame_done_r;
     assign frame_finished=  frame_finished_r;
     
-//    assign pre_want=    chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend && !frame_start_r[0];
-    assign pre_want=    chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend && !(|frame_start_r);
+//    assign pre_want=    chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend && !(|frame_start_r);
+    // accelerating pre_want:
+    assign pre_want= pre_want_r1 && !want_r && !xfer_start_r[0] && !suspend ;
 
     assign last_in_row_w=(row_left=={{(FRAME_WIDTH_BITS-NUM_XFER_BITS){1'b0}},xfer_num128_r});
     assign last_row_w=  next_y==window_height;
@@ -407,9 +409,9 @@ module  mcntrl_linear_rw #(
         else if (chn_rst || xfer_grant || start_skip_r)   need_r <= 0;
         else if ((pre_want  || want_r) && (page_cntr>=3)) need_r <= 1; // may raise need if want was already set
 
-        if (mrst)                                                want_r <= 0;
-        else if (chn_rst || xfer_grant || start_skip_r)          want_r <= 0;
-        else if (pre_want && (page_cntr>{1'b0,cmd_extra_pages})) want_r <= 1;
+        if (mrst)                                                  want_r <= 0;
+        else if (chn_rst || xfer_grant || start_skip_r)            want_r <= 0;
+        else if (pre_want && (page_cntr > {1'b0,cmd_extra_pages})) want_r <= 1;
         
     end    
     
@@ -469,6 +471,9 @@ wire    start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
 // now have row start address, bank and row_left ;
 // calculate number to read (min of row_left, maximal xfer and what is left in the DDR3 page    
     always @(posedge mclk) begin
+        // acceletaring pre_want
+        pre_want_r1 <= chn_en &&  !frame_done_r && busy_r && par_mod_r[PAR_MOD_LATENCY-2] && !(|frame_start_r[4:1]) && !last_block;
+    
         if      (mrst)                par_mod_r<=0;
         else if (pgm_param_w ||
                  xfer_start_r[0] ||

memctrl/memctrl16.v

@@ -126,6 +126,7 @@ module  memctrl16 #(
     parameter CLKFBOUT_DIV_REF =    3, // To get 300MHz for the reference clock
 `endif    
     parameter DIVCLK_DIVIDE=        1,
+    parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new 
     parameter CLKFBOUT_PHASE =      0.000,
     parameter SDCLK_PHASE =         0.000,
     parameter CLK_PHASE =           0.000,
@@ -905,6 +906,7 @@ end
         .CLKFBOUT_MULT_REF             (CLKFBOUT_MULT_REF),
         .CLKFBOUT_DIV_REF              (CLKFBOUT_DIV_REF),
         .DIVCLK_DIVIDE                 (DIVCLK_DIVIDE),
+        .CLKFBOUT_USE_FINE_PS          (CLKFBOUT_USE_FINE_PS),
         .CLKFBOUT_PHASE                (CLKFBOUT_PHASE),
         .SDCLK_PHASE                   (SDCLK_PHASE),
         .CLK_PHASE                     (CLK_PHASE),

memctrl/phy/byte_lane.v

@@ -78,7 +78,27 @@ reg        set_r=0;
 reg  dci_disable_dqs_r, dci_disable_dq_r;
 reg  [7:0] ld_odly=8'b0, ld_idly=8'b0;
 reg        ld_odly_dqs,ld_idly_dqs,ld_odly_dm;
-BUFR                          iclk_i    (.O(iclk),.I(dqs_read), .CLR(1'b0),.CE(1'b1)); // OK, works with constraint? Seems now work w/o
+
+BUFR  iclk_i    (.O(iclk),.I(dqs_read), .CLR(1'b0),.CE(1'b1)); // OK, works with constraint? Seems now work w/o
+/*
+wire iclk_int;
+//BUFR     iclk_int_i (.O(iclk_int), .I(dqs_read), .CLR(1'b0),.CE(1'b1));
+    assign iclk_int = dqs_read && !rst;
+BUFIO    iclk_i     (.O(iclk),     .I(iclk_int));
+CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance
+mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dqs_i/iobufs_dqs_i/IBUFDS/IBUFDS_M at N7 (IOB_X1Y120
+since it belongs to a shape containing instance mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/iclk_i.
+The shape requires relative placement between 
+mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dqs_i/iobufs_dqs_i/IBUFDS/IBUFDS_M and
+mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/iclk_i that cannnot be honored because it would result in
+an invalid location for mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/iclk_i. [x393.xdc:193]
+----------
+ERROR: [DRC 23-20] Rule violation (RTSTAT-1) Unrouted net - 2 net(s) are unrouted. The problem bus(es) and/or net(s) are 
+mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/iclk_int,
+mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/iclk_int.
+
+
+*/
 wire [9:0] decode_sel={
     (dly_addr[3:0]==9)?1'b1:1'b0,
     (dly_addr[3:0]==8)?1'b1:1'b0,

memctrl/phy/mcontr_sequencer.v

@@ -80,6 +80,7 @@ module  mcontr_sequencer   #(
     parameter CLKFBOUT_MULT_REF =   9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
     parameter CLKFBOUT_DIV_REF =    3, // To get 300MHz for the reference clock
     parameter DIVCLK_DIVIDE=        1,
+    parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new 
     parameter CLKFBOUT_PHASE =      0.000,
     parameter SDCLK_PHASE =         0.000,
     parameter CLK_PHASE =           0.000,
@@ -551,9 +552,9 @@ module  mcontr_sequencer   #(
         .CLKFBOUT_MULT_REF     (CLKFBOUT_MULT_REF),
         .CLKFBOUT_DIV_REF      (CLKFBOUT_DIV_REF),
         .DIVCLK_DIVIDE         (DIVCLK_DIVIDE),
+        .CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS),
         .CLKFBOUT_PHASE        (CLKFBOUT_PHASE),
         .SDCLK_PHASE           (SDCLK_PHASE), /// debugging
-        
         .CLK_PHASE             (CLK_PHASE),
         .CLK_DIV_PHASE         (CLK_DIV_PHASE),
         .MCLK_PHASE            (MCLK_PHASE),

memctrl/phy/phy_cmd.v

@@ -36,8 +36,9 @@ module  phy_cmd#(
     parameter CLKFBOUT_MULT_REF =   9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
     parameter CLKFBOUT_DIV_REF =    3, // To get 300MHz for the reference clock
     parameter DIVCLK_DIVIDE=        1,
+    parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new 
     parameter CLKFBOUT_PHASE =      0.000,
-    parameter SDCLK_PHASE =          0.000,
+    parameter SDCLK_PHASE =         0.000,
     parameter CLK_PHASE =           0.000,
     parameter CLK_DIV_PHASE =       0.000,
     parameter MCLK_PHASE =          90.000,
@@ -379,6 +380,7 @@ module  phy_cmd#(
         .CLKFBOUT_MULT_REF(CLKFBOUT_MULT_REF),
         .CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
         .DIVCLK_DIVIDE    (DIVCLK_DIVIDE),
+        .CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS),
         .CLKFBOUT_PHASE   (CLKFBOUT_PHASE),
         .SDCLK_PHASE      (SDCLK_PHASE),
         .CLK_PHASE        (CLK_PHASE),

memctrl/phy/phy_top.v

@@ -43,8 +43,9 @@ module  phy_top #(
     parameter CLKFBOUT_MULT_REF =   9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
     parameter CLKFBOUT_DIV_REF =    3, // To get 300MHz for the reference clock
     parameter DIVCLK_DIVIDE=        1,
+    parameter CLKFBOUT_USE_FINE_PS =1, // if 1 move CLKFBOUT_PHASE and SDCLK_PHASE, if 0 - other outputs (moved phases should be 0/same)
     parameter CLKFBOUT_PHASE =      0.000,
-    parameter SDCLK_PHASE =          0.000,
+    parameter SDCLK_PHASE =         0.000,
     parameter CLK_PHASE =           0.000,
     parameter CLK_DIV_PHASE =       0.000,
     parameter MCLK_PHASE =          90.000,  
@@ -312,6 +313,7 @@ wire sdclk; // BUFIO
 // So shifting phase dynamically by plus/- 113 moves SDCLK by a full period (2.5ns) forward and backward (113= 0x71)
 wire clk_pre, clk_div_pre, sdclk_pre, mclk_pre, clk_fb;
 BUFR clk_bufr_i (.O(clk), .CE(), .CLR(), .I(clk_pre));
+//BUFIO clk_buf_i (.O(clk), .I(clk_pre));
 BUFR clk_div_bufr_i (.O(clk_div), .CE(), .CLR(), .I(clk_div_pre));
 BUFIO iclk_bufio_i (.O(sdclk), .I(sdclk_pre) );
 //BUFIO clk_ref_i (.O(ref_clk), .I(clk_ref_pre));
@@ -325,19 +327,21 @@ BUFG mclk_i (.O(mclk),.I(mclk_pre) );
         .BANDWIDTH           (BANDWIDTH),
         .CLKFBOUT_MULT_F     (CLKFBOUT_MULT),
         .DIVCLK_DIVIDE       (DIVCLK_DIVIDE),
-        .CLKFBOUT_PHASE      (CLKFBOUT_PHASE),
-        .CLKOUT0_PHASE       (SDCLK_PHASE),
-        .CLKOUT1_PHASE       (CLK_PHASE),
-        .CLKOUT2_PHASE       (CLK_DIV_PHASE),
-        .CLKOUT3_PHASE       (MCLK_PHASE),
+        .CLKFBOUT_PHASE      (CLKFBOUT_USE_FINE_PS? 0.0 :           CLKFBOUT_PHASE),
+        .CLKOUT0_PHASE       (CLKFBOUT_USE_FINE_PS? 0.0 :           SDCLK_PHASE),
+        .CLKOUT1_PHASE       (CLKFBOUT_USE_FINE_PS? CLK_PHASE :     0.0),
+        .CLKOUT2_PHASE       (CLKFBOUT_USE_FINE_PS? CLK_DIV_PHASE : 0.0),
+        .CLKOUT3_PHASE       (CLKFBOUT_USE_FINE_PS? MCLK_PHASE :   90.000), // (78.75), // (MCLK_PHASE), // should be multiple of 11.25 (90.000/8)
+//ERROR: [DRC 23-20] Rule violation (AVAL-139) Phase shift check - The MMCME2_ADV cell mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i has a fractional CLKOUT3_PHASE value (75.000)  with CLKOUT3_USE_FINE_PS set to FALSE. It should be a multiple of [45 / CLKOUT3_DIVIDE] = [45 / 4] = 11.250.
+        
 //        .CLKOUT4_PHASE          (0.000),
 //        .CLKOUT5_PHASE          (0.000),
 //        .CLKOUT6_PHASE          (0.000),
-        .CLKFBOUT_USE_FINE_PS     ("FALSE"),
-        .CLKOUT0_USE_FINE_PS      ("FALSE"),
-        .CLKOUT1_USE_FINE_PS ("TRUE"),
-        .CLKOUT2_USE_FINE_PS ("TRUE"),
-        .CLKOUT3_USE_FINE_PS ("TRUE"),
+        .CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS? "TRUE" : "FALSE"),
+        .CLKOUT0_USE_FINE_PS  (CLKFBOUT_USE_FINE_PS? "TRUE" : "FALSE"),
+        .CLKOUT1_USE_FINE_PS  (CLKFBOUT_USE_FINE_PS? "FALSE" : "TRUE"),
+        .CLKOUT2_USE_FINE_PS  (CLKFBOUT_USE_FINE_PS? "FALSE" : "TRUE"),
+        .CLKOUT3_USE_FINE_PS  (CLKFBOUT_USE_FINE_PS? "FALSE" : "TRUE"),
 //        .CLKOUT4_USE_FINE_PS("FALSE"),
 //        .CLKOUT5_USE_FINE_PS("FALSE"),
 //        .CLKOUT6_USE_FINE_PS("FALSE"),

py393/import_verilog_parameters.py

@@ -393,6 +393,11 @@ class ImportVerilogParameters(object):
         # Try binary operation 
         # repeat until end of line or ')'
             while True:
+                try:
+                    opStart=skipWS(operand1[2])
+                except:
+                    print("line=\n",line)
+                    print("defines=\n",self.defines)
                 opStart=skipWS(operand1[2])
                 if (opStart == len(line)) : # or (line[opStart] == ')'): # just primary
                     return operand1
@@ -485,7 +490,7 @@ class ImportVerilogParameters(object):
 # Macro substitution excluding the very first character
             if "`" in line [1:]:
                 for define in self.defines:
-                    line.replace("`"+define,self.defines[define])
+                    line = line.replace("`"+define,self.defines[define])
             if line[0]== "`":
                 tokens=line[1:].replace("\t"," ").split(" ",1) #second tokens
                 for i in (1,2): 

py393/vrlg.py

@@ -144,12 +144,13 @@ CMPRS_CBIT_CMODE_MONO6__RAW = str
 MCONTR_PHY_0BIT_DCI_RST = int
 SENSOR_FIFO_2DEPTH = int
 HIGH_PERFORMANCE_MODE__TYPE = str
+PXD_CAPACITANCE__RAW = str
 AFI_LO_ADDR64__TYPE = str
 CAMSYNC_TRIG_DELAY2 = int
 AFI_SIZE64 = int
 LOGGER_CONF_IMU_BITS = int
 SENS_JTAG_TCK__RAW = str
-MCNTRL_SCANLINE_MASK__TYPE = str
+HISPI_DIFF_TERM = str
 MCONTR_PHY_0BIT_SDRST_ACT = int
 SENSI2C_IBUF_LOW_PWR = str
 CLKOUT_DIV_PCLK2X__RAW = str
@@ -176,6 +177,7 @@ CLKFBOUT_PHASE_SENSOR = float
 DFLT_REFRESH_PERIOD = int
 MCONTR_TOP_0BIT_REFRESH_EN__TYPE = str
 NUM_CYCLES_20__TYPE = str
+CMPRS_CSAT_CB__RAW = str
 SENS_JTAG_PGMEN = int
 NUM_CYCLES_03__TYPE = str
 CMPRS_CBIT_RUN_BITS__TYPE = str
@@ -243,6 +245,7 @@ SENSI2C_CMD_RUN_PBITS__TYPE = str
 LOGGER_CONF_SYN_BITS__TYPE = str
 GPIO_ADDR__TYPE = str
 CAMSYNC_TRIG_SRC = int
+SENS_CTRL_GP1__RAW = str
 CLKOUT_DIV_PCLK__TYPE = str
 LOGGER_PAGE_IMU = int
 MEMCLK_IOSTANDARD__RAW = str
@@ -297,6 +300,7 @@ MCONTR_LINTILE_EXTRAPG_BITS__TYPE = str
 SENS_CTRL_RST_MMCM = int
 LOGGER_CONF_EN_BITS__TYPE = str
 CLKIN_PERIOD_PCLK__RAW = str
+MAX_TILE_WIDTH__TYPE = str
 SENS_LENS_POST_SCALE_MASK = int
 BUF_IPCLK2X_SENS1__RAW = str
 SENSOR_MODE_WIDTH__RAW = str
@@ -309,6 +313,7 @@ CMPRS_CBIT_CMODE_JP4DIFF__RAW = str
 CMPRS_AFIMUX_MASK__TYPE = str
 MCONTR_SENS_INC = int
 CAMSYNC_TRIG_PERIOD__TYPE = str
+CMPRS_STATUS_REG_BASE__RAW = str
 DFLT_DQS_PATTERN = int
 SENS_GAMMA_ADDR_DATA__RAW = str
 DLY_LANE1_IDELAY__RAW = str
@@ -335,7 +340,7 @@ DFLT_WBUF_DELAY__RAW = str
 CAMSYNC_POST_MAGIC__RAW = str
 MCNTRL_TEST01_CHN2_MODE__TYPE = str
 NUM_CYCLES_24__RAW = str
-NUM_CYCLES_13__RAW = str
+SENS_REFCLK_FREQUENCY__TYPE = str
 LOGGER_CONF_MSG__RAW = str
 MCNTRL_TILED_STATUS_REG_CHN2_ADDR__RAW = str
 LAST_FRAME_BITS__RAW = str
@@ -367,6 +372,7 @@ MCONTR_CMPRS_STATUS_BASE = int
 BUFFER_DEPTH32 = int
 SENS_CTRL_QUADRANTS__TYPE = str
 SENS_LENS_BY_MASK__RAW = str
+SENS_CTRL_GP0__TYPE = str
 DFLT_REFRESH_ADDR = int
 SENS_LENS_BX_MASK__TYPE = str
 TEST01_SUSPEND__RAW = str
@@ -374,6 +380,7 @@ SENS_GAMMA_HEIGHT01__TYPE = str
 CMPRS_HIFREQ_REG_INC = int
 STATUS_ADDR_MASK__TYPE = str
 MCONTR_TOP_0BIT_ADDR_MASK__RAW = str
+NUM_CYCLES_13__RAW = str
 TEST01_START_FRAME = int
 RTC_SET_USEC__RAW = str
 LOGGER_CONF_SYN_BITS__RAW = str
@@ -402,6 +409,7 @@ NUM_CYCLES_21 = int
 FRAME_FULL_WIDTH__TYPE = str
 CAMSYNC_TRIG_DELAY2__TYPE = str
 CMDFRAMESEQ_REL__TYPE = str
+MAX_TILE_WIDTH__RAW = str
 PICKLE = str
 AFI_SIZE64__TYPE = str
 NUM_CYCLES_LOW_BIT__TYPE = str
@@ -421,9 +429,10 @@ CMPRS_CBIT_DCSUB_BITS__TYPE = str
 AXI_RD_ADDR_BITS__TYPE = str
 CAMSYNC_CHN_EN_BIT__TYPE = str
 CMDFRAMESEQ_ADDR_BASE__RAW = str
+MCONTR_LINTILE_SKIP_LATE__TYPE = str
 DEBUG_ADDR__RAW = str
 CONTROL_ADDR__RAW = str
-SENSI2C_CMD_RESET = int
+TILED_STARTY__RAW = str
 CMPRS_FRMT_MBCM1_BITS__TYPE = str
 SENS_CTRL_QUADRANTS_EN__RAW = str
 NUM_CYCLES_14__TYPE = str
@@ -519,6 +528,7 @@ MCONTR_TOP_16BIT_REFRESH_ADDRESS = int
 HISTOGRAM_RADDR0__TYPE = str
 LOGGER_CONF_SYN_BITS = int
 NUM_CYCLES_19 = int
+SENS_CTRL_GP1__TYPE = str
 MCNTRL_TEST01_MASK__TYPE = str
 SENS_CTRL_QUADRANTS_WIDTH__RAW = str
 SENSOR_FIFO_DELAY__RAW = str
@@ -540,6 +550,7 @@ BUF_IPCLK_SENS1__TYPE = str
 FFCLK0_IFD_DELAY_VALUE__TYPE = str
 MCONTR_TOP_16BIT_ADDR = int
 CMPRS_TIMEOUT = int
+HISPI_IOSTANDARD__TYPE = str
 CMPRS_AFIMUX_RST = int
 NUM_CYCLES_18 = int
 SENS_LENS_POST_SCALE_MASK__RAW = str
@@ -555,10 +566,11 @@ CMPRS_CBIT_BAYER = int
 GPIO_PORTEN__RAW = str
 SLEW_CLK__TYPE = str
 MCONTR_PHY_0BIT_DLY_SET = int
-CLKFBOUT_DIV_REF__RAW = str
+HISPI_DIFF_TERM__TYPE = str
+SENSI2C_CMD_ACIVE_EARLY0 = int
 CMD_PAUSE_BITS = int
 CMPRS_CBIT_CMODE_JP4DIFFHDR__RAW = str
-SENSIO_STATUS_REG_REL = int
+HISPI_IOSTANDARD__RAW = str
 SENSI2C_TBL_SA__TYPE = str
 BUF_IPCLK_SENS3__TYPE = str
 MCNTRL_TILED_MODE = int
@@ -589,6 +601,7 @@ SENSIO_RADDR__TYPE = str
 CLKFBOUT_MULT_PCLK__TYPE = str
 CLK_ADDR__TYPE = str
 CMPRS_FORMAT = int
+SENSIO_STATUS_REG_REL = int
 FFCLK1_CAPACITANCE = str
 CMPRS_CBIT_CMODE_BITS__RAW = str
 CMPRS_TABLES = int
@@ -597,7 +610,7 @@ CMPRS_AFIMUX_RADDR0__RAW = str
 CAMSYNC_EN_BIT = int
 MCONTR_PHY_16BIT_PATTERNS__RAW = str
 HISTOGRAM_RAM_MODE = str
-SENS_REFCLK_FREQUENCY__TYPE = str
+FFCLK1_DQS_BIAS__TYPE = str
 SENS_GAMMA_MODE_EN__RAW = str
 SENSI2C_TBL_SA_BITS__TYPE = str
 DEBUG_ADDR = int
@@ -669,7 +682,7 @@ SENS_LENS_FAT0_OUT_MASK__TYPE = str
 SENSI2C_ABS_RADDR__TYPE = str
 MCONTR_PHY_STATUS_REG_ADDR__TYPE = str
 WBUF_DLY_WLV__TYPE = str
-MEMBRIDGE_WIDTH64__TYPE = str
+HISPI_MSB_FIRST__TYPE = str
 MCONTR_TOP_16BIT_CHN_EN = int
 BUF_IPCLK2X_SENS1__TYPE = str
 DEFAULT_STATUS_MODE = int
@@ -722,6 +735,7 @@ AXI_RD_ADDR_BITS__RAW = str
 RTC_BITC_PREDIV = int
 SENS_SS_MOD_PERIOD__TYPE = str
 BUF_CLK1X_SYNC__RAW = str
+MCONTR_LINTILE_SKIP_LATE__RAW = str
 SENS_JTAG_PGMEN__TYPE = str
 MEMBRIDGE_LEN64__RAW = str
 MCONTR_LINTILE_EN = int
@@ -729,16 +743,19 @@ DFLT_REFRESH_ADDR__RAW = str
 GPIO_N = int
 MCONTR_ARBIT_ADDR_MASK__TYPE = str
 SENS_CTRL_MRST__TYPE = str
+SENS_CTRL_GP0 = int
+SENS_CTRL_GP1 = int
 FFCLK0_IBUF_LOW_PWR__TYPE = str
-FFCLK1_DQS_BIAS__TYPE = str
 SENS_GAMMA_RADDR = int
 NUM_CYCLES_14__RAW = str
-CMPRS_AFIMUX_MASK__RAW = str
+NUM_CYCLES_28__RAW = str
+CLKIN_PERIOD_SENSOR__RAW = str
 PHASE_WIDTH__TYPE = str
 CMPRS_JP4__RAW = str
 CMPRS_HIFREQ_REG_BASE__RAW = str
 SS_MOD_PERIOD = int
 MCONTR_CMPRS_BASE__TYPE = str
+HISPI_CAPACITANCE__TYPE = str
 TEST01_SUSPEND__TYPE = str
 SENS_LENS_POST_SCALE = int
 LOGGER_STATUS_REG_ADDR__TYPE = str
@@ -758,11 +775,13 @@ PHASE_WIDTH = int
 DFLT_DQ_TRI_OFF_PATTERN__TYPE = str
 MCNTRL_SCANLINE_MASK = int
 CLKOUT_DIV_XCLK2X = int
+MCNTRL_TILED_TILE_WHS__TYPE = str
 MULT_SAXI_BSLOG3__TYPE = str
 CLKFBOUT_MULT__RAW = str
 CMPRS_STATUS_REG_INC__RAW = str
 HISTOGRAM_RADDR0__RAW = str
 STATUS_ADDR_MASK = int
+PXD_CAPACITANCE = str
 SENS_LENS_AY = int
 CMPRS_CBIT_CMODE_MONO6__TYPE = str
 HISTOGRAM_RAM_MODE__RAW = str
@@ -778,6 +797,7 @@ NEWPAR__TYPE = str
 CMPRS_AFIMUX_STATUS_CNTRL__TYPE = str
 LOGGER_CONFIG__RAW = str
 LD_DLY_LANE0_ODELAY__RAW = str
+PXD_CLK_DIV_BITS__RAW = str
 CMPRS_FRMT_LMARG_BITS = int
 CMDSEQMUX_ADDR = int
 CLKOUT_DIV_AXIHP = int
@@ -828,6 +848,7 @@ SENSIO_CTRL__TYPE = str
 SENSIO_WIDTH__RAW = str
 CMPRS_MASK__TYPE = str
 MEMBRIDGE_SIZE64__RAW = str
+HISPI_IFD_DELAY_VALUE__RAW = str
 MCNTRL_PS_STATUS_CNTRL = int
 CLKOUT_DIV_SYNC = int