Commits · 2317d4fd0524929d638a091f1ed332ade27ec478 · Elphel / x393

22 Jan, 2021 1 commit
- fixed hargs-boson to load correct bit file · df06bda0
  Andrey Filippov authored 4 years ago
  
  df06bda0
21 Jan, 2021 1 commit
- adding boson · 6e111056
  Andrey Filippov authored 4 years ago
  
  6e111056
19 Apr, 2019 1 commit
- modifying for LWIR sesnor · 0be6290b
  Andrey Filippov authored 5 years ago
  
  0be6290b
02 Nov, 2016 1 commit
- added configuration for multiple initialization steps · 2db3e799
  Andrey Filippov authored 8 years ago
  
  2db3e799
28 Sep, 2016 1 commit
- increased delay after power off · 5455d171
  Andrey Filippov authored 8 years ago
  
  5455d171
04 Sep, 2016 1 commit
- working on memory channels synchronization · 51d9d5ad
  Andrey Filippov authored 8 years ago
  
  51d9d5ad
02 Sep, 2016 1 commit
- all initialization for parallel sensors (will not work with serial!) · 15f593e1
  Andrey Filippov authored 8 years ago
  
  15f593e1
24 Jun, 2016 1 commit
- 1.install imgsrv to /www/pages 2.default bitstream path=/tmp/ · dedb0313
  Oleg Dzhimiev authored 8 years ago
  
  dedb0313
20 Nov, 2015 1 commit
- more paramteres controlled over querry string · d2868135
  Andrey Filippov authored 9 years ago
  
  d2868135
07 Apr, 2015 1 commit
- added save/load state with pickle · 8ffbbc62
  Andrey Filippov authored 10 years ago
  
  8ffbbc62
20 Mar, 2015 1 commit
- chaneged handling of the shared parameters, added defaults and saving modified... · 1902d5ce
  Andrey Filippov authored 10 years ago
```
chaneged handling of the shared parameters, added defaults and saving modified parameters as Verilog include file
```
  1902d5ce
15 Mar, 2015 1 commit
- porting delay scan/adjustment functions from the eddr3 Python code · 6ff31a13
  Andrey Filippov authored 10 years ago
  
  6ff31a13
12 Mar, 2015 1 commit
- working on hardware testing, added utility functions to load bitstream and use GPIO for debugging · 27a6599b
  Andrey Filippov authored 10 years ago
  
  27a6599b