added configuration for multiple initialization steps

2db3e799 · Andrey Filippov · a2f208ee · 2db3e799 · 2db3e799 · 2db3e799
Commit 2db3e799 authored Nov 02, 2016 by Andrey Filippov
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hargs-post-par12 py393/hargs-post-par12 +9 -0

hargs-power-eyesis py393/hargs-power-eyesis +6 -0

hargs-power_par12 py393/hargs-power_par12 +6 -0

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--- a/py393/hargs-post-par12
+++ b/py393/hargs-post-par12
+-d TARGET_MODE=1
+-f /usr/local/verilog/system_defines.vh
+-f /usr/local/verilog/x393_parameters.vh   /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh
+-l /usr/local/verilog/x393_cur_params_target.vh
+-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
+-c bitstream_set_path /usr/local/verilog/x393_parallel.bit
+-c measure_all "*DI"
+-c setSensorClock 24.0 "2V5_LVDS"
+-c set_rtc
--- a/py393/hargs-power-eyesis
+++ b/py393/hargs-power-eyesis
+-d TARGET_MODE=1
+-f /usr/local/verilog/system_defines.vh
+-f /usr/local/verilog/x393_parameters.vh   /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh
+-l /usr/local/verilog/x393_cur_params_target.vh
+-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
+-c setEyesisPower 1
--- a/py393/hargs-power_par12
+++ b/py393/hargs-power_par12
+-d TARGET_MODE=1
+-f /usr/local/verilog/system_defines.vh
+-f /usr/local/verilog/x393_parameters.vh   /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh
+-l /usr/local/verilog/x393_cur_params_target.vh
+-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
+-c setupSensorsPower  "PAR12"  all  0  0.2