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Commit e4592ccb authored by Andrey Filippov's avatar Andrey Filippov
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merged with framepars for the event logger

parents 8555ff12 2723fb28
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Showing with 2187 additions and 136 deletions
.settings/com.elphel.vdt.cocotb.prefs
View file @ e4592ccb
......@@ -4,7 +4,7 @@ cocotb_@_CocotbExtraFiles=glbl.v<-@\#\#@->
cocotb_@_CocotbIncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
cocotb_@_CocotbMODULE=x393_cocotb_server<-@\#\#@->
cocotb_@_CocotbTESTCASE=run_test<-@\#\#@->
cocotb_@_GTKWaveSavFile=x393_cocotb_02.sav
cocotb_@_GTKWaveSavFile=x393_cocotb_03.sav
cocotb_@_GrepFindErr=error|ERROR
cocotb_@_GrepFindErrWarn=error|warning|ERROR|WARNING
cocotb_@_PatternInfo=.*[\\s.](\\w*\\.py)\:([0-9]+)\\s*\\S*\\s*\\S*\\s*(.*)
......
axi/mult_saxi_wr.v
View file @ e4592ccb
......@@ -427,7 +427,9 @@ module mult_saxi_wr #(
.MULT_SAXI_BSLOG3 (MULT_SAXI_BSLOG3)
) mult_saxi_wr_pointers_i (
.mclk (mclk), // input
.mrst (mrst), // input
.aclk (aclk), // input
.arst (arst), // input
.chn_en_mclk (en_chn_mclk), // input[3:0]
.sa_len_di (cmd_data[29:0]), // input[29:0]
.sa_len_wa (cmd_a[2:0]), // input[2:0]
......@@ -549,7 +551,7 @@ module mult_saxi_wr #(
.stb (cmd_stb), // input
.addr (cmd_a), // output[3:0]
.data (cmd_data), // output[31:0]
.we ({cmd_we_sa_len,we_ctrl,irq_log_we}) // output
.we ({irq_log_we,we_ctrl,cmd_we_sa_len}) // output
);
// now - converting all to parallel (TODO: use RAM for multi-word status data)
......
axi/mult_saxi_wr_pointers.v
View file @ e4592ccb
......@@ -45,7 +45,9 @@ module mult_saxi_wr_pointers#(
parameter MULT_SAXI_BSLOG3 = 4
)(
input mclk, // system clock
input mrst, //
input aclk, // global clock to run s_axi (@150MHz?)
input arst, //
input [3:0] chn_en_mclk, // enable this channle ( 0 - reset)
input [29:0] sa_len_di, // input data to write pointers address/data
input [ 2:0] sa_len_wa, // channel address to write sa/lengths
......@@ -57,7 +59,7 @@ module mult_saxi_wr_pointers#(
// provide address and burst length for AXI @aclk, will stay until ackn
output reg [29:0] axi_addr,
output reg [3:0] axi_len,
// write data to external pointre memory (to be read out by PIO) @ aclk
// write data to external pointer memory (to be read out by PIO) @ aclk
// alternatively - read out directly from ptr_ram?
output [29:0] pntr_wd, // @aclk
output [1:0] pntr_wa,
......@@ -92,6 +94,7 @@ module mult_saxi_wr_pointers#(
reg [30:0] ptr_rollover;
reg [4:0] burst_size; // ROM
wire [29:0] ptr_wd;
reg arst_d; //delayed version of arst
assign reset_rq_enc = {reset_rq_pri[3] | reset_rq_pri[2],
reset_rq_pri[3] | reset_rq_pri[1]};
......@@ -134,7 +137,12 @@ module mult_saxi_wr_pointers#(
always @ (posedge aclk) begin
chn_en_aclk <= chn_en_mclk;
reset_rq <= rst_pntr_aclk | (reset_rq & ~({4{resetting[0] &~ resetting[1]}} & reset_rq_pri));
arst_d <= arst; // probably not needed?
if (arst) reset_rq <= ~0; // or ~0 ? Add auto reset after
// else reset_rq <= {4{arst_d}} | rst_pntr_aclk | (reset_rq & ~({4{resetting[0] &~ resetting[1]}} & reset_rq_pri));
else reset_rq <= rst_pntr_aclk | (reset_rq & ~({4{resetting[0] &~ resetting[1]}} & reset_rq_pri));
if (start_resetting_w) reset_rq_pri <= {reset_rq[3] & ~(|reset_rq[2:0]),
reset_rq[2] & ~(|reset_rq[1:0]),
reset_rq[1] & ~reset_rq[0],
......
cocotb/x393_cocotb_03.sav
View file @ e4592ccb
This diff is collapsed.
cocotb/x393_cocotb_server.py
View file @ e4592ccb
......@@ -140,7 +140,16 @@ class X393_cocotb_server(object):
data_bytes = 4,
autoflush = self.autoflush,
blatency = 5)
#event logger from FPGA
self.saxigp1 = SAXIWrSim (entity = dut,
name = "saxigp1",
clock = dut.saxi0_aclk,
mempath = self.mempath,
memhigh = self.memhigh,
data_bytes = 4,
autoflush = self.autoflush,
blatency = 5)
level = logging.DEBUG if debug else logging.INFO # WARNING
self.dut._log.info('Set debug level '+str(level)+", debug="+str(debug))
......@@ -150,6 +159,7 @@ class X393_cocotb_server(object):
self.saxihp0w.log.setLevel(level)
self.saxihp1w.log.setLevel(level)
self.saxigp0.log.setLevel(level)
self.saxigp1.log.setLevel(level)
#Initialize socket
self.PORT = port
......@@ -208,6 +218,7 @@ class X393_cocotb_server(object):
self.saxihp0w_thread = cocotb.fork(self.saxihp0w.saxi_wr_run())
self.saxihp1w_thread = cocotb.fork(self.saxihp1w.saxi_wr_run())
self.saxigp0_thread = cocotb.fork(self.saxigp0.saxi_wr_run())
self.saxigp1_thread = cocotb.fork(self.saxigp1.saxi_wr_run())
self.soc_conn.send(self.cmd.toJSON(0)+"\n")
self.dut._log.debug('Sent 0 to the socket')
started=True
......
cocotb/x393_dut.v
View file @ e4592ccb
This diff is collapsed.
fpga_version.vh
View file @ e4592ccb
......@@ -35,7 +35,8 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h039300c0; //parallel - chnaging LOGGER_PAGE_IMU 3->0 (how it was in 353) -0.044/16, 79.59%
parameter FPGA_VERSION = 32'h039300c1; //parallel - modified after troubleshooting simulation -0.069/41, 79.90 %
// parameter FPGA_VERSION = 32'h039300c0; //parallel - changing LOGGER_PAGE_IMU 3->0 (how it was in 353) -0.044/16, 79.59%
// parameter FPGA_VERSION = 32'h039300bf; //parallel - mask extrenal timestamps mode -0.043/17 79.56%
// parameter FPGA_VERSION = 32'h039300be; //parallel - adding odd/even pixels shift -0.066/12, 80.26%
// parameter FPGA_VERSION = 32'h039300bd; //hispi, trying the same -0.173/36, 80.95%
......
logger/event_logger.v
View file @ e4592ccb
......@@ -92,7 +92,8 @@ module event_logger#(
// byte-parallel timestamps from 4 sensors channels (in triggered mode all are the same, different only in free running mode)
// each may generate logger event, channel number encoded in bits 25:24 of the external microseconds
input [3:0] sof_mclk, // start of frame (per-channel) to filter out non-first timestamps
input ts_stb_chn0, // @mclk 1 clock before ts_rcv_data is valid
input [7:0] ts_data_chn0, // @mclk byte-wide serialized timestamp message received or local
......@@ -123,19 +124,19 @@ module event_logger#(
wire sda, sda_en, scl, scl_en;
reg [6:0] ctrl_addr=7'h0; // 0 - period, 1 - reserved, 2..31 - registers to log, >32 - gps parameters, >64 - odometer message
reg we_d; // only if wa was 0
reg we_imu;
reg we_gps;
reg we_period;
reg we_bit_duration;
reg we_message;
reg we_config_imu; // bits 1:0, 2 - enable slot[1:0]
reg we_config_gps; // bits 6:3, 7 - enable - {ext,invert, slot[1:0]} slot==0 - disable
reg we_config_msg; // bits 12:8,13 - enable - {invert,extinp[3:0]} extinp[3:0]=='hf' - disable
reg we_config_syn; // bit 14, 15 - enable - enable logging external timestamps
reg we_config_rst; // bit 14, 15 - enable - enable logging external timestamps
reg we_config_debug; // bit 14, 15 - enable - enable logging external timestamps
reg we_bitHalfPeriod;
reg we_d = 0; // only if wa was 0
reg we_imu = 0;
reg we_gps = 0;
reg we_period = 0;
reg we_bit_duration = 0;
reg we_message = 0;
reg we_config_imu = 0; // bits 1:0, 2 - enable slot[1:0]
reg we_config_gps = 0; // bits 6:3, 7 - enable - {ext,invert, slot[1:0]} slot==0 - disable
reg we_config_msg = 0; // bits 12:8,13 - enable - {invert,extinp[3:0]} extinp[3:0]=='hf' - disable
reg we_config_syn = 0; // bit 14, 15 - enable - enable logging external timestamps
reg we_config_rst = 0; // bit 14, 15 - enable - reset
reg we_config_debug = 0; // bit 14, 15 - enable - debug bits set
reg we_bitHalfPeriod = 0;
reg [1:0] config_imu;
......@@ -159,7 +160,7 @@ module event_logger#(
reg [3:0] config_gps_mclk;
reg [4:0] config_msg_mclk;
reg [3:0] config_syn_mclk;
reg config_rst_mclk;
reg config_rst_mclk = 0;
reg [3:0] config_debug_mclk;
reg [15:0] bitHalfPeriod_mclk;
......@@ -211,6 +212,8 @@ module event_logger#(
reg [31:0] cmd_data_r; // valid next after cmd_we;
wire cmd_we;
wire cmd_status;
reg [3:0] timestamps_en; // enable timestamp to go through (first after sof)
assign ext_en = {{(GPIO_N-5){1'b0}},
(config_imu[1:0]==2'h2)?1'b1:1'b0,
......@@ -241,6 +244,9 @@ module event_logger#(
assign timestamp_request[1]=config_gps[3]? (config_gps[2]?nmea_sent_start:gps_ts_stb):gps_pulse1sec_single;
always @ (posedge mclk) begin
timestamps_en <= enable_syn_mclk & (sof_mclk | (timestamps_en & ~{ts_stb_chn3, ts_stb_chn2,ts_stb_chn1, ts_stb_chn0}));
end
// filter gps_pulse1sec
always @ (posedge xclk) begin
......@@ -257,9 +263,25 @@ module event_logger#(
gps_pulse1sec_single <= !gps_pulse1sec_denoise[1] && gps_pulse1sec_denoise[0];
end
// always @ (posedge mclk or posedge mrst) begin // was negedge
always @ (posedge mclk) begin // was negedge
if (cmd_we) cmd_data_r <= cmd_data; // valid next after cmd_we;
we_d <= !mrst && cmd_we && !cmd_a;
we_imu <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:5] == LOGGER_PAGE_IMU);
we_gps <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:5] == LOGGER_PAGE_GPS);
we_message <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:5] == LOGGER_PAGE_MSG);
we_period <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_PERIOD);
we_bit_duration <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_BIT_DURATION);
we_bitHalfPeriod<= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_BIT_HALF_PERIOD);
we_config_imu <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_IMU];
we_config_gps <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_GPS];
we_config_msg <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_MSG];
we_config_syn <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_SYN];
we_config_rst <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_EN];
we_config_debug <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_DBG];
end
always @ (posedge mclk) begin // was negedge
if (cmd_we) cmd_data_r <= cmd_data; // valid next after cmd_we;
/*
we_d <= cmd_we && !cmd_a;
we_imu <= cmd_we && !cmd_a && (ctrl_addr[6:5] == LOGGER_PAGE_IMU);
we_gps <= cmd_we && !cmd_a && (ctrl_addr[6:5] == LOGGER_PAGE_GPS);
......@@ -273,6 +295,7 @@ module event_logger#(
we_config_syn <= cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_SYN];
we_config_rst <= cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_EN];
we_config_debug <= cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_DBG];
*/
if (we_config_imu) config_imu_mclk[1:0] <= cmd_data_r[LOGGER_CONF_IMU - 1 -: LOGGER_CONF_IMU_BITS]; // bits 1:0, 2 - enable slot[1:0]
if (we_config_gps) config_gps_mclk[3:0] <= cmd_data_r[LOGGER_CONF_GPS - 1 -: LOGGER_CONF_GPS_BITS]; // bits 6:3, 7 - enable - {ext,inver, slot[1:0]} slot==0 - disable
......@@ -400,24 +423,24 @@ fixed-length de-noise circuitry with latency 256*T(xclk) (~3usec)
/* logs frame synchronization data from other camera (same as frame sync) */
// ts_stb (mclk) -> trig)
imu_exttime393 i_imu_exttime(
// .rst (rst), // input global reset
.mclk (mclk), // system clock, negedge
.xclk (xclk), // half frequency (80 MHz nominal)
.mrst (mrst), // @mclk - sync reset
.xrst (xrst), // @xclk - sync reset
.en_chn_mclk (enable_syn_mclk), // enable module operation, if 0 - reset
.ts_stb_chn0 (ts_stb_chn0), // input
.ts_data_chn0 (ts_data_chn0), // input[7:0]
.ts_stb_chn1 (ts_stb_chn1), // input
.ts_data_chn1 (ts_data_chn1), // input[7:0]
.ts_stb_chn2 (ts_stb_chn2), // input
.ts_data_chn2 (ts_data_chn2), // input[7:0]
.ts_stb_chn3 (ts_stb_chn3), // input
.ts_data_chn3 (ts_data_chn3), // input[7:0]
.ts (timestamp_request[2]), // timestamop request
.rdy (channel_ready[2]), // data ready
.rd_stb (channel_next[2]), // data read strobe (increment address)
.rdata (extts_data[15:0])); // data out (16 bits)
// .rst (rst), // input global reset
.mclk (mclk), // system clock, negedge
.xclk (xclk), // half frequency (80 MHz nominal)
.mrst (mrst), // @mclk - sync reset
.xrst (xrst), // @xclk - sync reset
.en_chn_mclk (enable_syn_mclk), // input[3:0] enable module operation, if 0 - reset
.ts_stb_chn0 (ts_stb_chn0 && timestamps_en[0]), // input
.ts_data_chn0 (ts_data_chn0), // input[7:0]
.ts_stb_chn1 (ts_stb_chn1 && timestamps_en[1]), // input
.ts_data_chn1 (ts_data_chn1), // input[7:0]
.ts_stb_chn2 (ts_stb_chn2 && timestamps_en[2]), // input
.ts_data_chn2 (ts_data_chn2), // input[7:0]
.ts_stb_chn3 (ts_stb_chn3 && timestamps_en[3]), // input
.ts_data_chn3 (ts_data_chn3), // input[7:0]
.ts (timestamp_request[2]), // timestamop request
.rdy (channel_ready[2]), // data ready
.rd_stb (channel_next[2]), // data read strobe (increment address)
.rdata (extts_data[15:0])); // data out (16 bits)
imu_timestamps393 i_imu_timestamps (
.xclk (xclk), // 80 MHz, posedge
......
logger/imu_exttime393.v
View file @ e4592ccb
......@@ -67,21 +67,23 @@ module imu_exttime393(
output ts, // timestamop request
output reg rdy, // data ready will go up with timestamp request (ahead of actual time), but it will
// anyway be ready sooner, than the local timestamp retrieved ant sent
input rd_stb, // data read strobe (increment address) - continuous 1'b1 until allthe packet is read out
input rd_stb, // data read strobe (increment address) - continuous 1'b1 until all the packet is read out
output [15:0] rdata); // data out (16 bits)
reg [ 4:0] raddr;
reg [ 2:0] raddr; // 2 bits for the address, 1 - overflow
wire en_mclk = |en_chn_mclk;
wire [3:0] ts_stb = {ts_stb_chn3, ts_stb_chn2, ts_stb_chn1, ts_stb_chn0};
wire [3:0] ts_got; // timestamp transferred to the channel FIFO
reg en;
reg rd_stb_r;
reg rd_start; // 1 xclk pulse at the readout start
wire rd_start_mclk;
reg ts_full; // internal 4 x 16 fifo is full (or getting full)
reg ts_pend; // ts fifo waiting to be rdead out
reg [3:0] in_full; // input fifo has (or is acquiring) timestamp
wire pre_copy_w;
reg [1:0] copy_selected; // copying from the winner of 4 input fifos to the x16 output fifo
reg [1:0] copy_selected; // copying from the winner of 4 input FIFOs to the x16 output fifo
reg copy_started;
reg [2:0] copy_cntr; // byte counter for copying
reg [1:0] sel_chn; // selected channel
......@@ -90,11 +92,12 @@ module imu_exttime393(
wire [3:0] chn_pri_w;
wire [1:0] chn_enc_w;
reg [15:0] ts_ram [0:3]; // inner timestamp x16 memory that receives timestamp from one of the 4 input channel fifos
reg [15:0] ts_ram [0:3]; // inner timestamp x16 memory that receives timestamp from one of the 4 input channel FIFOs
wire [31:0] dout_chn;
wire [7:0] copy_data; // data from the selected input fifos
reg [7:0] copy_data_r; // low byte of the timestamp data being copied from one of the input fifos to the ts_ram
reg [7:0] copy_data_r; // low byte of the timestamp data being copied from one of the input FIFOs to the ts_ram
reg rd_stb_mclk;
wire xfer_done_mclk; // valiud information (4 words) are sent out, may start new arbitration
assign chn_pri_w = {in_full[3] & ~(|in_full[2:0]),
in_full[2] & ~(|in_full[1:0]),
in_full[1] & ~in_full[0],
......@@ -102,7 +105,8 @@ module imu_exttime393(
assign chn_enc_w = {chn_pri_w[3] | chn_pri_w[2],
chn_pri_w[3] | chn_pri_w[1]};
assign pre_copy_w = (|in_full) && !copy_selected[0] && !ts_full;
// assign pre_copy_w = (|in_full) && !copy_selected[0] && !ts_full;
assign pre_copy_w = (|in_full) && !copy_selected[0] && !ts_full && !rd_stb_mclk;
assign copy_data = dout_chn[sel_chn * 8 +: 8]; // 4:1 mux
// acquire external timestamps @ mclk
......@@ -110,14 +114,25 @@ module imu_exttime393(
always @ (posedge mclk) begin
copy_started <= pre_copy_started;
if (!en_mclk) ts_full <= 0;
else if (pre_copy_started) ts_full <= 1; // turns on before in_full[*] - || will have no glitches
else if (rd_start_mclk) ts_full <= 0;
rd_stb_mclk <= rd_stb;
if (!en_mclk) ts_full <= 0;
else if (pre_copy_started) ts_full <= 1; // turns on before in_full[*] - || will have no glitches
// else if (rd_start_mclk) ts_full <= 0;
// else if (!ts_pend && !rd_stb_mclk) ts_full <= 0;
else if (xfer_done_mclk) ts_full <= 0;
if (!en_mclk) ts_pend <= 0;
else if (pre_copy_started) ts_pend <= 1;
else if (rd_stb_mclk) ts_pend <= 0;
if (!en_mclk) in_full <= 0;
else in_full <= en_chn_mclk & (ts_stb | (in_full & ~(chn1hot & {4{copy_started}})));
else in_full <= en_chn_mclk & (ts_got | (in_full & ~(chn1hot & {4{copy_started}})));
copy_selected <= {copy_selected[0], pre_copy_w | (copy_selected[0] & ~(&copy_cntr[2:1]))}; // off at count 6
// copy_selected <= {copy_selected[0], (|en_chn_mclk) & (pre_copy_w | (copy_selected[0] & ~(&copy_cntr[2:1])))}; // off at count 6
copy_selected <= {copy_selected[0], (|en_chn_mclk) & (pre_copy_w | (copy_selected[0] & (copy_cntr[2] | ~copy_cntr[1] )))}; // off at count 2
if (pre_copy_w) sel_chn <= chn_enc_w;
......@@ -137,14 +152,18 @@ module imu_exttime393(
en <= en_mclk;
rd_stb_r <= rd_stb;
rd_start <= en && rd_stb && ! rd_stb_r;
if (!en || ts) raddr[4:0] <= 5'h0;
else if (rd_stb) raddr[4:0] <= raddr[4:0] + 1;
if (!en || ts) raddr <= 0;
else if (rd_stb && !raddr[2]) raddr <= raddr + 1;
if (!en) rdy <= 1'b0;
else if (ts) rdy <= 1'b1; // too early, but it will become ready in time, before the local timestamp
else if (rd_stb && (raddr[1:0]==2'h3)) rdy <= 1'b0;
end
dly_var #(.WIDTH(1),.DLY_WIDTH(4)) ts_got0_i (.clk(mclk),.rst(~en_chn_mclk[0]), .dly(4'h7), .din(ts_stb[0]),.dout(ts_got[0]));
dly_var #(.WIDTH(1),.DLY_WIDTH(4)) ts_got1_i (.clk(mclk),.rst(~en_chn_mclk[1]), .dly(4'h7), .din(ts_stb[1]),.dout(ts_got[1]));
dly_var #(.WIDTH(1),.DLY_WIDTH(4)) ts_got2_i (.clk(mclk),.rst(~en_chn_mclk[2]), .dly(4'h7), .din(ts_stb[2]),.dout(ts_got[2]));
dly_var #(.WIDTH(1),.DLY_WIDTH(4)) ts_got3_i (.clk(mclk),.rst(~en_chn_mclk[3]), .dly(4'h7), .din(ts_stb[3]),.dout(ts_got[3]));
timestamp_fifo timestamp_fifo_chn0_i (
......@@ -155,7 +174,7 @@ module imu_exttime393(
.din (ts_data_chn0), // input[7:0]
.aclk (mclk), // input
.arst (mrst), // input
.advance (ts_stb[0]), // enough time
.advance (ts_got[0]), // enough time
.rclk (mclk), // input
.rrst (mrst), // input
.rstb (pre_copy_started && (sel_chn == 2'h0)),// input
......@@ -170,7 +189,7 @@ module imu_exttime393(
.din (ts_data_chn1), // input[7:0]
.aclk (mclk), // input
.arst (mrst), // input
.advance (ts_stb[1]), // enough time
.advance (ts_got[1]), // enough time
.rclk (mclk), // input
.rrst (mrst), // input
.rstb (pre_copy_started && (sel_chn == 2'h1)),// input
......@@ -185,7 +204,7 @@ module imu_exttime393(
.din (ts_data_chn2), // input[7:0]
.aclk (mclk), // input
.arst (mrst), // input
.advance (ts_stb[2]), // enough time
.advance (ts_got[2]), // enough time
.rclk (mclk), // input
.rrst (mrst), // input
.rstb (pre_copy_started && (sel_chn == 2'h2)),// input
......@@ -200,7 +219,7 @@ module imu_exttime393(
.din (ts_data_chn3), // input[7:0]
.aclk (mclk), // input
.arst (mrst), // input
.advance (ts_stb[3]), // enough time
.advance (ts_got[3]), // enough time
.rclk (mclk), // input
.rrst (mrst), // input
.rstb (pre_copy_started && (sel_chn == 2'h3)),// input
......@@ -208,10 +227,13 @@ module imu_exttime393(
);
pulse_cross_clock i_rd_start_mclk (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(rd_start), .out_pulse(rd_start_mclk),.busy());
// pulse_cross_clock i_rd_start_mclk (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(rd_start), .out_pulse(rd_start_mclk),.busy());
pulse_cross_clock i_rd_start_mclk (.rst(!en), .src_clk(xclk), .dst_clk(mclk), .in_pulse(rd_start), .out_pulse(rd_start_mclk),.busy());
pulse_cross_clock i_xfer_done_mclk (.rst(!en), .src_clk(xclk), .dst_clk(mclk), .in_pulse(raddr[1:0]==2'h3), .out_pulse(xfer_done_mclk),.busy());
//
// generate timestamp request as soon as one of the sub-channels starts copying. That time stamp will be stored for this (ext) channel
pulse_cross_clock i_ts (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(pre_copy_w), .out_pulse(ts),.busy());
// pulse_cross_clock i_ts (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(pre_copy_w), .out_pulse(ts),.busy());
pulse_cross_clock i_ts (.rst(en_chn_mclk == 0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(pre_copy_w), .out_pulse(ts),.busy());
endmodule
logger/imu_message393.v
View file @ e4592ccb
......@@ -81,11 +81,11 @@ module imu_message393 (
ts_r <= !trig_denoise[1] && trig_denoise[0];
if (!en || ts_r) raddr[4:0] <= 5'h0;
if (!en || ts_r) raddr[4:0] <= 5'h0;
else if (rd_stb) raddr[4:0] <= raddr[4:0] + 1;
if (ts_r || (rd_stb && (raddr[4:0]==5'h1b)) || !en) rdy_r <= 1'b0;
else if (trig_denoise[1] && !trig_denoise[0]) rdy_r <= 1'b1;
else if (trig_denoise[1] && !trig_denoise[0]) rdy_r <= 1'b1;
end
reg [31:0] odbuf0_ram[0:15];
......
logger/imu_spi393.v
View file @ e4592ccb
......@@ -40,25 +40,24 @@
module imu_spi393(
// input rst,
input mclk, // system clock, negedge TODO:COnvert to posedge!
input xclk, // half frequency (80 MHz nominal)
input we_ra, // write enable for registers to log (@negedge clk)
input we_div,// write enable for clock dividing(@negedge clk)
input we_period,// write enable for IMU cycle period(@negedge clk) 0 - disable, 1 - single, >1 - half bit periods
input [ 4:0] wa, // write address for register (5 bits, @negedge clk)
input [31:0] din, //
output mosi, // to IMU, bit 2 in J9
input miso, // from IMU, bit 3 on J9
input mclk, // system clock, negedge TODO:COnvert to posedge!
input xclk, // half frequency (80 MHz nominal)
input we_ra, // write enable for registers to log (@negedge clk)
input we_div, // write enable for clock dividing(@negedge clk)
input we_period, // write enable for IMU cycle period(@negedge clk) 0 - disable, 1 - single, >1 - half bit periods
input [ 4:0] wa, // write address for register (5 bits, @negedge clk)
input [31:0] din, //
output mosi, // to IMU, bit 2 in J9
input miso, // from IMU, bit 3 on J9
input [ 3:0] config_debug, // bit 0 - long sda_en
output sda, // sda, shared with i2c, bit 1
output sda_en, // enable sda output (when sda==0 and 1 cycle after sda 0->1)
output scl, // scl, shared with i2c, bit 0
output scl_en, // enable scl output (when scl==0 and 1 cycle after sda 0->1)
output ts, // timestamop request
output rdy, // data ready
input rd_stb, // data read strobe (increment address)
output [15:0] rdata); // data out (16 bits)
output sda, // sda, shared with i2c, bit 1
output sda_en, // enable sda output (when sda==0 and 1 cycle after sda 0->1)
output scl, // scl, shared with i2c, bit 0
output scl_en, // enable scl output (when scl==0 and 1 cycle after sda 0->1)
output ts, // timestamp request
output rdy, // data ready
input rd_stb, // data read strobe (increment address)
output [15:0] rdata); // data out (16 bits)
/*
input mclk; // system clock, negedge
input xclk; // half frequency (80 MHz nominal)
......@@ -115,14 +114,14 @@ module imu_spi393(
reg imu_start;
reg ts_r; // delay imu_start by one cycle, so it will be after rdy is reset
reg [31:0] period; // 0 - disable, 1 - single, >1 - period in 50 ns steps
reg [31:0] period=0; // 0 - disable, 1 - single, >1 - period in 50 ns steps
// reg [15:0] di_d;
reg imu_enabled_mclk;
reg imu_enabled_mclk = 0;
reg [1:0] imu_enabled=2'h0;
reg imu_run_mclk;
reg imu_run_mclk = 0;
reg [1:0] imu_run;
reg imu_when_ready_mclk;
reg imu_when_ready_mclk = 0;
reg [1:0] imu_when_ready;
reg imu_run_confirmed;
......@@ -184,7 +183,7 @@ module imu_spi393(
if (we_period) period[31:0] <= din[31:0];
if (we_timer[2]) imu_run_mclk <= (period[31:1]!=31'b0); // double-cycle
if (we_timer[3]) imu_enabled_mclk <= imu_run_mclk | period[0];
if (we_timer[3]) imu_enabled_mclk <= imu_run_mclk | period[0]; // NC393: Why period[0]?
if (we_timer[2]) imu_when_ready_mclk <= &period[31:16]; // double-cycle
......@@ -317,8 +316,8 @@ module imu_spi393(
sngl_wire_stb[2:0] <={sngl_wire_stb[1:0], en & ((scl_r[0] ^ pre_scl) | end_prepare)};
if (!en) sngl_wire_r[0]<=1'b0;
else if ((pre_scl ^scl_r[0]) | end_prepare) sngl_wire_r[0]<=1'b1;
if (!en) sngl_wire_r[0]<=1'b0;
else if ((pre_scl ^scl_r[0]) | end_prepare) sngl_wire_r[0]<=1'b1;
else if (!mosi_reg[15] || sngl_wire_stb[2] || scl_r[0]) sngl_wire_r[0]<=1'b0;
......
logger/logger_arbiter393.v
View file @ e4592ccb
......@@ -39,9 +39,9 @@
`timescale 1ns/1ps
module logger_arbiter393(
input xclk, // half frequency (80 MHz nominal)
input rst, // module reset (sync)
input [3:0] ts_rq_in, // in requests for timestamp (single-cycle - just leading edge )
input xclk, // half frequency (80 MHz nominal)
input rst, // module reset (sync)
input [3:0] ts_rq_in, // in requests for timestamp (single-cycle - just leading edge )
output [3:0] ts_rq, // out request for timestamp, to timestmp module
input [3:0] ts_grant, // granted ts requests from timestamping module
input [3:0] rdy, // channels ready (leading edge - became ready, trailing - no more data, use zero)
......@@ -98,7 +98,7 @@ module logger_arbiter393(
always @ (posedge xclk) begin
ts_rq_in_d[3:0] <= ts_rq_in[3:0];
if (rst) channel_r[1:0] <= 0;
if (wstart) channel_r[1:0] <= {chn1hot[3] | chn1hot[2],chn1hot[3] | chn1hot[1]};
if (wstart) chn_servicing[3:0] <= {chn1hot[3:1], ~|chn1hot[3:1]};
......@@ -109,7 +109,7 @@ module logger_arbiter393(
else ts_rq_r[3:0] <= ~ts_grant & ( wts_rq[3:0] | ts_rq_r[3:0]);
if (rst) ts_valid[3:0] <= 4'h0;
else ts_valid[3:0] <= (ts_grant[3:0] | (ts_valid & ~wts_rq[3:0]));
else ts_valid[3:0] <= (ts_grant[3:0] | (ts_valid & ~wts_rq[3:0]));
channels_ready[3:0] <= ts_valid[3:0] & rdy[3:0] & ~chn_servicing[3:0]; // ready should go down during servicing
......
logger/nmea_decoder393.v
View file @ e4592ccb
......@@ -201,7 +201,7 @@ module nmea_decoder393(
if (restart) vfy_first_comma <= 1'b0;
else if (stb[3] && msb) vfy_first_comma <= last_vfy_sent;
if (restart) valid <= 1'b1; // ready @ stb[2]
if (restart) valid <= 1'b1; // ready @ stb[2]
else if (stb[1] && (ser_di!=gp_exp_bit) &&
(vfy_dollar || vfy_gp || vfy_first_comma || (vfy_sel_sent && !lsbs5))) valid <= 1'b0;
......@@ -292,14 +292,14 @@ module nmea_decoder393(
assign rdata[11: 8] = odbuf2_ram[raddr[4:0]];
assign rdata[15:12] = odbuf3_ram[raddr[4:0]];
reg [3:0] gpxxx_ram[0:3];
reg [3:0] gpxxx_ram[0:15];
always @ (posedge mclk) if (we & ~wa[4]) gpxxx_ram[wa[3:0]] <= wd[3:0];
assign gpxxx_w_one[3:0] = gpxxx_ram[gpxxx_addr[3:0]];
// for each of the four sentences first byte - number of field (<=24), next 3 bytes - formats for each nmea filed (LSB first):
// for each of the four sentences first byte - number of field (<=24), next 3 bytes - formats for each nmea field (LSB first):
// 0 - nibble ("-" -> 0xd, "." -> 0xe), terminated with 0xf
// 1 - byte (2 nibbles), all bytes but last have MSB clear, last - set.
// No padding of nibbles to byte borders, bytes are encoded as 2 nibbles
reg [7:0] format_ram[0:3];
reg [7:0] format_ram[0:15];
always @ (posedge mclk) if (we & wa[4]) format_ram[wa[3:0]] <= wd[7:0];
assign format_data[7:0] = format_ram[{sentence[1:0],format_field[4:3]}];
......
py393/test_mcntrl.py
View file @ e4592ccb
......@@ -77,6 +77,7 @@ import x393_rtc
import x393_jpeg
import vrlg
import x393_export_c
import x393_logger
__all__ = []
__version__ = 0.1
__date__ = '2015-03-01'
......@@ -358,6 +359,8 @@ USAGE
x393Rtc = x393_rtc.X393Rtc(verbose,args.simulated,args.localparams)
x393Jpeg = x393_jpeg.X393Jpeg(verbose,args.simulated,args.localparams)
x393ExportC= x393_export_c.X393ExportC(verbose,args.simulated,args.localparams)
x393Logger = x393_logger.X393Logger(verbose,args.simulated,args.localparams)
#X393Logger
'''
print ("----------------------")
print("x393_mem.__dict__="+str(x393_mem.__dict__))
......@@ -392,6 +395,7 @@ USAGE
extractTasks(x393_rtc.X393Rtc, x393Rtc)
extractTasks(x393_jpeg.X393Jpeg, x393Jpeg)
extractTasks(x393_export_c.X393ExportC, x393ExportC)
extractTasks(x393_logger.X393Logger, x393Logger)
for cmdLine in commands:
print ('Running task: '+str(cmdLine))
......
py393/x393_jpeg.py
View file @ e4592ccb
......@@ -2160,6 +2160,118 @@ jpeg_sim_multi 4
jpeg_sim_multi 8
################## Simulate Parallel 11 - external trigger ####################
./py393/test_mcntrl.py @py393/cocoargs --simulated=localhost:7777
measure_all "*DI"
setup_all_sensors True None 0xf
set_sensor_io_ctl all None None 1 # Set ARO low - check if it is still needed?
#just testing
set_gpio_ports 1 1 # enable software gpio pins and porta (camsync)
set_gpio_pins 0 1 # pin 0 low, pin 1 - high
set_logger_params_file "/home/eyesis/git/x393-neon/attic/imu_config.bin"
set_camsync_period 31 # set bit duration
set_camsync_period 8000 # 80 usec
set_camsync_delay 0 400
set_camsync_delay 1 100
set_camsync_delay 2 200
set_camsync_delay 3 300
#set_camsync_inout <is_out> <bit_number> <active_positive>
set_camsync_inout 1 8 0
#set_camsync_inout 0 7 0
reset_camsync_inout 0 # start with internal trigger
#set_camsync_mode <en=None> <en_snd=None> <en_ts_external=None> <triggered_mode=None> <master_chn=None> <chn_en=None>
set_camsync_mode 1 1 1 1 0 0xf
set_sensor_histogram_window 0 0 4 4 25 21
set_sensor_histogram_window 1 0 4 4 41 21
set_sensor_histogram_window 2 0 4 4 25 41
set_sensor_histogram_window 3 0 4 4 41 41
r
read_control_register 0x430
read_control_register 0x431
write_cmd_frame_sequencer 0 1 2 0x600 0x48 # compressor q page = 1 // too late for frame 2
set_qtables 0 0 80
set_qtables 0 1 70
#irq coming, image not changing - yes
write_cmd_frame_sequencer 0 1 1 0x686 0x280005 #save 4 more lines than sensor has
write_cmd_frame_sequencer 0 1 1 0x680 0x5507 #enable abort
#write_cmd_frame_sequencer 0 1 1 0x6c6 0x300006 #save 4 more lines that compressor has
write_cmd_frame_sequencer 0 1 2 0x600 0x5 #stop compressor `
write_cmd_frame_sequencer 0 1 2 0x680 0x5405 # stop sensor memory (+0) // sensor memory should be controlled first, (9 commands
write_cmd_frame_sequencer 0 1 2 0x6c0 0x5c49 # stop compressor memory (+0)
write_cmd_frame_sequencer 0 1 3 0x686 0x240005 # correct lines
write_cmd_frame_sequencer 0 1 3 0x680 0x5507 # run sensor memory (+1) Can not be 0
write_cmd_frame_sequencer 0 1 4 0x686 0x280005 #save 4 more lines than sensor has
write_cmd_frame_sequencer 0 1 4 0x6c6 0x300006 #save more lines than compressor needs (sensor provides)
write_cmd_frame_sequencer 0 1 4 0x6c0 0x7d4b # run compressor memory (+2)
write_cmd_frame_sequencer 0 1 4 0x600 0x7 # run compressor (+0)
write_cmd_frame_sequencer 0 1 1 0x600 0x48 # compressor q page = 1
write_cmd_frame_sequencer 0 1 4 0x600 0x40 # compressor q page = 0
read_control_register 0x431
read_control_register 0x430
#testing histograms
write_control_register 0x409 0xc0
#set_sensor_io_dly_hispi all 0x48 0x68 0x68 0x68 0x68
#set_sensor_io_ctl all None None None None None 1 None # load all delays?
compressor_control all None None None None None 2
compressor_interrupt_control all clr
compressor_interrupt_control all en
compressor_control all 3
r
read_status 0x21
r
jpeg_sim_multi 4
r
read_status 0x21
r
jpeg_sim_multi 3
r
read_status 0x21
r
write_cmd_frame_sequencer 0 1 1 0x686 0x240005 # correct lines
write_cmd_frame_sequencer 0 1 1 0x6c6 0x200006 # correct lines
write_cmd_frame_sequencer 0 1 1 0x680 0x5507 # run sensor memory, update frame#, reset buffers
write_cmd_frame_sequencer 0 1 1 0x6c0 0x7d4b # run compressor memory
write_cmd_frame_sequencer 0 1 1 0x600 0x7 # run compressor
#switch to external (wired) trigger
set_camsync_inout 0 7 0
jpeg_sim_multi 4
###switch to external (wired) trigger
##set_camsync_inout 0 7 0
jpeg_sim_multi 4
#set_camsync_mode <en=None> <en_snd=None> <en_ts_external=None> <triggered_mode=None> <master_chn=None> <chn_en=None>
#keeping external trigger mode (#9 was switching to internal)
#set_camsync_mode None None None 0
jpeg_sim_multi 4
jpeg_sim_multi 8
################## Serial ####################
cd /usr/local/verilog/; test_mcntrl.py @hargs
......
py393/x393_logger.py 0 → 100644
View file @ e4592ccb
This diff is collapsed.
x393.v
View file @ e4592ccb
......@@ -2314,7 +2314,8 @@ assign axi_grst = axi_rst_pre;
.ts_local_data (ts_logegr_data), // input[7:0]
.ext_di (gpio_rd), // input[9:0]
.ext_do (gpio_logger), // output[9:0]
.ext_en (gpio_logger_en), // output[9:0]
.ext_en (gpio_logger_en), // output[9:0]
.sof_mclk (sof_out_mclk), // input[3:0]
.ts_stb_chn0 (ts_pre_stb[0]), // input
.ts_data_chn0 (ts_data[0 * 8 +: 8]), // input[7:0]
.ts_stb_chn1 (ts_pre_stb[1]), // input
......
x393_parallel.bit
View file @ e4592ccb
No preview for this file type
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