Commit e4592ccb authored by Andrey Filippov's avatar Andrey Filippov
Browse files

merged with framepars for the event logger

parents 8555ff12 2723fb28
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+1 −1
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@@ -4,7 +4,7 @@ cocotb_@_CocotbExtraFiles=glbl.v<-@\#\#@->
cocotb_@_CocotbIncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
cocotb_@_CocotbMODULE=x393_cocotb_server<-@\#\#@->
cocotb_@_CocotbTESTCASE=run_test<-@\#\#@->
cocotb_@_GTKWaveSavFile=x393_cocotb_02.sav
cocotb_@_GTKWaveSavFile=x393_cocotb_03.sav
cocotb_@_GrepFindErr=error|ERROR
cocotb_@_GrepFindErrWarn=error|warning|ERROR|WARNING
cocotb_@_PatternInfo=.*[\\s.](\\w*\\.py)\:([0-9]+)\\s*\\S*\\s*\\S*\\s*(.*)
+3 −1
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@@ -427,7 +427,9 @@ module mult_saxi_wr #(
        .MULT_SAXI_BSLOG3   (MULT_SAXI_BSLOG3)
    ) mult_saxi_wr_pointers_i (
        .mclk         (mclk),           // input
        .mrst         (mrst),           // input
        .aclk         (aclk),           // input
        .arst         (arst),           // input
        .chn_en_mclk  (en_chn_mclk),    // input[3:0] 
        .sa_len_di    (cmd_data[29:0]), // input[29:0] 
        .sa_len_wa    (cmd_a[2:0]),     // input[2:0] 
@@ -549,7 +551,7 @@ module mult_saxi_wr #(
        .stb         (cmd_stb),                           // input
        .addr        (cmd_a),                             // output[3:0] 
        .data        (cmd_data),                          // output[31:0] 
        .we          ({cmd_we_sa_len,we_ctrl,irq_log_we}) // output
        .we          ({irq_log_we,we_ctrl,cmd_we_sa_len}) // output
    );
    
    // now - converting all to parallel (TODO: use RAM for multi-word status data)
+10 −2
Original line number Diff line number Diff line
@@ -45,7 +45,9 @@ module mult_saxi_wr_pointers#(
    parameter MULT_SAXI_BSLOG3 =          4
)(
    input                         mclk,             // system clock
    input                         mrst,             //
    input                         aclk,             // global clock to run s_axi (@150MHz?)
    input                         arst,             //
    input                   [3:0] chn_en_mclk,      // enable this channle ( 0 - reset)
    input                  [29:0] sa_len_di,        // input data to write pointers address/data
    input                  [ 2:0] sa_len_wa,        // channel address to write sa/lengths
@@ -57,7 +59,7 @@ module mult_saxi_wr_pointers#(
    // provide address and burst length for AXI @aclk, will stay until ackn
    output reg             [29:0] axi_addr,
    output reg              [3:0] axi_len,
    // write data to external pointre memory (to be read out by PIO) @ aclk
    // write data to external pointer memory (to be read out by PIO) @ aclk
    // alternatively - read out directly from ptr_ram?
    output                 [29:0] pntr_wd, // @aclk
    output                  [1:0] pntr_wa,
@@ -92,6 +94,7 @@ module mult_saxi_wr_pointers#(
    reg  [30:0] ptr_rollover;
    reg   [4:0] burst_size;             // ROM
    wire [29:0] ptr_wd;
    reg         arst_d;                 //delayed version of arst
    
    assign reset_rq_enc = {reset_rq_pri[3] | reset_rq_pri[2],
                           reset_rq_pri[3] | reset_rq_pri[1]};
@@ -134,7 +137,12 @@ module mult_saxi_wr_pointers#(
    
    always @ (posedge aclk) begin
        chn_en_aclk <= chn_en_mclk;
        reset_rq <= rst_pntr_aclk | (reset_rq  & ~({4{resetting[0] &~ resetting[1]}} & reset_rq_pri));        
        arst_d <= arst; // probably not needed?
        
        if (arst) reset_rq <= ~0; // or ~0 ? Add auto reset after
//        else      reset_rq <= {4{arst_d}} | rst_pntr_aclk | (reset_rq  & ~({4{resetting[0] &~ resetting[1]}} & reset_rq_pri));
        else      reset_rq <= rst_pntr_aclk | (reset_rq  & ~({4{resetting[0] &~ resetting[1]}} & reset_rq_pri));
                
        if (start_resetting_w)  reset_rq_pri <= {reset_rq[3] & ~(|reset_rq[2:0]),
                                                 reset_rq[2] & ~(|reset_rq[1:0]),
                                                 reset_rq[1] &     ~reset_rq[0],
+1033 −35

File changed.

Preview size limit exceeded, changes collapsed.

+12 −1
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@@ -140,6 +140,15 @@ class X393_cocotb_server(object):
                                    data_bytes = 4,
                                    autoflush =  self.autoflush,
                                    blatency =   5)
        #event logger from FPGA
        self.saxigp1 =   SAXIWrSim (entity =     dut,
                                    name =       "saxigp1",
                                    clock =      dut.saxi0_aclk,
                                    mempath =    self.mempath,
                                    memhigh =    self.memhigh,
                                    data_bytes = 4,
                                    autoflush =  self.autoflush,
                                    blatency =   5)

        level = logging.DEBUG if debug else logging.INFO # WARNING
        self.dut._log.info('Set debug level '+str(level)+", debug="+str(debug))
@@ -150,6 +159,7 @@ class X393_cocotb_server(object):
        self.saxihp0w.log.setLevel(level)
        self.saxihp1w.log.setLevel(level)
        self.saxigp0.log.setLevel(level)
        self.saxigp1.log.setLevel(level)
        
        #Initialize socket
        self.PORT = port
@@ -208,6 +218,7 @@ class X393_cocotb_server(object):
            self.saxihp0w_thread = cocotb.fork(self.saxihp0w.saxi_wr_run())    
            self.saxihp1w_thread = cocotb.fork(self.saxihp1w.saxi_wr_run())    
            self.saxigp0_thread =  cocotb.fork(self.saxigp0.saxi_wr_run())    
            self.saxigp1_thread =  cocotb.fork(self.saxigp1.saxi_wr_run())    
            self.soc_conn.send(self.cmd.toJSON(0)+"\n")
            self.dut._log.debug('Sent 0 to the socket')
            started=True
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