Skip to content

X
x393
Commit e4592ccb authored by Andrey Filippov's avatar Andrey Filippov
Browse files
Options

merged with framepars for the event logger

parents 8555ff12 2723fb28
Hide whitespace changes
Inline Side-by-side
Showing with 2187 additions and 136 deletions
.settings/com.elphel.vdt.cocotb.prefs
View file @ e4592ccb
......@@ -4,7 +4,7 @@ cocotb_@_CocotbExtraFiles=glbl.v<-@\#\#@->
cocotb_@_CocotbIncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
cocotb_@_CocotbMODULE=x393_cocotb_server<-@\#\#@->
cocotb_@_CocotbTESTCASE=run_test<-@\#\#@->
cocotb_@_GTKWaveSavFile=x393_cocotb_02.sav
cocotb_@_GTKWaveSavFile=x393_cocotb_03.sav
cocotb_@_GrepFindErr=error|ERROR
cocotb_@_GrepFindErrWarn=error|warning|ERROR|WARNING
cocotb_@_PatternInfo=.*[\\s.](\\w*\\.py)\:([0-9]+)\\s*\\S*\\s*\\S*\\s*(.*)
......
axi/mult_saxi_wr.v
View file @ e4592ccb
......@@ -427,7 +427,9 @@ module mult_saxi_wr #(
.MULT_SAXI_BSLOG3 (MULT_SAXI_BSLOG3)
) mult_saxi_wr_pointers_i (
.mclk (mclk), // input
.mrst (mrst), // input
.aclk (aclk), // input
.arst (arst), // input
.chn_en_mclk (en_chn_mclk), // input[3:0]
.sa_len_di (cmd_data[29:0]), // input[29:0]
.sa_len_wa (cmd_a[2:0]), // input[2:0]
......@@ -549,7 +551,7 @@ module mult_saxi_wr #(
.stb (cmd_stb), // input
.addr (cmd_a), // output[3:0]
.data (cmd_data), // output[31:0]
.we ({cmd_we_sa_len,we_ctrl,irq_log_we}) // output
.we ({irq_log_we,we_ctrl,cmd_we_sa_len}) // output
);
// now - converting all to parallel (TODO: use RAM for multi-word status data)
......
axi/mult_saxi_wr_pointers.v
View file @ e4592ccb
......@@ -45,7 +45,9 @@ module mult_saxi_wr_pointers#(
parameter MULT_SAXI_BSLOG3 = 4
)(
input mclk, // system clock
input mrst, //
input aclk, // global clock to run s_axi (@150MHz?)
input arst, //
input [3:0] chn_en_mclk, // enable this channle ( 0 - reset)
input [29:0] sa_len_di, // input data to write pointers address/data
input [ 2:0] sa_len_wa, // channel address to write sa/lengths
......@@ -57,7 +59,7 @@ module mult_saxi_wr_pointers#(
// provide address and burst length for AXI @aclk, will stay until ackn
output reg [29:0] axi_addr,
output reg [3:0] axi_len,
// write data to external pointre memory (to be read out by PIO) @ aclk
// write data to external pointer memory (to be read out by PIO) @ aclk
// alternatively - read out directly from ptr_ram?
output [29:0] pntr_wd, // @aclk
output [1:0] pntr_wa,
......@@ -92,6 +94,7 @@ module mult_saxi_wr_pointers#(
reg [30:0] ptr_rollover;
reg [4:0] burst_size; // ROM
wire [29:0] ptr_wd;
reg arst_d; //delayed version of arst
assign reset_rq_enc = {reset_rq_pri[3] | reset_rq_pri[2],
reset_rq_pri[3] | reset_rq_pri[1]};
......@@ -134,7 +137,12 @@ module mult_saxi_wr_pointers#(
always @ (posedge aclk) begin
chn_en_aclk <= chn_en_mclk;
reset_rq <= rst_pntr_aclk | (reset_rq & ~({4{resetting[0] &~ resetting[1]}} & reset_rq_pri));
arst_d <= arst; // probably not needed?
if (arst) reset_rq <= ~0; // or ~0 ? Add auto reset after
// else reset_rq <= {4{arst_d}} | rst_pntr_aclk | (reset_rq & ~({4{resetting[0] &~ resetting[1]}} & reset_rq_pri));
else reset_rq <= rst_pntr_aclk | (reset_rq & ~({4{resetting[0] &~ resetting[1]}} & reset_rq_pri));
if (start_resetting_w) reset_rq_pri <= {reset_rq[3] & ~(|reset_rq[2:0]),
reset_rq[2] & ~(|reset_rq[1:0]),
reset_rq[1] & ~reset_rq[0],
......
cocotb/x393_cocotb_03.sav
View file @ e4592ccb
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Thu Sep 29 06:48:24 2016
[*] Mon Oct 24 00:30:16 2016
[*]
[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20160928204209937.fst"
[dumpfile_mtime] "Thu Sep 29 04:17:10 2016"
[dumpfile_size] 406908202
[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20161023171014405.fst"
[dumpfile_mtime] "Mon Oct 24 00:23:04 2016"
[dumpfile_size] 364619214
[savefile] "/home/eyesis/git/x393-neon/cocotb/x393_cocotb_03.sav"
[timestart] 282452000
[timestart] 0
[size] 1814 1171
[pos] 1920 0
*-18.670311 283500000 271290000 271540000 118460000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[pos] 0 0
*-26.593010 46043333 53094051 136169617 216213845 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_dut.
[treeopen] x393_dut.simul_sensor12bits_2_i.
[treeopen] x393_dut.simul_sensor12bits_3_i.
[treeopen] x393_dut.simul_sensor12bits_i.
[treeopen] x393_dut.x393_i.
[treeopen] x393_dut.x393_i.compressor393_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.
[treeopen] x393_dut.x393_i.sensors393_i.
[treeopen] x393_dut.x393_i.event_logger_i.i_imu_exttime.
[treeopen] x393_dut.x393_i.event_logger_i.i_imu_exttime.timestamp_fifo_chn0_i.
[treeopen] x393_dut.x393_i.event_logger_i.i_imu_spi.
[treeopen] x393_dut.x393_i.event_logger_i.i_logger_arbiter.
[treeopen] x393_dut.x393_i.event_logger_i.i_nmea_decoder.
[treeopen] x393_dut.x393_i.event_logger_i.i_rs232_rcv.
[treeopen] x393_dut.x393_i.mult_saxi_wr_i.
[treeopen] x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.
......@@ -34,15 +40,14 @@
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_parallel12_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_sync_i.
[treeopen] x393_dut.x393_i.timing393_i.
[treeopen] x393_dut.x393_i.timing393_i.camsync393_i.
[sst_width] 461
[signals_width] 299
[sst_width] 398
[signals_width] 323
[sst_expanded] 1
[sst_vpaned_height] 487
[sst_vpaned_height] 486
@820
x393_dut.TEST_TITLE[639:0]
@800200
@c00200
-SENSOR0
@28
x393_dut.simul_sensor12bits_i.MRST
......@@ -70,7 +75,7 @@ x393_dut.simul_sensor12bits_i.state[3:0]
x393_dut.simul_sensor12bits_i.stated[3:0]
@8022
x393_dut.simul_sensor12bits_i.cntr[15:0]
@1000200
@1401200
-SENSOR0
@c00200
-SENSOR1
......@@ -85,7 +90,7 @@ x393_dut.simul_sensor12bits_2_i.HACT
x393_dut.simul_sensor12bits_2_i.stopped
@1401200
-SENSOR1
@800200
@c00200
-SENSOR2
@28
x393_dut.simul_sensor12bits_3_i.arst1
......@@ -111,7 +116,7 @@ x393_dut.simul_sensor12bits_3_i.state[3:0]
x393_dut.simul_sensor12bits_3_i.stated[3:0]
@8022
x393_dut.simul_sensor12bits_3_i.cntr[15:0]
@1000200
@1401200
-SENSOR2
@c00200
-SENSOR3
......@@ -126,7 +131,7 @@ x393_dut.simul_sensor12bits_4_i.HACT
x393_dut.simul_sensor12bits_4_i.stopped
@1401200
-SENSOR3
@800200
@c00200
-ARO
@c00022
x393_dut.x393_i.sensors393_i.sns_ctl[3:0]
......@@ -137,7 +142,7 @@ x393_dut.x393_i.sensors393_i.sns_ctl[3:0]
(3)x393_dut.x393_i.sensors393_i.sns_ctl[3:0]
@1401200
-group_end
@800200
@c00200
-chn0
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.aro
......@@ -153,9 +158,9 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_paral
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.pclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.ibpf
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.bpf
@1000200
@1401200
-chn0
@800200
@c00200
-chn1
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_parallel12_i.aro
......@@ -166,9 +171,9 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_sync_
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_sync_i.sof_in
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.vact_to_fifo
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_parallel12_i.vact
@1000200
@1401200
-chn1
@800200
@c00200
-chn2
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sens_parallel12_i.aro
......@@ -186,9 +191,9 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sens_paral
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sens_parallel12_i.pclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sens_parallel12_i.ibpf
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sens_parallel12_i.bpf
@1000200
@1401200
-chn2
@800200
@c00200
-chn3
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_parallel12_i.aro
......@@ -200,7 +205,7 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_sync_
x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_sync_i.eof_in
x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.vact_to_fifo
x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_parallel12_i.vact
@1000200
@1401200
-chn3
@800200
-sens_sync
......@@ -208,8 +213,9 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_paral
-
@1000200
-sens_sync
@1401200
-ARO
@800200
@c00200
-clocks
@28
x393_dut.x393_i.pclk
......@@ -245,8 +251,9 @@ x393_dut.x393_i.timing393_i.rtc393_i.refclk2x_mclk
-
@1000200
-rtc
@1401200
-clocks
@800200
@c00200
-synchronization
@28
x393_dut.x393_i.timing393_i.camsync393_i.cmd_we
......@@ -704,7 +711,6 @@ x393_dut.x393_i.timing393_i.camsync393_i.pre_rcv_error
x393_dut.x393_i.timing393_i.camsync393_i.pclk
@22
x393_dut.x393_i.timing393_i.camsync393_i.bit_length_plus1[7:0]
@23
x393_dut.x393_i.timing393_i.camsync393_i.bit_snd_counter[5:0]
@200
-ts_compressor
......@@ -718,9 +724,9 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.ts_pre_stb
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.ts_rstb
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.ts_dout[7:0]
@1000200
@1401200
-synchronization
@800200
@c00200
-interrupts
@800022
x393_dut.x393_i.cmprs_irq[3:0]
......@@ -743,9 +749,9 @@ x393_dut.x393_i.sata_irq
-other_irqs
@200
-
@1000200
@1401200
-interrupts
@800200
@c00200
- cmd
@22
x393_dut.x393_i.cmd_root_ad[7:0]
......@@ -763,7 +769,7 @@ x393_dut.x393_i.axiwr_waddr[13:0]
x393_dut.x393_i.axiwr_wen
@22
x393_dut.x393_i.axiwr_wdata[31:0]
@1000200
@1401200
- cmd
@800200
-i2c
......@@ -771,9 +777,1001 @@ x393_dut.x393_i.axiwr_wdata[31:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.rpointer[5:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.wpage0[3:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.page_r[3:0]
@1000200
-i2c
@c00200
-gpio
@800022
x393_dut.x393_i.gpio393_i.io_pins[9:0]
@28
(0)x393_dut.x393_i.gpio393_i.io_pins[9:0]
(1)x393_dut.x393_i.gpio393_i.io_pins[9:0]
(2)x393_dut.x393_i.gpio393_i.io_pins[9:0]
(3)x393_dut.x393_i.gpio393_i.io_pins[9:0]
(4)x393_dut.x393_i.gpio393_i.io_pins[9:0]
(5)x393_dut.x393_i.gpio393_i.io_pins[9:0]
[color] 2
(6)x393_dut.x393_i.gpio393_i.io_pins[9:0]
(7)x393_dut.x393_i.gpio393_i.io_pins[9:0]
(8)x393_dut.x393_i.gpio393_i.io_pins[9:0]
(9)x393_dut.x393_i.gpio393_i.io_pins[9:0]
@1001200
-group_end
@800022
x393_dut.x393_i.gpio393_i.ext_pins[9:0]
@28
(0)x393_dut.x393_i.gpio393_i.ext_pins[9:0]
(1)x393_dut.x393_i.gpio393_i.ext_pins[9:0]
(2)x393_dut.x393_i.gpio393_i.ext_pins[9:0]
(3)x393_dut.x393_i.gpio393_i.ext_pins[9:0]
(4)x393_dut.x393_i.gpio393_i.ext_pins[9:0]
(5)x393_dut.x393_i.gpio393_i.ext_pins[9:0]
(6)x393_dut.x393_i.gpio393_i.ext_pins[9:0]
(7)x393_dut.x393_i.gpio393_i.ext_pins[9:0]
(8)x393_dut.x393_i.gpio393_i.ext_pins[9:0]
(9)x393_dut.x393_i.gpio393_i.ext_pins[9:0]
@1001200
-group_end
@1401200
-gpio
@800200
-event_logger
@200
-x393
@800022
x393_dut.x393_i.sof_out_mclk[3:0]
@28
(0)x393_dut.x393_i.sof_out_mclk[3:0]
(1)x393_dut.x393_i.sof_out_mclk[3:0]
(2)x393_dut.x393_i.sof_out_mclk[3:0]
(3)x393_dut.x393_i.sof_out_mclk[3:0]
@1001200
-group_end
@800022
x393_dut.x393_i.ts_pre_stb[3:0]
@28
(0)x393_dut.x393_i.ts_pre_stb[3:0]
(1)x393_dut.x393_i.ts_pre_stb[3:0]
(2)x393_dut.x393_i.ts_pre_stb[3:0]
(3)x393_dut.x393_i.ts_pre_stb[3:0]
@1001200
-group_end
@c00022
x393_dut.x393_i.event_logger_i.ext_di[9:0]
@28
(0)x393_dut.x393_i.event_logger_i.ext_di[9:0]
(1)x393_dut.x393_i.event_logger_i.ext_di[9:0]
(2)x393_dut.x393_i.event_logger_i.ext_di[9:0]
(3)x393_dut.x393_i.event_logger_i.ext_di[9:0]
(4)x393_dut.x393_i.event_logger_i.ext_di[9:0]
(5)x393_dut.x393_i.event_logger_i.ext_di[9:0]
(6)x393_dut.x393_i.event_logger_i.ext_di[9:0]
(7)x393_dut.x393_i.event_logger_i.ext_di[9:0]
(8)x393_dut.x393_i.event_logger_i.ext_di[9:0]
(9)x393_dut.x393_i.event_logger_i.ext_di[9:0]
@1401200
-group_end
@c00022
x393_dut.x393_i.event_logger_i.ext_do[9:0]
@28
(0)x393_dut.x393_i.event_logger_i.ext_do[9:0]
(1)x393_dut.x393_i.event_logger_i.ext_do[9:0]
(2)x393_dut.x393_i.event_logger_i.ext_do[9:0]
(3)x393_dut.x393_i.event_logger_i.ext_do[9:0]
(4)x393_dut.x393_i.event_logger_i.ext_do[9:0]
(5)x393_dut.x393_i.event_logger_i.ext_do[9:0]
(6)x393_dut.x393_i.event_logger_i.ext_do[9:0]
(7)x393_dut.x393_i.event_logger_i.ext_do[9:0]
(8)x393_dut.x393_i.event_logger_i.ext_do[9:0]
(9)x393_dut.x393_i.event_logger_i.ext_do[9:0]
@1401200
-group_end
@c00022
x393_dut.x393_i.event_logger_i.ext_en[9:0]
@28
(0)x393_dut.x393_i.event_logger_i.ext_en[9:0]
(1)x393_dut.x393_i.event_logger_i.ext_en[9:0]
(2)x393_dut.x393_i.event_logger_i.ext_en[9:0]
(3)x393_dut.x393_i.event_logger_i.ext_en[9:0]
(4)x393_dut.x393_i.event_logger_i.ext_en[9:0]
(5)x393_dut.x393_i.event_logger_i.ext_en[9:0]
(6)x393_dut.x393_i.event_logger_i.ext_en[9:0]
(7)x393_dut.x393_i.event_logger_i.ext_en[9:0]
(8)x393_dut.x393_i.event_logger_i.ext_en[9:0]
(9)x393_dut.x393_i.event_logger_i.ext_en[9:0]
x393_dut.x393_i.event_logger_i.config_rst
x393_dut.x393_i.event_logger_i.enable_gps
@22
x393_dut.x393_i.event_logger_i.bitHalfPeriod_mclk[15:0]
@28
x393_dut.x393_i.event_logger_i.we_bitHalfPeriod
x393_dut.x393_i.event_logger_i.mrst
x393_dut.x393_i.event_logger_i.mclk
x393_dut.x393_i.event_logger_i.cmd_we
x393_dut.x393_i.event_logger_i.we_period
@c00200
-imu_spi393
@28
x393_dut.x393_i.event_logger_i.i_imu_spi.config_single_wire
x393_dut.x393_i.event_logger_i.i_imu_spi.sngl_wire_r[1:0]
x393_dut.x393_i.event_logger_i.i_imu_spi.sngl_wire
x393_dut.x393_i.event_logger_i.i_imu_spi.pre_scl
@c00028
x393_dut.x393_i.event_logger_i.i_imu_spi.scl_r[1:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_imu_spi.scl_r[1:0]
(1)x393_dut.x393_i.event_logger_i.i_imu_spi.scl_r[1:0]
@1401200
-group_end
@28
x393_dut.x393_i.event_logger_i.i_imu_spi.end_prepare
@c08022
x393_dut.x393_i.event_logger_i.i_imu_spi.seq_state[1:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_imu_spi.seq_state[1:0]
(1)x393_dut.x393_i.event_logger_i.i_imu_spi.seq_state[1:0]
@1401200
-group_end
@8022
x393_dut.x393_i.event_logger_i.i_imu_spi.seq_counter[9:0]
@28
x393_dut.x393_i.event_logger_i.i_imu_spi.imu_enabled_mclk
x393_dut.x393_i.event_logger_i.i_imu_spi.imu_start_mclk
x393_dut.x393_i.event_logger_i.i_imu_spi.imu_start
x393_dut.x393_i.event_logger_i.i_imu_spi.ts
@c00022
x393_dut.x393_i.event_logger_i.i_imu_spi.config_debug[3:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_imu_spi.config_debug[3:0]
(1)x393_dut.x393_i.event_logger_i.i_imu_spi.config_debug[3:0]
(2)x393_dut.x393_i.event_logger_i.i_imu_spi.config_debug[3:0]
(3)x393_dut.x393_i.event_logger_i.i_imu_spi.config_debug[3:0]
@1401200
-group_end
@28
x393_dut.x393_i.event_logger_i.i_imu_spi.imu_when_ready_mclk
x393_dut.x393_i.event_logger_i.i_imu_spi.imu_when_ready[1:0]
x393_dut.x393_i.event_logger_i.i_imu_spi.imu_start_first
@22
x393_dut.x393_i.event_logger_i.i_imu_spi.we_timer[4:1]
@28
x393_dut.x393_i.event_logger_i.i_imu_spi.en
@c00028
x393_dut.x393_i.event_logger_i.i_imu_spi.imu_enabled[1:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_imu_spi.imu_enabled[1:0]
(1)x393_dut.x393_i.event_logger_i.i_imu_spi.imu_enabled[1:0]
@1401200
-group_end
@28
x393_dut.x393_i.event_logger_i.i_imu_spi.imu_enabled_mclk
x393_dut.x393_i.event_logger_i.i_imu_spi.imu_run_mclk
@22
x393_dut.x393_i.event_logger_i.i_imu_spi.period[31:0]
@28
x393_dut.x393_i.event_logger_i.i_imu_spi.we_period
@800022
x393_dut.x393_i.event_logger_i.i_imu_spi.we_timer[4:1]
@28
(0)x393_dut.x393_i.event_logger_i.i_imu_spi.we_timer[4:1]
(1)x393_dut.x393_i.event_logger_i.i_imu_spi.we_timer[4:1]
(2)x393_dut.x393_i.event_logger_i.i_imu_spi.we_timer[4:1]
(3)x393_dut.x393_i.event_logger_i.i_imu_spi.we_timer[4:1]
@c00022
x393_dut.x393_i.event_logger_i.i_imu_spi.clk_en[3:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_imu_spi.clk_en[3:0]
(1)x393_dut.x393_i.event_logger_i.i_imu_spi.clk_en[3:0]
(2)x393_dut.x393_i.event_logger_i.i_imu_spi.clk_en[3:0]
(3)x393_dut.x393_i.event_logger_i.i_imu_spi.clk_en[3:0]
@1401200
-group_end
@28
x393_dut.x393_i.event_logger_i.i_imu_spi.clk_div[1:0]
x393_dut.x393_i.event_logger_i.i_imu_spi.en
x393_dut.x393_i.event_logger_i.i_imu_spi.mclk
@1001200
-group_end
@200
-
@1401200
-imu_spi393
-group_end
@c00200
-rs232_rcvr
@28
x393_dut.x393_i.axi_aclk
@c00200
-task_send_serial_bit
@28
x393_dut.RS232_SENDING_BYTE
x393_dut.RS232_SENDING_PAUSE
@22
[color] 6
x393_dut.send_serial_bit.d[7:0]
[color] 6
x393_dut.send_serial_bit.data_byte[7:0]
@c00022
x393_dut.send_serial_line.char
@28
(0)x393_dut.send_serial_line.char
(1)x393_dut.send_serial_line.char
(2)x393_dut.send_serial_line.char
(3)x393_dut.send_serial_line.char
(4)x393_dut.send_serial_line.char
(5)x393_dut.send_serial_line.char
(6)x393_dut.send_serial_line.char
(7)x393_dut.send_serial_line.char
(8)x393_dut.send_serial_line.char
(9)x393_dut.send_serial_line.char
(10)x393_dut.send_serial_line.char
(11)x393_dut.send_serial_line.char
(12)x393_dut.send_serial_line.char
(13)x393_dut.send_serial_line.char
(14)x393_dut.send_serial_line.char
(15)x393_dut.send_serial_line.char
(16)x393_dut.send_serial_line.char
(17)x393_dut.send_serial_line.char
(18)x393_dut.send_serial_line.char
(19)x393_dut.send_serial_line.char
(20)x393_dut.send_serial_line.char
(21)x393_dut.send_serial_line.char
(22)x393_dut.send_serial_line.char
(23)x393_dut.send_serial_line.char
(24)x393_dut.send_serial_line.char
(25)x393_dut.send_serial_line.char
(26)x393_dut.send_serial_line.char
(27)x393_dut.send_serial_line.char
(28)x393_dut.send_serial_line.char
(29)x393_dut.send_serial_line.char
(30)x393_dut.send_serial_line.char
(31)x393_dut.send_serial_line.char
@1401200
-group_end
-task_send_serial_bit
@28
x393_dut.x393_i.event_logger_i.i_rs232_rcv.xclk
@200
-
@28
x393_dut.x393_i.event_logger_i.i_rs232_rcv.ser_rst
x393_dut.x393_i.event_logger_i.i_rs232_rcv.ser_di
x393_dut.x393_i.event_logger_i.i_rs232_rcv.ser_filt_di
x393_dut.x393_i.event_logger_i.i_rs232_rcv.ser_do
x393_dut.x393_i.event_logger_i.i_rs232_rcv.ser_do_stb
x393_dut.x393_i.event_logger_i.i_rs232_rcv.wait_just_pause
x393_dut.x393_i.event_logger_i.i_rs232_rcv.wait_pause
x393_dut.x393_i.event_logger_i.i_rs232_rcv.wait_start
x393_dut.x393_i.event_logger_i.i_rs232_rcv.reset_wait_pause
x393_dut.x393_i.event_logger_i.i_rs232_rcv.ts_stb
x393_dut.x393_i.event_logger_i.i_rs232_rcv.start
@c00022
x393_dut.x393_i.event_logger_i.i_rs232_rcv.debug[4:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_rs232_rcv.debug[4:0]
(1)x393_dut.x393_i.event_logger_i.i_rs232_rcv.debug[4:0]
(2)x393_dut.x393_i.event_logger_i.i_rs232_rcv.debug[4:0]
(3)x393_dut.x393_i.event_logger_i.i_rs232_rcv.debug[4:0]
(4)x393_dut.x393_i.event_logger_i.i_rs232_rcv.debug[4:0]
@1401200
-group_end
@22
x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_dur_cntr[15:0]
@c00022
x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_dur_cntr_r[15:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_dur_cntr_r[15:0]
(1)x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_dur_cntr_r[15:0]
(2)x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_dur_cntr_r[15:0]
(3)x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_dur_cntr_r[15:0]
(4)x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_dur_cntr_r[15:0]
(5)x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_dur_cntr_r[15:0]
(6)x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_dur_cntr_r[15:0]
(7)x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_dur_cntr_r[15:0]
(8)x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_dur_cntr_r[15:0]
(9)x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_dur_cntr_r[15:0]
(10)x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_dur_cntr_r[15:0]
(11)x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_dur_cntr_r[15:0]
(12)x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_dur_cntr_r[15:0]
(13)x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_dur_cntr_r[15:0]
(14)x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_dur_cntr_r[15:0]
(15)x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_dur_cntr_r[15:0]
@1401200
-group_end
@c00022
x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_cntr[4:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_cntr[4:0]
(1)x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_cntr[4:0]
(2)x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_cntr[4:0]
(3)x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_cntr[4:0]
(4)x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_cntr[4:0]
@1401200
-group_end
@28
x393_dut.x393_i.event_logger_i.i_rs232_rcv.last_half_bit
x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_half_end
@c08022
x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_cntr_r[4:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_cntr_r[4:0]
(1)x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_cntr_r[4:0]
(2)x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_cntr_r[4:0]
(3)x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_cntr_r[4:0]
(4)x393_dut.x393_i.event_logger_i.i_rs232_rcv.bit_cntr_r[4:0]
@1401200
-group_end
@28
x393_dut.x393_i.event_logger_i.i_rs232_rcv.reset_wait_pause
x393_dut.x393_i.event_logger_i.i_rs232_rcv.restart[1:0]
x393_dut.x393_i.event_logger_i.i_rs232_rcv.reset_bit_duration
@22
x393_dut.x393_i.event_logger_i.i_rs232_rcv.bitHalfPeriod[15:0]
@1401200
-rs232_rcvr
@c00200
-nmea_decoder
@28
x393_dut.x393_i.event_logger_i.i_nmea_decoder.start
x393_dut.x393_i.event_logger_i.i_nmea_decoder.start_char
x393_dut.x393_i.event_logger_i.i_nmea_decoder.start_format
x393_dut.x393_i.event_logger_i.i_nmea_decoder.restart
x393_dut.x393_i.event_logger_i.i_nmea_decoder.ser_rst
x393_dut.x393_i.event_logger_i.i_nmea_decoder.gp_exp_bit
x393_dut.x393_i.event_logger_i.i_nmea_decoder.ser_di
x393_dut.x393_i.event_logger_i.i_nmea_decoder.ser_stb
x393_dut.x393_i.event_logger_i.i_nmea_decoder.nmea_sent_start
x393_dut.x393_i.event_logger_i.i_nmea_decoder.rdy
@22
[color] 2
x393_dut.x393_i.event_logger_i.i_nmea_decoder.raddr[4:0]
@28
[color] 2
x393_dut.x393_i.event_logger_i.i_nmea_decoder.rd_stb
@22
[color] 2
x393_dut.x393_i.event_logger_i.i_nmea_decoder.rdata[15:0]
@c00022
x393_dut.x393_i.event_logger_i.i_nmea_decoder.debug[23:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_nmea_decoder.debug[23:0]
(1)x393_dut.x393_i.event_logger_i.i_nmea_decoder.debug[23:0]
(2)x393_dut.x393_i.event_logger_i.i_nmea_decoder.debug[23:0]
(3)x393_dut.x393_i.event_logger_i.i_nmea_decoder.debug[23:0]
(4)x393_dut.x393_i.event_logger_i.i_nmea_decoder.debug[23:0]
(5)x393_dut.x393_i.event_logger_i.i_nmea_decoder.debug[23:0]
(6)x393_dut.x393_i.event_logger_i.i_nmea_decoder.debug[23:0]
(7)x393_dut.x393_i.event_logger_i.i_nmea_decoder.debug[23:0]
(8)x393_dut.x393_i.event_logger_i.i_nmea_decoder.debug[23:0]
(9)x393_dut.x393_i.event_logger_i.i_nmea_decoder.debug[23:0]
(10)x393_dut.x393_i.event_logger_i.i_nmea_decoder.debug[23:0]
(11)x393_dut.x393_i.event_logger_i.i_nmea_decoder.debug[23:0]
(12)x393_dut.x393_i.event_logger_i.i_nmea_decoder.debug[23:0]
(13)x393_dut.x393_i.event_logger_i.i_nmea_decoder.debug[23:0]
(14)x393_dut.x393_i.event_logger_i.i_nmea_decoder.debug[23:0]
(15)x393_dut.x393_i.event_logger_i.i_nmea_decoder.debug[23:0]
(16)x393_dut.x393_i.event_logger_i.i_nmea_decoder.debug[23:0]
(17)x393_dut.x393_i.event_logger_i.i_nmea_decoder.debug[23:0]
(18)x393_dut.x393_i.event_logger_i.i_nmea_decoder.debug[23:0]
(19)x393_dut.x393_i.event_logger_i.i_nmea_decoder.debug[23:0]
(20)x393_dut.x393_i.event_logger_i.i_nmea_decoder.debug[23:0]
(21)x393_dut.x393_i.event_logger_i.i_nmea_decoder.debug[23:0]
(22)x393_dut.x393_i.event_logger_i.i_nmea_decoder.debug[23:0]
(23)x393_dut.x393_i.event_logger_i.i_nmea_decoder.debug[23:0]
@1401200
-group_end
@28
x393_dut.x393_i.event_logger_i.i_nmea_decoder.valid
x393_dut.x393_i.event_logger_i.i_nmea_decoder.vfy_dollar
x393_dut.x393_i.event_logger_i.i_nmea_decoder.vfy_gp
x393_dut.x393_i.event_logger_i.i_nmea_decoder.last_vfy_gp
x393_dut.x393_i.event_logger_i.i_nmea_decoder.last_vfy_sent
x393_dut.x393_i.event_logger_i.i_nmea_decoder.vfy_sel_sent
x393_dut.x393_i.event_logger_i.i_nmea_decoder.vfy_first_comma
@c00022
x393_dut.x393_i.event_logger_i.i_nmea_decoder.gpxxx_addr[3:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_nmea_decoder.gpxxx_addr[3:0]
(1)x393_dut.x393_i.event_logger_i.i_nmea_decoder.gpxxx_addr[3:0]
(2)x393_dut.x393_i.event_logger_i.i_nmea_decoder.gpxxx_addr[3:0]
(3)x393_dut.x393_i.event_logger_i.i_nmea_decoder.gpxxx_addr[3:0]
@1401200
-group_end
@c00022
x393_dut.x393_i.event_logger_i.i_nmea_decoder.gpxxx_w_one[3:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_nmea_decoder.gpxxx_w_one[3:0]
(1)x393_dut.x393_i.event_logger_i.i_nmea_decoder.gpxxx_w_one[3:0]
(2)x393_dut.x393_i.event_logger_i.i_nmea_decoder.gpxxx_w_one[3:0]
(3)x393_dut.x393_i.event_logger_i.i_nmea_decoder.gpxxx_w_one[3:0]
@1401200
-group_end
@28
x393_dut.x393_i.event_logger_i.i_nmea_decoder.msb
@c00022
x393_dut.x393_i.event_logger_i.i_nmea_decoder.stb[3:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_nmea_decoder.stb[3:0]
(1)x393_dut.x393_i.event_logger_i.i_nmea_decoder.stb[3:0]
(2)x393_dut.x393_i.event_logger_i.i_nmea_decoder.stb[3:0]
(3)x393_dut.x393_i.event_logger_i.i_nmea_decoder.stb[3:0]
@1401200
-group_end
@28
x393_dut.x393_i.event_logger_i.i_nmea_decoder.we
@22
x393_dut.x393_i.event_logger_i.i_nmea_decoder.wa[4:0]
x393_dut.x393_i.event_logger_i.i_nmea_decoder.wd[7:0]
@200
-
@28
x393_dut.x393_i.event_logger_i.i_nmea_decoder.nibble_stb
@c00022
x393_dut.x393_i.event_logger_i.i_nmea_decoder.nibble_count[6:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_nmea_decoder.nibble_count[6:0]
(1)x393_dut.x393_i.event_logger_i.i_nmea_decoder.nibble_count[6:0]
(2)x393_dut.x393_i.event_logger_i.i_nmea_decoder.nibble_count[6:0]
(3)x393_dut.x393_i.event_logger_i.i_nmea_decoder.nibble_count[6:0]
(4)x393_dut.x393_i.event_logger_i.i_nmea_decoder.nibble_count[6:0]
(5)x393_dut.x393_i.event_logger_i.i_nmea_decoder.nibble_count[6:0]
(6)x393_dut.x393_i.event_logger_i.i_nmea_decoder.nibble_count[6:0]
@1401200
-group_end
@22
x393_dut.x393_i.event_logger_i.i_nmea_decoder.nibble[3:0]
@1401200
-nmea_decoder
@c00200
-imu_exttime
@28
x393_dut.x393_i.event_logger_i.i_imu_exttime.mclk
x393_dut.x393_i.event_logger_i.i_imu_exttime.mrst
x393_dut.x393_i.event_logger_i.i_imu_exttime.xclk
x393_dut.x393_i.event_logger_i.i_imu_exttime.xrst
x393_dut.x393_i.event_logger_i.i_imu_exttime.ts
x393_dut.x393_i.event_logger_i.i_imu_exttime.rdy
x393_dut.x393_i.event_logger_i.i_imu_exttime.rd_stb
x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_full
x393_dut.x393_i.event_logger_i.i_imu_exttime.rd_start
x393_dut.x393_i.event_logger_i.i_imu_exttime.rd_start_mclk
@22
x393_dut.x393_i.event_logger_i.i_imu_exttime.copy_data[7:0]
x393_dut.x393_i.event_logger_i.i_imu_exttime.copy_data_r[7:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_imu_exttime.copy_selected[1:0]
x393_dut.x393_i.event_logger_i.i_imu_exttime.sel_chn[1:0]
(1)x393_dut.x393_i.event_logger_i.i_imu_exttime.copy_selected[1:0]
(2)x393_dut.x393_i.event_logger_i.i_imu_exttime.copy_cntr[2:0]
x393_dut.x393_i.event_logger_i.i_imu_exttime.raddr[2:0]
@c00022
x393_dut.x393_i.event_logger_i.i_imu_exttime.rdata[15:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_imu_exttime.rdata[15:0]
(1)x393_dut.x393_i.event_logger_i.i_imu_exttime.rdata[15:0]
(2)x393_dut.x393_i.event_logger_i.i_imu_exttime.rdata[15:0]
(3)x393_dut.x393_i.event_logger_i.i_imu_exttime.rdata[15:0]
(4)x393_dut.x393_i.event_logger_i.i_imu_exttime.rdata[15:0]
(5)x393_dut.x393_i.event_logger_i.i_imu_exttime.rdata[15:0]
(6)x393_dut.x393_i.event_logger_i.i_imu_exttime.rdata[15:0]
(7)x393_dut.x393_i.event_logger_i.i_imu_exttime.rdata[15:0]
(8)x393_dut.x393_i.event_logger_i.i_imu_exttime.rdata[15:0]
(9)x393_dut.x393_i.event_logger_i.i_imu_exttime.rdata[15:0]
(10)x393_dut.x393_i.event_logger_i.i_imu_exttime.rdata[15:0]
(11)x393_dut.x393_i.event_logger_i.i_imu_exttime.rdata[15:0]
(12)x393_dut.x393_i.event_logger_i.i_imu_exttime.rdata[15:0]
(13)x393_dut.x393_i.event_logger_i.i_imu_exttime.rdata[15:0]
(14)x393_dut.x393_i.event_logger_i.i_imu_exttime.rdata[15:0]
(15)x393_dut.x393_i.event_logger_i.i_imu_exttime.rdata[15:0]
@1401200
-group_end
@22
x393_dut.x393_i.event_logger_i.i_imu_exttime.en_chn_mclk[3:0]
@800022
x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_stb[3:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_stb[3:0]
(1)x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_stb[3:0]
(2)x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_stb[3:0]
(3)x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_stb[3:0]
@1001200
-group_end
@c00022
x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_data_chn0[7:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_data_chn0[7:0]
(1)x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_data_chn0[7:0]
(2)x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_data_chn0[7:0]
(3)x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_data_chn0[7:0]
(4)x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_data_chn0[7:0]
(5)x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_data_chn0[7:0]
(6)x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_data_chn0[7:0]
(7)x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_data_chn0[7:0]
@1401200
-group_end
@22
x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_data_chn1[7:0]
x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_data_chn2[7:0]
x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_data_chn3[7:0]
@c00022
x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_got[3:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_got[3:0]
(1)x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_got[3:0]
(2)x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_got[3:0]
(3)x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_got[3:0]
@1401200
-group_end
@28
x393_dut.x393_i.event_logger_i.i_imu_exttime.i_ts.rst
x393_dut.x393_i.event_logger_i.i_imu_exttime.pre_copy_started
x393_dut.x393_i.event_logger_i.i_imu_exttime.pre_copy_w
x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_full
@800022
x393_dut.x393_i.event_logger_i.i_imu_exttime.in_full[3:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_imu_exttime.in_full[3:0]
(1)x393_dut.x393_i.event_logger_i.i_imu_exttime.in_full[3:0]
(2)x393_dut.x393_i.event_logger_i.i_imu_exttime.in_full[3:0]
(3)x393_dut.x393_i.event_logger_i.i_imu_exttime.in_full[3:0]
x393_dut.x393_i.event_logger_i.i_imu_exttime.en
@1001200
-group_end
@28
x393_dut.x393_i.event_logger_i.i_imu_exttime.ts_full
@c00022
x393_dut.x393_i.event_logger_i.i_imu_exttime.chn_pri_w[3:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_imu_exttime.chn_pri_w[3:0]
(1)x393_dut.x393_i.event_logger_i.i_imu_exttime.chn_pri_w[3:0]
(2)x393_dut.x393_i.event_logger_i.i_imu_exttime.chn_pri_w[3:0]
(3)x393_dut.x393_i.event_logger_i.i_imu_exttime.chn_pri_w[3:0]
@1401200
-group_end
@28
x393_dut.x393_i.event_logger_i.i_imu_exttime.chn_enc_w[1:0]
@800028
x393_dut.x393_i.event_logger_i.i_imu_exttime.copy_selected[1:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_imu_exttime.copy_selected[1:0]
(1)x393_dut.x393_i.event_logger_i.i_imu_exttime.copy_selected[1:0]
@1001200
-group_end
@c00022
x393_dut.x393_i.event_logger_i.i_imu_exttime.copy_cntr[2:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_imu_exttime.copy_cntr[2:0]
(1)x393_dut.x393_i.event_logger_i.i_imu_exttime.copy_cntr[2:0]
(2)x393_dut.x393_i.event_logger_i.i_imu_exttime.copy_cntr[2:0]
@1401200
-group_end
@c00022
x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(1)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(2)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(3)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(4)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(5)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(6)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(7)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(8)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(9)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(10)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(11)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(12)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(13)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(14)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(15)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(16)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(17)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(18)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(19)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(20)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(21)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(22)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(23)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(24)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(25)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(26)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(27)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(28)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(29)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(30)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
(31)x393_dut.x393_i.event_logger_i.i_imu_exttime.dout_chn[31:0]
@1401200
-group_end
@28
x393_dut.x393_i.event_logger_i.i_imu_exttime.pre_copy_started
x393_dut.x393_i.event_logger_i.i_imu_exttime.sel_chn[1:0]
@200
-fifo0
@28
x393_dut.x393_i.event_logger_i.i_imu_exttime.timestamp_fifo_chn0_i.rcv
@22
x393_dut.x393_i.event_logger_i.i_imu_exttime.timestamp_fifo_chn0_i.wpntr[3:0]
x393_dut.x393_i.event_logger_i.i_imu_exttime.timestamp_fifo_chn0_i.din[7:0]
@28
x393_dut.x393_i.event_logger_i.i_imu_exttime.timestamp_fifo_chn0_i.advance
x393_dut.x393_i.event_logger_i.i_imu_exttime.timestamp_fifo_chn0_i.advance_r[1:0]
@22
x393_dut.x393_i.event_logger_i.i_imu_exttime.timestamp_fifo_chn0_i.rpntr[3:0]
x393_dut.x393_i.event_logger_i.i_imu_exttime.timestamp_fifo_chn0_i.dout[7:0]
@200
-
@1401200
-imu_exttime
@c00200
-imu_spi
-external
@28
x393_dut.IMU_CS
x393_dut.IMU_MOSI
x393_dut.IMU_MISO
@22
x393_dut.IMU_LOOPBACK[15:0]
@28
x393_dut.IMU_SCLK_OUT
@200
-
@28
(6)x393_dut.x393_i.gpio393_i.ext_pins[9:0]
(7)x393_dut.x393_i.gpio393_i.ext_pins[9:0]
@1401200
-external
@28
x393_dut.x393_i.event_logger_i.i_imu_spi.mosi
x393_dut.x393_i.event_logger_i.i_imu_spi.miso
x393_dut.x393_i.event_logger_i.i_imu_spi.sda
x393_dut.x393_i.event_logger_i.i_imu_spi.sda_en
x393_dut.x393_i.event_logger_i.i_imu_spi.scl
x393_dut.x393_i.event_logger_i.i_imu_spi.scl_en
x393_dut.x393_i.event_logger_i.i_imu_spi.ts
x393_dut.x393_i.event_logger_i.i_imu_spi.rdy
x393_dut.x393_i.event_logger_i.i_imu_spi.rd_stb
@22
x393_dut.x393_i.event_logger_i.i_imu_spi.raddr[4:0]
x393_dut.x393_i.event_logger_i.i_imu_spi.rdata[15:0]
@28
x393_dut.x393_i.event_logger_i.i_imu_spi.stall
@1401200
-imu_spi
@c00200
-logger_arbiter
@28
x393_dut.x393_i.event_logger_i.i_logger_arbiter.rst
x393_dut.x393_i.event_logger_i.i_logger_arbiter.xclk
@c00022
x393_dut.x393_i.event_logger_i.i_logger_arbiter.rdy[3:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_logger_arbiter.rdy[3:0]
(1)x393_dut.x393_i.event_logger_i.i_logger_arbiter.rdy[3:0]
(2)x393_dut.x393_i.event_logger_i.i_logger_arbiter.rdy[3:0]
(3)x393_dut.x393_i.event_logger_i.i_logger_arbiter.rdy[3:0]
@1401200
-group_end
@c00022
x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_rq_in[3:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_rq_in[3:0]
(1)x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_rq_in[3:0]
(2)x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_rq_in[3:0]
(3)x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_rq_in[3:0]
@1401200
-group_end
@c00022
x393_dut.x393_i.event_logger_i.i_logger_arbiter.wts_rq[3:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_logger_arbiter.wts_rq[3:0]
(1)x393_dut.x393_i.event_logger_i.i_logger_arbiter.wts_rq[3:0]
(2)x393_dut.x393_i.event_logger_i.i_logger_arbiter.wts_rq[3:0]
(3)x393_dut.x393_i.event_logger_i.i_logger_arbiter.wts_rq[3:0]
@1401200
-group_end
@c00022
x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_grant[3:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_grant[3:0]
(1)x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_grant[3:0]
(2)x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_grant[3:0]
(3)x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_grant[3:0]
@1401200
-group_end
@22
x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_valid[3:0]
x393_dut.x393_i.event_logger_i.i_logger_arbiter.chn_servicing[3:0]
@28
x393_dut.x393_i.event_logger_i.i_logger_arbiter.ts_en
@c00022
x393_dut.x393_i.event_logger_i.i_logger_arbiter.seq_cntr[4:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_logger_arbiter.seq_cntr[4:0]
(1)x393_dut.x393_i.event_logger_i.i_logger_arbiter.seq_cntr[4:0]
(2)x393_dut.x393_i.event_logger_i.i_logger_arbiter.seq_cntr[4:0]
(3)x393_dut.x393_i.event_logger_i.i_logger_arbiter.seq_cntr[4:0]
(4)x393_dut.x393_i.event_logger_i.i_logger_arbiter.seq_cntr[4:0]
@1401200
-group_end
@c08022
x393_dut.x393_i.event_logger_i.i_logger_arbiter.seq_cntr[4:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_logger_arbiter.seq_cntr[4:0]
(1)x393_dut.x393_i.event_logger_i.i_logger_arbiter.seq_cntr[4:0]
(2)x393_dut.x393_i.event_logger_i.i_logger_arbiter.seq_cntr[4:0]
(3)x393_dut.x393_i.event_logger_i.i_logger_arbiter.seq_cntr[4:0]
(4)x393_dut.x393_i.event_logger_i.i_logger_arbiter.seq_cntr[4:0]
@1401200
-group_end
@28
x393_dut.x393_i.event_logger_i.i_logger_arbiter.pre_nxt
@800022
x393_dut.x393_i.event_logger_i.i_logger_arbiter.nxt[3:0]
@28
(0)x393_dut.x393_i.event_logger_i.i_logger_arbiter.nxt[3:0]
(1)x393_dut.x393_i.event_logger_i.i_logger_arbiter.nxt[3:0]
(2)x393_dut.x393_i.event_logger_i.i_logger_arbiter.nxt[3:0]
(3)x393_dut.x393_i.event_logger_i.i_logger_arbiter.nxt[3:0]
x393_dut.x393_i.event_logger_i.i_logger_arbiter.seq_cntr_last
@1001200
-group_end
@28
x393_dut.x393_i.event_logger_i.i_logger_arbiter.channel[1:0]
@22
x393_dut.x393_i.event_logger_i.i_logger_arbiter.sample_counter[23:0]
@28
x393_dut.x393_i.event_logger_i.i_logger_arbiter.dv
x393_dut.x393_i.event_logger_i.i_logger_arbiter.busy
@22
x393_dut.x393_i.event_logger_i.i_logger_arbiter.channels_ready[3:0]
x393_dut.x393_i.event_logger_i.i_logger_arbiter.chn_servicing[3:0]
@28
x393_dut.x393_i.event_logger_i.i_logger_arbiter.wstart
x393_dut.x393_i.event_logger_i.i_logger_arbiter.chn1hot[3:1]
@1401200
-logger_arbiter
@28
x393_dut.x393_i.event_logger_i.gps_pulse1sec_single
@c00022
x393_dut.x393_i.event_logger_i.timestamp_request[3:0]
@28
(0)x393_dut.x393_i.event_logger_i.timestamp_request[3:0]
(1)x393_dut.x393_i.event_logger_i.timestamp_request[3:0]
(2)x393_dut.x393_i.event_logger_i.timestamp_request[3:0]
(3)x393_dut.x393_i.event_logger_i.timestamp_request[3:0]
@1401200
-group_end
@c00022
x393_dut.x393_i.event_logger_i.timestamp_request_long[3:0]
@28
(0)x393_dut.x393_i.event_logger_i.timestamp_request_long[3:0]
(1)x393_dut.x393_i.event_logger_i.timestamp_request_long[3:0]
(2)x393_dut.x393_i.event_logger_i.timestamp_request_long[3:0]
(3)x393_dut.x393_i.event_logger_i.timestamp_request_long[3:0]
@1401200
-group_end
@c00022
x393_dut.x393_i.event_logger_i.timestamp_ackn[3:0]
@28
(0)x393_dut.x393_i.event_logger_i.timestamp_ackn[3:0]
(1)x393_dut.x393_i.event_logger_i.timestamp_ackn[3:0]
(2)x393_dut.x393_i.event_logger_i.timestamp_ackn[3:0]
(3)x393_dut.x393_i.event_logger_i.timestamp_ackn[3:0]
@1401200
-group_end
@22
x393_dut.x393_i.event_logger_i.channel_ready[3:0]
@c00022
x393_dut.x393_i.event_logger_i.channel_next[3:0]
@28
(0)x393_dut.x393_i.event_logger_i.channel_next[3:0]
(1)x393_dut.x393_i.event_logger_i.channel_next[3:0]
(2)x393_dut.x393_i.event_logger_i.channel_next[3:0]
(3)x393_dut.x393_i.event_logger_i.channel_next[3:0]
@1401200
-group_end
@28
x393_dut.x393_i.event_logger_i.mux_rdy_source
x393_dut.x393_i.event_logger_i.mux_data_valid
x393_dut.x393_i.event_logger_i.ts_en
@22
x393_dut.x393_i.event_logger_i.timestamps_rdata[15:0]
@c00022
x393_dut.x393_i.event_logger_i.mux_data_source[15:0]
@28
(0)x393_dut.x393_i.event_logger_i.mux_data_source[15:0]
(1)x393_dut.x393_i.event_logger_i.mux_data_source[15:0]
(2)x393_dut.x393_i.event_logger_i.mux_data_source[15:0]
(3)x393_dut.x393_i.event_logger_i.mux_data_source[15:0]
(4)x393_dut.x393_i.event_logger_i.mux_data_source[15:0]
(5)x393_dut.x393_i.event_logger_i.mux_data_source[15:0]
(6)x393_dut.x393_i.event_logger_i.mux_data_source[15:0]
(7)x393_dut.x393_i.event_logger_i.mux_data_source[15:0]
(8)x393_dut.x393_i.event_logger_i.mux_data_source[15:0]
(9)x393_dut.x393_i.event_logger_i.mux_data_source[15:0]
(10)x393_dut.x393_i.event_logger_i.mux_data_source[15:0]
(11)x393_dut.x393_i.event_logger_i.mux_data_source[15:0]
(12)x393_dut.x393_i.event_logger_i.mux_data_source[15:0]
(13)x393_dut.x393_i.event_logger_i.mux_data_source[15:0]
(14)x393_dut.x393_i.event_logger_i.mux_data_source[15:0]
(15)x393_dut.x393_i.event_logger_i.mux_data_source[15:0]
@1401200
-group_end
@22
x393_dut.x393_i.event_logger_i.mux_data_final[15:0]
@800022
x393_dut.x393_i.event_logger_i.timestamp_request[3:0]
@28
(0)x393_dut.x393_i.event_logger_i.timestamp_request[3:0]
(1)x393_dut.x393_i.event_logger_i.timestamp_request[3:0]
(2)x393_dut.x393_i.event_logger_i.timestamp_request[3:0]
(3)x393_dut.x393_i.event_logger_i.timestamp_request[3:0]
@1001200
-group_end
@28
x393_dut.x393_i.event_logger_i.mclk
@22
[color] 3
x393_dut.x393_i.event_logger_i.data_out[15:0]
@28
[color] 3
x393_dut.x393_i.event_logger_i.data_out_stb
@22
[color] 3
x393_dut.x393_i.event_logger_i.sample_counter[23:0]
@c00200
-x393
@22
x393_dut.x393_i.logger_out[15:0]
@28
x393_dut.x393_i.logger_stb
@1401200
-x393
@1000200
-i2c
-event_logger
@800200
-mult_saxi_wr_inbuf
@28
x393_dut.x393_i.mult_saxi_wr_inbuf_i.mclk
x393_dut.x393_i.mult_saxi_wr_inbuf_i.en
@22
x393_dut.x393_i.mult_saxi_wr_inbuf_i.data_in[15:0]
@28
x393_dut.x393_i.mult_saxi_wr_inbuf_i.valid
x393_dut.x393_i.mult_saxi_wr_inbuf_i.has_burst
x393_dut.x393_i.mult_saxi_wr_inbuf_i.read_burst
@22
x393_dut.x393_i.mult_saxi_wr_inbuf_i.data_out[31:0]
@1000200
-mult_saxi_wr_inbuf
@800200
-mult_saxi_wr
@22
x393_dut.x393_i.mult_saxi_wr_i.cmd_ad[7:0]
@28
x393_dut.x393_i.mult_saxi_wr_i.cmd_stb
x393_dut.x393_i.mult_saxi_wr_i.pre_valid_chn0
x393_dut.x393_i.mult_saxi_wr_i.irq_log_we
x393_dut.x393_i.mult_saxi_wr_i.we_ctrl
x393_dut.x393_i.mult_saxi_wr_i.cmd_we_sa_len
@22
x393_dut.x393_i.mult_saxi_wr_i.cmd_a[3:0]
x393_dut.x393_i.mult_saxi_wr_i.cmd_data[31:0]
@28
x393_dut.x393_i.mult_saxi_wr_i.saxi_awready
x393_dut.x393_i.mult_saxi_wr_i.saxi_awvalid
@22
x393_dut.x393_i.mult_saxi_wr_i.saxi_awaddr[31:0]
@28
x393_dut.x393_i.mult_saxi_wr_i.saxi_wready
x393_dut.x393_i.mult_saxi_wr_i.saxi_wvalid
@22
x393_dut.x393_i.mult_saxi_wr_i.saxi_wdata[31:0]
x393_dut.x393_i.mult_saxi_wr_i.axi_addr[29:0]
@800200
-mult_saxi_wr_pointers
@22
x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.chn[1:0]
x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.start
@28
x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.busy
@22
x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.chn_en_mclk[3:0]
x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.chn_en_aclk[3:0]
x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.axi_len[3:0]
x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.axi_addr[29:0]
@28
x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.ptr_we
@22
x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.irqs[3:0]
@28
x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.aclk
x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.rst_aclk
x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.en_aclk
x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.busy_r
x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.rst
@c00022
x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.rst_pntr_mclk[3:0]
@28
(0)x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.rst_pntr_mclk[3:0]
(1)x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.rst_pntr_mclk[3:0]
(2)x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.rst_pntr_mclk[3:0]
(3)x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.rst_pntr_mclk[3:0]
@1401200
-group_end
@c00022
x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.rst_pntr_aclk[3:0]
@28
(0)x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.rst_pntr_aclk[3:0]
(1)x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.rst_pntr_aclk[3:0]
(2)x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.rst_pntr_aclk[3:0]
(3)x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.rst_pntr_aclk[3:0]
@1401200
-group_end
@800022
x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.reset_rq[3:0]
@22
x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.reset_rq_pri[3:0]
@28
(0)x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.reset_rq[3:0]
(1)x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.reset_rq[3:0]
(2)x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.reset_rq[3:0]
(3)x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.reset_rq[3:0]
@1001200
-group_end
@28
x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.start_resetting_w
x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.resetting[1:0]
x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.seq[1:0]
x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.pntr_we
x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.pntr_wa[1:0]
@22
x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.pntr_wd[29:0]
@28
x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.sa_len_we
x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.sa_len_wa[2:0]
@22
x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.sa_len_di[29:0]
@28
x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.sa_len_ra[2:0]
@23
x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.sa_len_ram_out[29:0]
@28
x393_dut.x393_i.mult_saxi_wr_i.mrst
x393_dut.x393_i.mult_saxi_wr_i.arst
@200
-
@1000200
-mult_saxi_wr_pointers
-mult_saxi_wr
@c00200
-IMU_
@28
x393_dut.GPS1SEC
x393_dut.IMU_103695REVA
x393_dut.IMU_ACTIVE
[color] 3
x393_dut.IMU_CS
x393_dut.IMU_DATA_READY
x393_dut.IMU_EN
x393_dut.IMU_LATE_ACKN
@22
x393_dut.IMU_LOOPBACK[15:0]
@28
x393_dut.IMU_MISO
x393_dut.IMU_MOSI
x393_dut.IMU_MOSI_D
x393_dut.IMU_MOSI_OUT
x393_dut.IMU_MOSI_REVA
[color] 6
x393_dut.IMU_NMOSI
x393_dut.IMU_SCLK
x393_dut.IMU_SCLK_OUT
x393_dut.IMU_SCL
x393_dut.IMU_SDA
@22
x393_dut.IMU_TAPS[5:1]
@1401200
-IMU_
[pattern_trace] 1
[pattern_trace] 0
cocotb/x393_cocotb_server.py
View file @ e4592ccb
......@@ -140,7 +140,16 @@ class X393_cocotb_server(object):
data_bytes = 4,
autoflush = self.autoflush,
blatency = 5)
#event logger from FPGA
self.saxigp1 = SAXIWrSim (entity = dut,
name = "saxigp1",
clock = dut.saxi0_aclk,
mempath = self.mempath,
memhigh = self.memhigh,
data_bytes = 4,
autoflush = self.autoflush,
blatency = 5)
level = logging.DEBUG if debug else logging.INFO # WARNING
self.dut._log.info('Set debug level '+str(level)+", debug="+str(debug))
......@@ -150,6 +159,7 @@ class X393_cocotb_server(object):
self.saxihp0w.log.setLevel(level)
self.saxihp1w.log.setLevel(level)
self.saxigp0.log.setLevel(level)
self.saxigp1.log.setLevel(level)
#Initialize socket
self.PORT = port
......@@ -208,6 +218,7 @@ class X393_cocotb_server(object):
self.saxihp0w_thread = cocotb.fork(self.saxihp0w.saxi_wr_run())
self.saxihp1w_thread = cocotb.fork(self.saxihp1w.saxi_wr_run())
self.saxigp0_thread = cocotb.fork(self.saxigp0.saxi_wr_run())
self.saxigp1_thread = cocotb.fork(self.saxigp1.saxi_wr_run())
self.soc_conn.send(self.cmd.toJSON(0)+"\n")
self.dut._log.debug('Sent 0 to the socket')
started=True
......
cocotb/x393_dut.v
View file @ e4592ccb
......@@ -145,6 +145,19 @@ module x393_dut#(
input [3:0] saxigp0_bresp_latency,
output [3:0] saxigp0_wr_qos,
// Event logger FPGA -> CPU
output [31:0] saxigp1_wr_address,
output [ 5:0] saxigp1_wid,
output saxigp1_wr_valid,
input saxigp1_wr_ready,
output [31:0] saxigp1_wr_data,
output [3:0] saxigp1_wr_stb,
output [1:0] saxigp1_wr_size,
input [3:0] saxigp1_bresp_latency,
output [3:0] saxigp1_wr_qos,
output [NUM_INTERRUPTS-1:0] irq_r, // {x393_i.sata_irq, x393_i.cmprs_irq[3:0], x393_i.frseq_irq[3:0]};
// SATA and SATA clock I/O
......@@ -679,8 +692,6 @@ module x393_dut#(
wire [ 9:0] gpio_pins; // inout[9:0] ([8]-synco0,[7]-syncio0,[6]-synco1,[9]-syncio1)
// Connect trigger outs to triggets in (#10 needed for Icarus)
assign #10 gpio_pins[7] = gpio_pins[8];
assign #10 gpio_pins[9] = gpio_pins[6];
// DDR3 signals
wire SDRST;
......@@ -1349,6 +1360,43 @@ simul_axi_hp_wr #(
.sim_wr_qos (saxigp0_wr_qos) // output[3:0]
);
// SAXI_GP1 - event logger to system memory
simul_saxi_gp_wr simul_saxi_gp1_wr_i (
.rst (RST), // input
.aclk (saxi0_aclk), // input
.aresetn (), // output
.awaddr (x393_i.ps7_i.SAXIGP1AWADDR), // input[31:0]
.awvalid (x393_i.ps7_i.SAXIGP1AWVALID), // input
.awready (x393_i.ps7_i.SAXIGP1AWREADY), // output
.awid (x393_i.ps7_i.SAXIGP1AWID), // input[5:0]
.awlock (x393_i.ps7_i.SAXIGP1AWLOCK), // input[1:0]
.awcache (x393_i.ps7_i.SAXIGP1AWCACHE), // input[3:0]
.awprot (x393_i.ps7_i.SAXIGP1AWPROT), // input[2:0]
.awlen (x393_i.ps7_i.SAXIGP1AWLEN), // input[3:0]
.awsize (x393_i.ps7_i.SAXIGP1AWSIZE), // input[1:0]
.awburst (x393_i.ps7_i.SAXIGP1AWBURST), // input[1:0]
.awqos (x393_i.ps7_i.SAXIGP1AWQOS), // input[3:0]
.wdata (x393_i.ps7_i.SAXIGP1WDATA), // input[31:0]
.wvalid (x393_i.ps7_i.SAXIGP1WVALID), // input
.wready (x393_i.ps7_i.SAXIGP1WREADY), // output
.wid (x393_i.ps7_i.SAXIGP1WID), // input[5:0]
.wlast (x393_i.ps7_i.SAXIGP1WLAST), // input
.wstrb (x393_i.ps7_i.SAXIGP1WSTRB), // input[3:0]
.bvalid (x393_i.ps7_i.SAXIGP1BVALID), // output
.bready (x393_i.ps7_i.SAXIGP1BREADY), // input
.bid (x393_i.ps7_i.SAXIGP1BID), // output[5:0]
.bresp (x393_i.ps7_i.SAXIGP1BRESP), // output[1:0]
.sim_wr_address (saxigp1_wr_address), // output[31:0]
.sim_wid (saxigp1_wid), // output[5:0]
.sim_wr_valid (saxigp1_wr_valid), // output
.sim_wr_ready (saxigp1_wr_ready), // input
.sim_wr_data (saxigp1_wr_data), // output[31:0]
.sim_wr_stb (saxigp1_wr_stb), // output[3:0]
.sim_wr_size (saxigp1_wr_size), // output[1:0]
.sim_bresp_latency (saxigp1_bresp_latency), // input[3:0]
.sim_wr_qos (saxigp1_wr_qos) // output[3:0]
);
// Generate all clocks
simul_clk #(
......@@ -1713,6 +1761,221 @@ simul_axi_hp_wr #(
//localparam line = `__LINE__;
assign x393_i.ps7_i.FCLKCLK= {4{CLK}};
assign x393_i.ps7_i.FCLKRESETN= {RST,~RST,RST,~RST};
`define TEST_IMU
assign #10 gpio_pins[7] = gpio_pins[8];
`ifndef TEST_IMU
assign #10 gpio_pins[9] = gpio_pins[6];
`endif
`ifdef TEST_IMU
// localparam X313_WA_IOPINS_EN_IMU_OUT= 'hc0000000;
// localparam X313_WA_IOPINS_DIS_IMU_OUT='h80000000; //SuppressThisWarning Veditor UNUSED
// localparam X313_WA_IMU_CTRL= 'h7f;
// localparam X313_WA_IMU_DATA= 'h7e;
// localparam X313_RA_IMU_DATA= 'h7e; // read fifo word, advance pointer (32 reads w/o ready check)
// localparam X313_RA_IMU_STATUS= 'h7f; // LSB==ready
// localparam IMU_PERIOD= 'h800; // normal period
// localparam IMU_AUTO_PERIOD= 'hffff0000; // period defined by IMU ready
localparam IMU_BIT_DURATION= 'h3; // actual F(scl) will be F(xclk)/2/(IMU_BIT_DURATION+1)
localparam IMU_READY_PERIOD=100000; //100usec
localparam IMU_NREADY_DURATION=10000; //10usec
localparam IMU_GPS_BIT_PERIOD='h18; // 20; // serial communication duration of a bit (in system clocks)
// use start of trigger as a timestamp (in async mode to prevent timestamp jitter)
// parameter X313_WA_DCR1_EARLYTRIGEN='hc; //OBSOLETE!
// parameter X313_WA_DCR1_EARLYTRIGDIS='h8;
`endif
`ifdef TEST_IMU
//wire [11:0] EXT; // bidirectional
//reg TEST_CPU_WR_OK;
//reg TEST_CPU_RD_OK;
reg SERIAL_BIT = 1'b1;
reg GPS1SEC = 1'b0;
reg ODOMETER_PULSE= 1'b0;
integer SERIAL_DATA_FD; // @SuppressThisWarning VEditor
reg IMU_DATA_READY;
wire IMU_SCL=gpio_pins[0];
wire IMU_SDA=gpio_pins[1];
wire IMU_MOSI=gpio_pins[2];
wire IMU_MISO=gpio_pins[3]; // @SuppressThisWarning VEditor just for simulation
reg IMU_EN;
wire IMU_ACTIVE; // @SuppressThisWarning VEditor just for simulation
wire IMU_NMOSI=!IMU_MOSI;
wire [5:1] IMU_TAPS;
reg IMU_LATE_ACKN = 0;
reg IMU_SCLK = 1;
reg IMU_MOSI_REVA;
reg IMU_103695REVA = 1;
wire IMU_MOSI_OUT;
wire IMU_SCLK_OUT;
reg RS232_SENDING_BYTE; // @SuppressThisWarning VEditor just for simulation
reg RS232_SENDING_PAUSE; // @SuppressThisWarning VEditor just for simulation
`endif
`ifdef TEST_IMU
initial begin
SERIAL_DATA_FD=$fopen({`ROOTPATH,"/input_data/gps_data.dat"},"r");
#10000;
while (!$feof (SERIAL_DATA_FD)) begin
repeat (18*IMU_BIT_DURATION) begin wait (axi_hclk); wait (~axi_hclk); end // was 20
send_serial_line;
send_serial_bit('h0a);
send_serial_pause; // was not here
GPS1SEC=1'b1;
send_serial_line;
send_serial_bit('h0a);
GPS1SEC=1'b0;
send_serial_line;
send_serial_bit('h0a);
send_serial_pause;
send_serial_pause;
ODOMETER_PULSE=1'b1;
send_serial_pause;
ODOMETER_PULSE=1'b0;
// repeat (20) send_serial_pause;
end
end
`endif
`ifdef TEST_IMU
assign IMU_MOSI_OUT=IMU_103695REVA? IMU_MOSI_REVA : IMU_MOSI;
assign IMU_SCLK_OUT=IMU_103695REVA?(IMU_SCLK):IMU_SCL;
always @ (posedge IMU_SDA) begin
IMU_EN<=IMU_MOSI;
end
wire IMU_CS=IMU_103695REVA?!IMU_ACTIVE:!(IMU_EN &&IMU_SDA);
reg IMU_MOSI_D;
always @ (posedge IMU_SCLK_OUT) begin
// IMU_MOSI_D<=IMU_MOSI;
IMU_MOSI_D<=IMU_MOSI_OUT;
end
reg [15:0] IMU_LOOPBACK;
always @ (negedge IMU_SCLK_OUT) begin
if (!IMU_CS) IMU_LOOPBACK[15:0]<={IMU_LOOPBACK[14:0],IMU_MOSI_D};
end
assign gpio_pins[3]=IMU_CS?IMU_DATA_READY: IMU_LOOPBACK[15];
PULLUP i_IMU_SDA (.O(IMU_SDA));
PULLUP i_IMU_SCL (.O(IMU_SCL));
initial begin
// SERIAL_DATA_FD=$fopen("gps_data.dat","r");
end
always begin
#(IMU_READY_PERIOD-IMU_NREADY_DURATION) IMU_DATA_READY=1'b0;
#(IMU_NREADY_DURATION) IMU_DATA_READY=1'b1;
end
assign gpio_pins[4]=SERIAL_BIT;
assign gpio_pins[5]=GPS1SEC;
// assign gpio_pins[6]=ODOMETER_PULSE;
assign gpio_pins[9]=ODOMETER_PULSE;
oneshot i_oneshot (.trigger(IMU_NMOSI),
.out(IMU_ACTIVE));
dly5taps i_dly5taps (.dly_in(IMU_NMOSI),
.dly_out(IMU_TAPS[5:1]));
always @ (negedge IMU_ACTIVE or posedge IMU_TAPS[5]) if (!IMU_ACTIVE) IMU_LATE_ACKN<= 1'b0; else IMU_LATE_ACKN<= 1'b1;
always @ (negedge IMU_LATE_ACKN or posedge IMU_TAPS[4]) if (!IMU_LATE_ACKN) IMU_SCLK<= 1'b1; else IMU_SCLK<= ~IMU_SCLK;
always @ (negedge IMU_SCLK) IMU_MOSI_REVA <= IMU_NMOSI;
task send_serial_bit;
input [7:0] data_byte;
reg [7:0] d;
begin
RS232_SENDING_BYTE <= 1;
d <= data_byte;
wait (axi_hclk); wait (~axi_hclk);
// SERIAL_BIT should be 1 here
// Send start bit
SERIAL_BIT <= 1'b0;
repeat (IMU_GPS_BIT_PERIOD) begin wait (axi_hclk); wait (~axi_hclk); end
// Send 8 data bits, LSB first
repeat (8) begin
SERIAL_BIT <= d[0];
#1 d[7:0] <= {1'b0,d[7:1]};
repeat (IMU_GPS_BIT_PERIOD) begin wait (axi_hclk); wait (~axi_hclk); end
end
// Send stop bit
SERIAL_BIT <= 1'b1;
RS232_SENDING_BYTE <= 0; // before stop bit
repeat (IMU_GPS_BIT_PERIOD) begin wait (axi_hclk); wait (~axi_hclk); end
end
endtask
task send_serial_pause;
begin
RS232_SENDING_PAUSE <= 1;
wait (axi_hclk); wait (~axi_hclk);
SERIAL_BIT <= 1'b1;
repeat (16) begin
repeat (IMU_GPS_BIT_PERIOD) begin wait (axi_hclk); wait (~axi_hclk); end
end
RS232_SENDING_PAUSE <= 0;
end
endtask
// SERIAL_DATA_FD=$fopen("gps_data.dat","r");
task send_serial_line;
integer char;
begin
char=0;
while (!$feof (SERIAL_DATA_FD) && (char != 'h0a)) begin
char=$fgetc(SERIAL_DATA_FD);
send_serial_bit(char);
end
end
endtask
`endif
endmodule
module oneshot(trigger,
out);
input trigger;
output out;
reg out;
event start;
parameter duration=4000;
initial out= 0;
always @ (posedge trigger) begin
disable timeout;
#0 -> start;
end
always @start
begin : timeout
out = 1;
# duration out = 0;
end
endmodule
module dly5taps (dly_in,
dly_out);
input dly_in;
output [5:1] dly_out;
reg [5:1] dly_out;
parameter dly=6; // delay per tap, ns
always @ (dly_in) # dly dly_out[1] <= dly_in;
always @ (dly_out[1]) # dly dly_out[2] <= dly_out[1];
always @ (dly_out[2]) # dly dly_out[3] <= dly_out[2];
always @ (dly_out[3]) # dly dly_out[4] <= dly_out[3];
always @ (dly_out[4]) # dly dly_out[5] <= dly_out[4];
endmodule
fpga_version.vh
View file @ e4592ccb
......@@ -35,7 +35,8 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h039300c0; //parallel - chnaging LOGGER_PAGE_IMU 3->0 (how it was in 353) -0.044/16, 79.59%
parameter FPGA_VERSION = 32'h039300c1; //parallel - modified after troubleshooting simulation -0.069/41, 79.90 %
// parameter FPGA_VERSION = 32'h039300c0; //parallel - changing LOGGER_PAGE_IMU 3->0 (how it was in 353) -0.044/16, 79.59%
// parameter FPGA_VERSION = 32'h039300bf; //parallel - mask extrenal timestamps mode -0.043/17 79.56%
// parameter FPGA_VERSION = 32'h039300be; //parallel - adding odd/even pixels shift -0.066/12, 80.26%
// parameter FPGA_VERSION = 32'h039300bd; //hispi, trying the same -0.173/36, 80.95%
......
logger/event_logger.v
View file @ e4592ccb
......@@ -92,7 +92,8 @@ module event_logger#(
// byte-parallel timestamps from 4 sensors channels (in triggered mode all are the same, different only in free running mode)
// each may generate logger event, channel number encoded in bits 25:24 of the external microseconds
input [3:0] sof_mclk, // start of frame (per-channel) to filter out non-first timestamps
input ts_stb_chn0, // @mclk 1 clock before ts_rcv_data is valid
input [7:0] ts_data_chn0, // @mclk byte-wide serialized timestamp message received or local
......@@ -123,19 +124,19 @@ module event_logger#(
wire sda, sda_en, scl, scl_en;
reg [6:0] ctrl_addr=7'h0; // 0 - period, 1 - reserved, 2..31 - registers to log, >32 - gps parameters, >64 - odometer message
reg we_d; // only if wa was 0
reg we_imu;
reg we_gps;
reg we_period;
reg we_bit_duration;
reg we_message;
reg we_config_imu; // bits 1:0, 2 - enable slot[1:0]
reg we_config_gps; // bits 6:3, 7 - enable - {ext,invert, slot[1:0]} slot==0 - disable
reg we_config_msg; // bits 12:8,13 - enable - {invert,extinp[3:0]} extinp[3:0]=='hf' - disable
reg we_config_syn; // bit 14, 15 - enable - enable logging external timestamps
reg we_config_rst; // bit 14, 15 - enable - enable logging external timestamps
reg we_config_debug; // bit 14, 15 - enable - enable logging external timestamps
reg we_bitHalfPeriod;
reg we_d = 0; // only if wa was 0
reg we_imu = 0;
reg we_gps = 0;
reg we_period = 0;
reg we_bit_duration = 0;
reg we_message = 0;
reg we_config_imu = 0; // bits 1:0, 2 - enable slot[1:0]
reg we_config_gps = 0; // bits 6:3, 7 - enable - {ext,invert, slot[1:0]} slot==0 - disable
reg we_config_msg = 0; // bits 12:8,13 - enable - {invert,extinp[3:0]} extinp[3:0]=='hf' - disable
reg we_config_syn = 0; // bit 14, 15 - enable - enable logging external timestamps
reg we_config_rst = 0; // bit 14, 15 - enable - reset
reg we_config_debug = 0; // bit 14, 15 - enable - debug bits set
reg we_bitHalfPeriod = 0;
reg [1:0] config_imu;
......@@ -159,7 +160,7 @@ module event_logger#(
reg [3:0] config_gps_mclk;
reg [4:0] config_msg_mclk;
reg [3:0] config_syn_mclk;
reg config_rst_mclk;
reg config_rst_mclk = 0;
reg [3:0] config_debug_mclk;
reg [15:0] bitHalfPeriod_mclk;
......@@ -211,6 +212,8 @@ module event_logger#(
reg [31:0] cmd_data_r; // valid next after cmd_we;
wire cmd_we;
wire cmd_status;
reg [3:0] timestamps_en; // enable timestamp to go through (first after sof)
assign ext_en = {{(GPIO_N-5){1'b0}},
(config_imu[1:0]==2'h2)?1'b1:1'b0,
......@@ -241,6 +244,9 @@ module event_logger#(
assign timestamp_request[1]=config_gps[3]? (config_gps[2]?nmea_sent_start:gps_ts_stb):gps_pulse1sec_single;
always @ (posedge mclk) begin
timestamps_en <= enable_syn_mclk & (sof_mclk | (timestamps_en & ~{ts_stb_chn3, ts_stb_chn2,ts_stb_chn1, ts_stb_chn0}));
end
// filter gps_pulse1sec
always @ (posedge xclk) begin
......@@ -257,9 +263,25 @@ module event_logger#(
gps_pulse1sec_single <= !gps_pulse1sec_denoise[1] && gps_pulse1sec_denoise[0];
end
// always @ (posedge mclk or posedge mrst) begin // was negedge
always @ (posedge mclk) begin // was negedge
if (cmd_we) cmd_data_r <= cmd_data; // valid next after cmd_we;
we_d <= !mrst && cmd_we && !cmd_a;
we_imu <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:5] == LOGGER_PAGE_IMU);
we_gps <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:5] == LOGGER_PAGE_GPS);
we_message <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:5] == LOGGER_PAGE_MSG);
we_period <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_PERIOD);
we_bit_duration <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_BIT_DURATION);
we_bitHalfPeriod<= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_BIT_HALF_PERIOD);
we_config_imu <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_IMU];
we_config_gps <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_GPS];
we_config_msg <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_MSG];
we_config_syn <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_SYN];
we_config_rst <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_EN];
we_config_debug <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_DBG];
end
always @ (posedge mclk) begin // was negedge
if (cmd_we) cmd_data_r <= cmd_data; // valid next after cmd_we;
/*
we_d <= cmd_we && !cmd_a;
we_imu <= cmd_we && !cmd_a && (ctrl_addr[6:5] == LOGGER_PAGE_IMU);
we_gps <= cmd_we && !cmd_a && (ctrl_addr[6:5] == LOGGER_PAGE_GPS);
......@@ -273,6 +295,7 @@ module event_logger#(
we_config_syn <= cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_SYN];
we_config_rst <= cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_EN];
we_config_debug <= cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_DBG];
*/
if (we_config_imu) config_imu_mclk[1:0] <= cmd_data_r[LOGGER_CONF_IMU - 1 -: LOGGER_CONF_IMU_BITS]; // bits 1:0, 2 - enable slot[1:0]
if (we_config_gps) config_gps_mclk[3:0] <= cmd_data_r[LOGGER_CONF_GPS - 1 -: LOGGER_CONF_GPS_BITS]; // bits 6:3, 7 - enable - {ext,inver, slot[1:0]} slot==0 - disable
......@@ -400,24 +423,24 @@ fixed-length de-noise circuitry with latency 256*T(xclk) (~3usec)
/* logs frame synchronization data from other camera (same as frame sync) */
// ts_stb (mclk) -> trig)
imu_exttime393 i_imu_exttime(
// .rst (rst), // input global reset
.mclk (mclk), // system clock, negedge
.xclk (xclk), // half frequency (80 MHz nominal)
.mrst (mrst), // @mclk - sync reset
.xrst (xrst), // @xclk - sync reset
.en_chn_mclk (enable_syn_mclk), // enable module operation, if 0 - reset
.ts_stb_chn0 (ts_stb_chn0), // input
.ts_data_chn0 (ts_data_chn0), // input[7:0]
.ts_stb_chn1 (ts_stb_chn1), // input
.ts_data_chn1 (ts_data_chn1), // input[7:0]
.ts_stb_chn2 (ts_stb_chn2), // input
.ts_data_chn2 (ts_data_chn2), // input[7:0]
.ts_stb_chn3 (ts_stb_chn3), // input
.ts_data_chn3 (ts_data_chn3), // input[7:0]
.ts (timestamp_request[2]), // timestamop request
.rdy (channel_ready[2]), // data ready
.rd_stb (channel_next[2]), // data read strobe (increment address)
.rdata (extts_data[15:0])); // data out (16 bits)
// .rst (rst), // input global reset
.mclk (mclk), // system clock, negedge
.xclk (xclk), // half frequency (80 MHz nominal)
.mrst (mrst), // @mclk - sync reset
.xrst (xrst), // @xclk - sync reset
.en_chn_mclk (enable_syn_mclk), // input[3:0] enable module operation, if 0 - reset
.ts_stb_chn0 (ts_stb_chn0 && timestamps_en[0]), // input
.ts_data_chn0 (ts_data_chn0), // input[7:0]
.ts_stb_chn1 (ts_stb_chn1 && timestamps_en[1]), // input
.ts_data_chn1 (ts_data_chn1), // input[7:0]
.ts_stb_chn2 (ts_stb_chn2 && timestamps_en[2]), // input
.ts_data_chn2 (ts_data_chn2), // input[7:0]
.ts_stb_chn3 (ts_stb_chn3 && timestamps_en[3]), // input
.ts_data_chn3 (ts_data_chn3), // input[7:0]
.ts (timestamp_request[2]), // timestamop request
.rdy (channel_ready[2]), // data ready
.rd_stb (channel_next[2]), // data read strobe (increment address)
.rdata (extts_data[15:0])); // data out (16 bits)
imu_timestamps393 i_imu_timestamps (
.xclk (xclk), // 80 MHz, posedge
......
logger/imu_exttime393.v
View file @ e4592ccb
......@@ -67,21 +67,23 @@ module imu_exttime393(
output ts, // timestamop request
output reg rdy, // data ready will go up with timestamp request (ahead of actual time), but it will
// anyway be ready sooner, than the local timestamp retrieved ant sent
input rd_stb, // data read strobe (increment address) - continuous 1'b1 until allthe packet is read out
input rd_stb, // data read strobe (increment address) - continuous 1'b1 until all the packet is read out
output [15:0] rdata); // data out (16 bits)
reg [ 4:0] raddr;
reg [ 2:0] raddr; // 2 bits for the address, 1 - overflow
wire en_mclk = |en_chn_mclk;
wire [3:0] ts_stb = {ts_stb_chn3, ts_stb_chn2, ts_stb_chn1, ts_stb_chn0};
wire [3:0] ts_got; // timestamp transferred to the channel FIFO
reg en;
reg rd_stb_r;
reg rd_start; // 1 xclk pulse at the readout start
wire rd_start_mclk;
reg ts_full; // internal 4 x 16 fifo is full (or getting full)
reg ts_pend; // ts fifo waiting to be rdead out
reg [3:0] in_full; // input fifo has (or is acquiring) timestamp
wire pre_copy_w;
reg [1:0] copy_selected; // copying from the winner of 4 input fifos to the x16 output fifo
reg [1:0] copy_selected; // copying from the winner of 4 input FIFOs to the x16 output fifo
reg copy_started;
reg [2:0] copy_cntr; // byte counter for copying
reg [1:0] sel_chn; // selected channel
......@@ -90,11 +92,12 @@ module imu_exttime393(
wire [3:0] chn_pri_w;
wire [1:0] chn_enc_w;
reg [15:0] ts_ram [0:3]; // inner timestamp x16 memory that receives timestamp from one of the 4 input channel fifos
reg [15:0] ts_ram [0:3]; // inner timestamp x16 memory that receives timestamp from one of the 4 input channel FIFOs
wire [31:0] dout_chn;
wire [7:0] copy_data; // data from the selected input fifos
reg [7:0] copy_data_r; // low byte of the timestamp data being copied from one of the input fifos to the ts_ram
reg [7:0] copy_data_r; // low byte of the timestamp data being copied from one of the input FIFOs to the ts_ram
reg rd_stb_mclk;
wire xfer_done_mclk; // valiud information (4 words) are sent out, may start new arbitration
assign chn_pri_w = {in_full[3] & ~(|in_full[2:0]),
in_full[2] & ~(|in_full[1:0]),
in_full[1] & ~in_full[0],
......@@ -102,7 +105,8 @@ module imu_exttime393(
assign chn_enc_w = {chn_pri_w[3] | chn_pri_w[2],
chn_pri_w[3] | chn_pri_w[1]};
assign pre_copy_w = (|in_full) && !copy_selected[0] && !ts_full;
// assign pre_copy_w = (|in_full) && !copy_selected[0] && !ts_full;
assign pre_copy_w = (|in_full) && !copy_selected[0] && !ts_full && !rd_stb_mclk;
assign copy_data = dout_chn[sel_chn * 8 +: 8]; // 4:1 mux
// acquire external timestamps @ mclk
......@@ -110,14 +114,25 @@ module imu_exttime393(
always @ (posedge mclk) begin
copy_started <= pre_copy_started;
if (!en_mclk) ts_full <= 0;
else if (pre_copy_started) ts_full <= 1; // turns on before in_full[*] - || will have no glitches
else if (rd_start_mclk) ts_full <= 0;
rd_stb_mclk <= rd_stb;
if (!en_mclk) ts_full <= 0;
else if (pre_copy_started) ts_full <= 1; // turns on before in_full[*] - || will have no glitches
// else if (rd_start_mclk) ts_full <= 0;
// else if (!ts_pend && !rd_stb_mclk) ts_full <= 0;
else if (xfer_done_mclk) ts_full <= 0;
if (!en_mclk) ts_pend <= 0;
else if (pre_copy_started) ts_pend <= 1;
else if (rd_stb_mclk) ts_pend <= 0;
if (!en_mclk) in_full <= 0;
else in_full <= en_chn_mclk & (ts_stb | (in_full & ~(chn1hot & {4{copy_started}})));
else in_full <= en_chn_mclk & (ts_got | (in_full & ~(chn1hot & {4{copy_started}})));
copy_selected <= {copy_selected[0], pre_copy_w | (copy_selected[0] & ~(&copy_cntr[2:1]))}; // off at count 6
// copy_selected <= {copy_selected[0], (|en_chn_mclk) & (pre_copy_w | (copy_selected[0] & ~(&copy_cntr[2:1])))}; // off at count 6
copy_selected <= {copy_selected[0], (|en_chn_mclk) & (pre_copy_w | (copy_selected[0] & (copy_cntr[2] | ~copy_cntr[1] )))}; // off at count 2
if (pre_copy_w) sel_chn <= chn_enc_w;
......@@ -137,14 +152,18 @@ module imu_exttime393(
en <= en_mclk;
rd_stb_r <= rd_stb;
rd_start <= en && rd_stb && ! rd_stb_r;
if (!en || ts) raddr[4:0] <= 5'h0;
else if (rd_stb) raddr[4:0] <= raddr[4:0] + 1;
if (!en || ts) raddr <= 0;
else if (rd_stb && !raddr[2]) raddr <= raddr + 1;
if (!en) rdy <= 1'b0;
else if (ts) rdy <= 1'b1; // too early, but it will become ready in time, before the local timestamp
else if (rd_stb && (raddr[1:0]==2'h3)) rdy <= 1'b0;
end
dly_var #(.WIDTH(1),.DLY_WIDTH(4)) ts_got0_i (.clk(mclk),.rst(~en_chn_mclk[0]), .dly(4'h7), .din(ts_stb[0]),.dout(ts_got[0]));
dly_var #(.WIDTH(1),.DLY_WIDTH(4)) ts_got1_i (.clk(mclk),.rst(~en_chn_mclk[1]), .dly(4'h7), .din(ts_stb[1]),.dout(ts_got[1]));
dly_var #(.WIDTH(1),.DLY_WIDTH(4)) ts_got2_i (.clk(mclk),.rst(~en_chn_mclk[2]), .dly(4'h7), .din(ts_stb[2]),.dout(ts_got[2]));
dly_var #(.WIDTH(1),.DLY_WIDTH(4)) ts_got3_i (.clk(mclk),.rst(~en_chn_mclk[3]), .dly(4'h7), .din(ts_stb[3]),.dout(ts_got[3]));
timestamp_fifo timestamp_fifo_chn0_i (
......@@ -155,7 +174,7 @@ module imu_exttime393(
.din (ts_data_chn0), // input[7:0]
.aclk (mclk), // input
.arst (mrst), // input
.advance (ts_stb[0]), // enough time
.advance (ts_got[0]), // enough time
.rclk (mclk), // input
.rrst (mrst), // input
.rstb (pre_copy_started && (sel_chn == 2'h0)),// input
......@@ -170,7 +189,7 @@ module imu_exttime393(
.din (ts_data_chn1), // input[7:0]
.aclk (mclk), // input
.arst (mrst), // input
.advance (ts_stb[1]), // enough time
.advance (ts_got[1]), // enough time
.rclk (mclk), // input
.rrst (mrst), // input
.rstb (pre_copy_started && (sel_chn == 2'h1)),// input
......@@ -185,7 +204,7 @@ module imu_exttime393(
.din (ts_data_chn2), // input[7:0]
.aclk (mclk), // input
.arst (mrst), // input
.advance (ts_stb[2]), // enough time
.advance (ts_got[2]), // enough time
.rclk (mclk), // input
.rrst (mrst), // input
.rstb (pre_copy_started && (sel_chn == 2'h2)),// input
......@@ -200,7 +219,7 @@ module imu_exttime393(
.din (ts_data_chn3), // input[7:0]
.aclk (mclk), // input
.arst (mrst), // input
.advance (ts_stb[3]), // enough time
.advance (ts_got[3]), // enough time
.rclk (mclk), // input
.rrst (mrst), // input
.rstb (pre_copy_started && (sel_chn == 2'h3)),// input
......@@ -208,10 +227,13 @@ module imu_exttime393(
);
pulse_cross_clock i_rd_start_mclk (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(rd_start), .out_pulse(rd_start_mclk),.busy());
// pulse_cross_clock i_rd_start_mclk (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(rd_start), .out_pulse(rd_start_mclk),.busy());
pulse_cross_clock i_rd_start_mclk (.rst(!en), .src_clk(xclk), .dst_clk(mclk), .in_pulse(rd_start), .out_pulse(rd_start_mclk),.busy());
pulse_cross_clock i_xfer_done_mclk (.rst(!en), .src_clk(xclk), .dst_clk(mclk), .in_pulse(raddr[1:0]==2'h3), .out_pulse(xfer_done_mclk),.busy());
//
// generate timestamp request as soon as one of the sub-channels starts copying. That time stamp will be stored for this (ext) channel
pulse_cross_clock i_ts (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(pre_copy_w), .out_pulse(ts),.busy());
// pulse_cross_clock i_ts (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(pre_copy_w), .out_pulse(ts),.busy());
pulse_cross_clock i_ts (.rst(en_chn_mclk == 0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(pre_copy_w), .out_pulse(ts),.busy());
endmodule
logger/imu_message393.v
View file @ e4592ccb
......@@ -81,11 +81,11 @@ module imu_message393 (
ts_r <= !trig_denoise[1] && trig_denoise[0];
if (!en || ts_r) raddr[4:0] <= 5'h0;
if (!en || ts_r) raddr[4:0] <= 5'h0;
else if (rd_stb) raddr[4:0] <= raddr[4:0] + 1;
if (ts_r || (rd_stb && (raddr[4:0]==5'h1b)) || !en) rdy_r <= 1'b0;
else if (trig_denoise[1] && !trig_denoise[0]) rdy_r <= 1'b1;
else if (trig_denoise[1] && !trig_denoise[0]) rdy_r <= 1'b1;
end
reg [31:0] odbuf0_ram[0:15];
......
logger/imu_spi393.v
View file @ e4592ccb
......@@ -40,25 +40,24 @@
module imu_spi393(
// input rst,
input mclk, // system clock, negedge TODO:COnvert to posedge!
input xclk, // half frequency (80 MHz nominal)
input we_ra, // write enable for registers to log (@negedge clk)
input we_div,// write enable for clock dividing(@negedge clk)
input we_period,// write enable for IMU cycle period(@negedge clk) 0 - disable, 1 - single, >1 - half bit periods
input [ 4:0] wa, // write address for register (5 bits, @negedge clk)
input [31:0] din, //
output mosi, // to IMU, bit 2 in J9
input miso, // from IMU, bit 3 on J9
input mclk, // system clock, negedge TODO:COnvert to posedge!
input xclk, // half frequency (80 MHz nominal)
input we_ra, // write enable for registers to log (@negedge clk)
input we_div, // write enable for clock dividing(@negedge clk)
input we_period, // write enable for IMU cycle period(@negedge clk) 0 - disable, 1 - single, >1 - half bit periods
input [ 4:0] wa, // write address for register (5 bits, @negedge clk)
input [31:0] din, //
output mosi, // to IMU, bit 2 in J9
input miso, // from IMU, bit 3 on J9
input [ 3:0] config_debug, // bit 0 - long sda_en
output sda, // sda, shared with i2c, bit 1
output sda_en, // enable sda output (when sda==0 and 1 cycle after sda 0->1)
output scl, // scl, shared with i2c, bit 0
output scl_en, // enable scl output (when scl==0 and 1 cycle after sda 0->1)
output ts, // timestamop request
output rdy, // data ready
input rd_stb, // data read strobe (increment address)
output [15:0] rdata); // data out (16 bits)
output sda, // sda, shared with i2c, bit 1
output sda_en, // enable sda output (when sda==0 and 1 cycle after sda 0->1)
output scl, // scl, shared with i2c, bit 0
output scl_en, // enable scl output (when scl==0 and 1 cycle after sda 0->1)
output ts, // timestamp request
output rdy, // data ready
input rd_stb, // data read strobe (increment address)
output [15:0] rdata); // data out (16 bits)
/*
input mclk; // system clock, negedge
input xclk; // half frequency (80 MHz nominal)
......@@ -115,14 +114,14 @@ module imu_spi393(
reg imu_start;
reg ts_r; // delay imu_start by one cycle, so it will be after rdy is reset
reg [31:0] period; // 0 - disable, 1 - single, >1 - period in 50 ns steps
reg [31:0] period=0; // 0 - disable, 1 - single, >1 - period in 50 ns steps
// reg [15:0] di_d;
reg imu_enabled_mclk;
reg imu_enabled_mclk = 0;
reg [1:0] imu_enabled=2'h0;
reg imu_run_mclk;
reg imu_run_mclk = 0;
reg [1:0] imu_run;
reg imu_when_ready_mclk;
reg imu_when_ready_mclk = 0;
reg [1:0] imu_when_ready;
reg imu_run_confirmed;
......@@ -184,7 +183,7 @@ module imu_spi393(
if (we_period) period[31:0] <= din[31:0];
if (we_timer[2]) imu_run_mclk <= (period[31:1]!=31'b0); // double-cycle
if (we_timer[3]) imu_enabled_mclk <= imu_run_mclk | period[0];
if (we_timer[3]) imu_enabled_mclk <= imu_run_mclk | period[0]; // NC393: Why period[0]?
if (we_timer[2]) imu_when_ready_mclk <= &period[31:16]; // double-cycle
......@@ -317,8 +316,8 @@ module imu_spi393(
sngl_wire_stb[2:0] <={sngl_wire_stb[1:0], en & ((scl_r[0] ^ pre_scl) | end_prepare)};
if (!en) sngl_wire_r[0]<=1'b0;
else if ((pre_scl ^scl_r[0]) | end_prepare) sngl_wire_r[0]<=1'b1;
if (!en) sngl_wire_r[0]<=1'b0;
else if ((pre_scl ^scl_r[0]) | end_prepare) sngl_wire_r[0]<=1'b1;
else if (!mosi_reg[15] || sngl_wire_stb[2] || scl_r[0]) sngl_wire_r[0]<=1'b0;
......
logger/logger_arbiter393.v
View file @ e4592ccb
......@@ -39,9 +39,9 @@
`timescale 1ns/1ps
module logger_arbiter393(
input xclk, // half frequency (80 MHz nominal)
input rst, // module reset (sync)
input [3:0] ts_rq_in, // in requests for timestamp (single-cycle - just leading edge )
input xclk, // half frequency (80 MHz nominal)
input rst, // module reset (sync)
input [3:0] ts_rq_in, // in requests for timestamp (single-cycle - just leading edge )
output [3:0] ts_rq, // out request for timestamp, to timestmp module
input [3:0] ts_grant, // granted ts requests from timestamping module
input [3:0] rdy, // channels ready (leading edge - became ready, trailing - no more data, use zero)
......@@ -98,7 +98,7 @@ module logger_arbiter393(
always @ (posedge xclk) begin
ts_rq_in_d[3:0] <= ts_rq_in[3:0];
if (rst) channel_r[1:0] <= 0;
if (wstart) channel_r[1:0] <= {chn1hot[3] | chn1hot[2],chn1hot[3] | chn1hot[1]};
if (wstart) chn_servicing[3:0] <= {chn1hot[3:1], ~|chn1hot[3:1]};
......@@ -109,7 +109,7 @@ module logger_arbiter393(
else ts_rq_r[3:0] <= ~ts_grant & ( wts_rq[3:0] | ts_rq_r[3:0]);
if (rst) ts_valid[3:0] <= 4'h0;
else ts_valid[3:0] <= (ts_grant[3:0] | (ts_valid & ~wts_rq[3:0]));
else ts_valid[3:0] <= (ts_grant[3:0] | (ts_valid & ~wts_rq[3:0]));
channels_ready[3:0] <= ts_valid[3:0] & rdy[3:0] & ~chn_servicing[3:0]; // ready should go down during servicing
......
logger/nmea_decoder393.v
View file @ e4592ccb
......@@ -201,7 +201,7 @@ module nmea_decoder393(
if (restart) vfy_first_comma <= 1'b0;
else if (stb[3] && msb) vfy_first_comma <= last_vfy_sent;
if (restart) valid <= 1'b1; // ready @ stb[2]
if (restart) valid <= 1'b1; // ready @ stb[2]
else if (stb[1] && (ser_di!=gp_exp_bit) &&
(vfy_dollar || vfy_gp || vfy_first_comma || (vfy_sel_sent && !lsbs5))) valid <= 1'b0;
......@@ -292,14 +292,14 @@ module nmea_decoder393(
assign rdata[11: 8] = odbuf2_ram[raddr[4:0]];
assign rdata[15:12] = odbuf3_ram[raddr[4:0]];
reg [3:0] gpxxx_ram[0:3];
reg [3:0] gpxxx_ram[0:15];
always @ (posedge mclk) if (we & ~wa[4]) gpxxx_ram[wa[3:0]] <= wd[3:0];
assign gpxxx_w_one[3:0] = gpxxx_ram[gpxxx_addr[3:0]];
// for each of the four sentences first byte - number of field (<=24), next 3 bytes - formats for each nmea filed (LSB first):
// for each of the four sentences first byte - number of field (<=24), next 3 bytes - formats for each nmea field (LSB first):
// 0 - nibble ("-" -> 0xd, "." -> 0xe), terminated with 0xf
// 1 - byte (2 nibbles), all bytes but last have MSB clear, last - set.
// No padding of nibbles to byte borders, bytes are encoded as 2 nibbles
reg [7:0] format_ram[0:3];
reg [7:0] format_ram[0:15];
always @ (posedge mclk) if (we & wa[4]) format_ram[wa[3:0]] <= wd[7:0];
assign format_data[7:0] = format_ram[{sentence[1:0],format_field[4:3]}];
......
py393/test_mcntrl.py
View file @ e4592ccb
......@@ -77,6 +77,7 @@ import x393_rtc
import x393_jpeg
import vrlg
import x393_export_c
import x393_logger
__all__ = []
__version__ = 0.1
__date__ = '2015-03-01'
......@@ -358,6 +359,8 @@ USAGE
x393Rtc = x393_rtc.X393Rtc(verbose,args.simulated,args.localparams)
x393Jpeg = x393_jpeg.X393Jpeg(verbose,args.simulated,args.localparams)
x393ExportC= x393_export_c.X393ExportC(verbose,args.simulated,args.localparams)
x393Logger = x393_logger.X393Logger(verbose,args.simulated,args.localparams)
#X393Logger
'''
print ("----------------------")
print("x393_mem.__dict__="+str(x393_mem.__dict__))
......@@ -392,6 +395,7 @@ USAGE
extractTasks(x393_rtc.X393Rtc, x393Rtc)
extractTasks(x393_jpeg.X393Jpeg, x393Jpeg)
extractTasks(x393_export_c.X393ExportC, x393ExportC)
extractTasks(x393_logger.X393Logger, x393Logger)
for cmdLine in commands:
print ('Running task: '+str(cmdLine))
......
py393/x393_jpeg.py
View file @ e4592ccb
......@@ -2160,6 +2160,118 @@ jpeg_sim_multi 4
jpeg_sim_multi 8
################## Simulate Parallel 11 - external trigger ####################
./py393/test_mcntrl.py @py393/cocoargs --simulated=localhost:7777
measure_all "*DI"
setup_all_sensors True None 0xf
set_sensor_io_ctl all None None 1 # Set ARO low - check if it is still needed?
#just testing
set_gpio_ports 1 1 # enable software gpio pins and porta (camsync)
set_gpio_pins 0 1 # pin 0 low, pin 1 - high
set_logger_params_file "/home/eyesis/git/x393-neon/attic/imu_config.bin"
set_camsync_period 31 # set bit duration
set_camsync_period 8000 # 80 usec
set_camsync_delay 0 400
set_camsync_delay 1 100
set_camsync_delay 2 200
set_camsync_delay 3 300
#set_camsync_inout <is_out> <bit_number> <active_positive>
set_camsync_inout 1 8 0
#set_camsync_inout 0 7 0
reset_camsync_inout 0 # start with internal trigger
#set_camsync_mode <en=None> <en_snd=None> <en_ts_external=None> <triggered_mode=None> <master_chn=None> <chn_en=None>
set_camsync_mode 1 1 1 1 0 0xf
set_sensor_histogram_window 0 0 4 4 25 21
set_sensor_histogram_window 1 0 4 4 41 21
set_sensor_histogram_window 2 0 4 4 25 41
set_sensor_histogram_window 3 0 4 4 41 41
r
read_control_register 0x430
read_control_register 0x431
write_cmd_frame_sequencer 0 1 2 0x600 0x48 # compressor q page = 1 // too late for frame 2
set_qtables 0 0 80
set_qtables 0 1 70
#irq coming, image not changing - yes
write_cmd_frame_sequencer 0 1 1 0x686 0x280005 #save 4 more lines than sensor has
write_cmd_frame_sequencer 0 1 1 0x680 0x5507 #enable abort
#write_cmd_frame_sequencer 0 1 1 0x6c6 0x300006 #save 4 more lines that compressor has
write_cmd_frame_sequencer 0 1 2 0x600 0x5 #stop compressor `
write_cmd_frame_sequencer 0 1 2 0x680 0x5405 # stop sensor memory (+0) // sensor memory should be controlled first, (9 commands
write_cmd_frame_sequencer 0 1 2 0x6c0 0x5c49 # stop compressor memory (+0)
write_cmd_frame_sequencer 0 1 3 0x686 0x240005 # correct lines
write_cmd_frame_sequencer 0 1 3 0x680 0x5507 # run sensor memory (+1) Can not be 0
write_cmd_frame_sequencer 0 1 4 0x686 0x280005 #save 4 more lines than sensor has
write_cmd_frame_sequencer 0 1 4 0x6c6 0x300006 #save more lines than compressor needs (sensor provides)
write_cmd_frame_sequencer 0 1 4 0x6c0 0x7d4b # run compressor memory (+2)
write_cmd_frame_sequencer 0 1 4 0x600 0x7 # run compressor (+0)
write_cmd_frame_sequencer 0 1 1 0x600 0x48 # compressor q page = 1
write_cmd_frame_sequencer 0 1 4 0x600 0x40 # compressor q page = 0
read_control_register 0x431
read_control_register 0x430
#testing histograms
write_control_register 0x409 0xc0
#set_sensor_io_dly_hispi all 0x48 0x68 0x68 0x68 0x68
#set_sensor_io_ctl all None None None None None 1 None # load all delays?
compressor_control all None None None None None 2
compressor_interrupt_control all clr
compressor_interrupt_control all en
compressor_control all 3
r
read_status 0x21
r
jpeg_sim_multi 4
r
read_status 0x21
r
jpeg_sim_multi 3
r
read_status 0x21
r
write_cmd_frame_sequencer 0 1 1 0x686 0x240005 # correct lines
write_cmd_frame_sequencer 0 1 1 0x6c6 0x200006 # correct lines
write_cmd_frame_sequencer 0 1 1 0x680 0x5507 # run sensor memory, update frame#, reset buffers
write_cmd_frame_sequencer 0 1 1 0x6c0 0x7d4b # run compressor memory
write_cmd_frame_sequencer 0 1 1 0x600 0x7 # run compressor
#switch to external (wired) trigger
set_camsync_inout 0 7 0
jpeg_sim_multi 4
###switch to external (wired) trigger
##set_camsync_inout 0 7 0
jpeg_sim_multi 4
#set_camsync_mode <en=None> <en_snd=None> <en_ts_external=None> <triggered_mode=None> <master_chn=None> <chn_en=None>
#keeping external trigger mode (#9 was switching to internal)
#set_camsync_mode None None None 0
jpeg_sim_multi 4
jpeg_sim_multi 8
################## Serial ####################
cd /usr/local/verilog/; test_mcntrl.py @hargs
......
py393/x393_logger.py 0 → 100644
View file @ e4592ccb
from __future__ import division
from __future__ import print_function
'''
# Copyright (C) 2016, Elphel.inc.
# Class to control event logger module
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http:#www.gnu.org/licenses/>.
@author: Andrey Filippov
@copyright: 2015 Elphel, Inc.
@license: GPLv3.0+
@contact: andrey@elphel.coml
@deffield updated: Updated
'''
__author__ = "Andrey Filippov"
__copyright__ = "Copyright 2015, Elphel, Inc."
__license__ = "GPL"
__version__ = "3.0+"
__maintainer__ = "Andrey Filippov"
__email__ = "andrey@elphel.com"
__status__ = "Development"
#import sys
#import pickle
import struct
from x393_mem import X393Mem
import x393_axi_control_status
import x393_gpio
import x393_utils
#import time
import vrlg
# parameter SYNC_BIT_LENGTH=8-1; /// 7 pixel clock pulses
# SYNC_BIT_LENGTH=8-1 # 7 pixel clock pulses
MEM_PATH='/sys/devices/soc0/elphel393-mem@0/'
BUFFER_ADDRESS_LOGGER_NAME='buffer_address_logger'
BUFFER_PAGES_LOGGER_NAME='buffer_pages_logger'
PAGE_SIZE=4096
# For simulation
BUFFER_ADDRESS_LOGGER = 0x2d000000
BUFFER_LEN_LOGGER = 1024*PAGE_SIZE
class X393Logger(object):
DRY_MODE= True # True
DEBUG_MODE= 1
ADDR_REG = 1
DATA_REG = 0
PCA9500_PP_ADDR = 0x40 #< PCA9500 i2c slave addr for the parallel port (read will be 0x41)
SLOW_SPI = 26 # just for the driver, not written to FPGA (was 23 for NC353)
I2C_SA3 = 28 #Low 3 bits of the SA7 of the PCA9500 slave address
# X313_IMU_PERIOD_ADDR = 0x0 # request period for IMU (in SPI bit periods)
# X313_IMU_DIVISOR_ADDR = 0x1 # xclk (80MHz) clock divisor for half SPI bit period 393: clock is Now clock is logger_clk=100MHz (200 MHz?)
# X313_IMU_RS232DIV_ADDR = 0x2 # serial gps bit duration in xclk (80MHz) periods - 16 bits
# X313_IMU_CONFIGURE_ADDR = 0x3 # IMU logger configuration
X313_IMU_REGISTERS_ADDR = 0x4
X313_IMU_NMEA_FORMAT_ADDR = 0x20
X313_IMU_MESSAGE_ADDR = 0x40 #40..4f, only first 0xe visible
#// offsets in the file (during write)
X313_IMU_PERIOD_OFFS = 0x0
X313_IMU_DIVISOR_OFFS = 0x4
X313_IMU_RS232DIV_OFFS = 0x8
X313_IMU_CONFIGURE_OFFS = 0xc
X313_IMU_SLEEP_OFFS = 0x10
X313_IMU_REGISTERS_OFFS = 0x14 # .. 0x2f
X313_IMU_NMEA_FORMAT_OFFS = 0x30
X313_IMU_MESSAGE_OFFS = 0xB0 # 0xB0..0xE7
WHICH_INIT = 1
WHICH_RESET = 2
WHICH_RESET_SPI = 4
WHICH_DIVISOR = 8
WHICH_RS232DIV = 16
WHICH_NMEA = 32
WHICH_CONFIG = 64
WHICH_REGISTERS = 128
WHICH_MESSAGE = 256
WHICH_PERIOD = 512
WHICH_EN_DMA = 1024
WHICH_EN_LOGGER = 2048
x393_mem=None
x393_axi_tasks=None #x393X393AxiControlStatus
X393_gpio=None
x393_utils=None
verbose=1
def __init__(self, debug_mode=1,dry_mode=True, saveFileName=None):
global BUFFER_ADDRESS_LOGGER, BUFFER_LEN_LOGGER
self.DEBUG_MODE= debug_mode
self.DRY_MODE= dry_mode
self.x393_mem= X393Mem(debug_mode,dry_mode)
self.x393_axi_tasks= x393_axi_control_status.X393AxiControlStatus(debug_mode,dry_mode)
self.x393_utils= x393_utils.X393Utils(debug_mode,dry_mode, saveFileName) # should not overwrite save file path
self.X393_gpio = x393_gpio.X393GPIO(debug_mode,dry_mode, saveFileName)
try:
self.verbose=vrlg.VERBOSE
except:
pass
if dry_mode:
print ("Running in simulated mode, using hard-coded addresses:")
else:
try:
with open(MEM_PATH+BUFFER_ADDRESS_LOGGER_NAME) as sysfile:
BUFFER_ADDRESS_LOGGER=int(sysfile.read(),0)
with open(MEM_PATH+BUFFER_PAGES_LOGGER_NAME) as sysfile:
BUFFER_LEN_LOGGER=PAGE_SIZE*int(sysfile.read(),0)
except:
print("Failed to get reserved physical memory range")
print('BUFFER_ADDRESS_LOGGER=',BUFFER_ADDRESS_LOGGER)
print('BUFFER_LEN_LOGGER=',BUFFER_LEN_LOGGER)
return
print('BUFFER_ADDRESS_LOGGER=0x%x'%(BUFFER_ADDRESS_LOGGER))
print('BUFFER_LEN_LOGGER=0x%x'%(BUFFER_LEN_LOGGER))
"""
/** Initialize FPGA DMA engine for the logger. Obviously requires bitstream to be loaded. */
int logger_init_fpga(int force) ///< if 0, only do if not already initialized
{
x393_status_ctrl_t logger_status_ctrl= {.d32 = 0};
x393_status_ctrl_t mult_saxi_status_ctrl= {.d32 = 0};
x393_mult_saxi_al_t mult_saxi_a= {.d32=0};
x393_mult_saxi_al_t mult_saxi_l= {.d32=0};
x393_mult_saxi_irqlen_t mult_saxi_irqlen= {.d32=0};
if (logger_fpga_configured && !force) return 0; // Already initialized
mult_saxi_a.addr32 = logger_phys >> 2; // in DWORDs
x393_mult_saxi_buf_address(mult_saxi_a, MULT_SAXI_CHN);
mult_saxi_l.addr32 = logger_size >> 2;
x393_mult_saxi_buf_len (mult_saxi_l, MULT_SAXI_CHN);
mult_saxi_irqlen.irqlen = LOGGER_IRQ_DW_BIT;
x393_mult_saxi_irqlen (mult_saxi_irqlen, MULT_SAXI_CHN);
logger_status_ctrl.mode = LOGGER_STATUS_MODE;
set_x393_logger_status_ctrl(logger_status_ctrl);
if (MULT_SAXI_STATUS_MODE) { // do not set (overwrite other channels if 0)
mult_saxi_status_ctrl.mode = MULT_SAXI_STATUS_MODE;
set_x393_mult_saxi_status_ctrl(mult_saxi_status_ctrl);
}
// resets (do once?)
logger_dma_ctrl(0); ///reset DMA
#if LOGGER_USE_IRQ
logger_irq_cmd(X393_IRQ_RESET);
logger_irq_cmd(X393_IRQ_ENABLE);
#endif /* LOGGER_USE_IRQ */
logger_fpga_configured = 1;
return 0;
}
"""
def logger_init_fpga(self, force = False, irqlen = 4, chn = 0):
"""
Initialize DMA channel for the event logger
@param irqlen [ 4: 0] (0) lowest DW address bit that has to change to generate interrupt
@param force if False only do if not yet done
@param chn - mult_saxi channel (0..3), currently connected is 0
"""
print ("logger_init_fpga")
if not force:
if self.x393_axi_tasks.read_control_register(vrlg.MULT_SAXI_ADDR + 2* chn):
return
print("write_control_register 0x%x 0x%x"% (vrlg.MULT_SAXI_ADDR + 2* chn, BUFFER_ADDRESS_LOGGER >> 2))
self.x393_axi_tasks.write_control_register(vrlg.MULT_SAXI_ADDR + 2* chn, BUFFER_ADDRESS_LOGGER >> 2)
print("write_control_register 0x%x 0x%x"% (vrlg.MULT_SAXI_ADDR + 2* chn + 1, BUFFER_LEN_LOGGER >> 2))
self.x393_axi_tasks.write_control_register(vrlg.MULT_SAXI_ADDR + 2* chn + 1, BUFFER_LEN_LOGGER >> 2)
print("write_control_register 0x%x 0x%x"% (vrlg.MULT_SAXI_IRQLEN_ADDR + chn, irqlen))
self.x393_axi_tasks.write_control_register(vrlg.MULT_SAXI_IRQLEN_ADDR + chn, irqlen)
print("program_status 0x%x 0x%x 3 0"%(vrlg.MULT_SAXI_CNTRL_ADDR, vrlg.MULT_SAXI_CNTRL_STATUS))
self.x393_axi_tasks.program_status (vrlg.MULT_SAXI_CNTRL_ADDR, vrlg.MULT_SAXI_CNTRL_STATUS, 3, 0) # auto update
def logger_dma_ctrl (self, mode, chn = 0):
"""
Control dma for channel (the only channel)
@param mode: 0 - reset, 1 - enable/pause, 2 - reset
@param chn - mult_saxi channel (0..3), currently connected is 0
"""
print ("logger_dma_ctrl")
if mode == 0:
d = 0
elif mode == 1:
d = 0x1 << chn
elif mode == 2:
d = 0x11 << chn
else:
raise Exception("mode should be 0 (reset), 1 - pause or 2 - run")
print("write_control_register 0x%x 0x%x"% (vrlg.MULT_SAXI_CNTRL_ADDR + vrlg.MULT_SAXI_CNTRL_MODE, d))
self.x393_axi_tasks.write_control_register(vrlg.MULT_SAXI_CNTRL_ADDR + vrlg.MULT_SAXI_CNTRL_MODE, d)
def logger_interrupt_control (self,
cntrl = "clr",
chn = 0):
"""
Control logger interrupts
@param cntrl - "clr" - clear, "en" - enable, "dis" - disable
@param chn - compressor channel number, "a" or "all" - same for all 4 channels
"""
print ("logger_interrupt_control")
if cntrl.lower() == "clr":
data = 1
elif cntrl.lower() == "dis":
data = 2
elif cntrl.lower() == "en":
data = 3
else:
raise Exception ("logger_interrupt_control(): invalid control mode: %s, only 'clr', 'en' and 'dis' are accepted"%(str(cntrl)))
print("write_control_register 0x%x 0x%x"% (vrlg.MULT_SAXI_CNTRL_ADDR + vrlg.MULT_SAXI_CNTRL_IRQ, data << (2* chn)))
self.x393_axi_tasks.write_control_register(vrlg.MULT_SAXI_CNTRL_ADDR + vrlg.MULT_SAXI_CNTRL_IRQ, data << (2* chn))
def logger_reset(self, rst):
"""
Reset logger module
@param rst: 1 - reset, 0 - normal operation
"""
print ("need to stop logger DMA if it is running")
print ("Resetting logger")
self.x393_axi_tasks.write_control_register(vrlg.LOGGER_ADDR + self.ADDR_REG, vrlg.LOGGER_CONFIG);
data = (2,3)[rst] << (vrlg.LOGGER_CONF_EN - vrlg.LOGGER_CONF_EN_BITS)
self.x393_axi_tasks.write_control_register(vrlg.LOGGER_ADDR + self.DATA_REG, data);
def logger_init(self,config):
"""
Init logger module
@param config - configuration word (only non-FPGA bit fields are processed)
"""
print("Enabling I/O pins for IMU")
data = 3 << 6
self.x393_axi_tasks.write_control_register(vrlg.GPIO_ADDR + vrlg.GPIO_SET_PINS, data << vrlg.GPIO_PORTEN)
i2c_sa8= self.PCA9500_PP_ADDR + (((config >> self.I2C_SA3) & 0x7)<<1) # Here 8-bit is needed, not SA7
enable_IMU = (0xff,0xfd)[(config >> self.SLOW_SPI) & 1] # bit[0] - reset IMU
i2c_err = 0
print("Supposed (not yet implemented) to send i2c command in raw mode - address=0x%x, data=0x%x, result=0x%x\n"%(i2c_sa8, enable_IMU, i2c_err))
self.logger_init_fpga(force = False, irqlen = 4, chn = 0)
self.logger_interrupt_control (cntrl = "en", chn = 0)
def logger_reset_spi(self):
"""
Reset IMU SPI
"""
print("Resetting IMU SPI")
self.logger_set_period(0)
def logger_set_period(self,period):
"""
Set SPI clock divisor
@param period: IMU update period (0xffff - automatic, when IMU is ready)
"""
print("Setting IMU update period = 0x%x"%(period))
self.x393_axi_tasks.write_control_register(vrlg.LOGGER_ADDR + self.ADDR_REG, vrlg.LOGGER_PERIOD)
self.x393_axi_tasks.write_control_register(vrlg.LOGGER_ADDR + self.DATA_REG, period)
def logger_set_divisor(self,divisor):
"""
Set SPI clock divisor
@param divisor: clock divisor for SPI from 100MHz (divisor -1 will be written to FPGA)
"""
print("Setting SPI clock divisor (decremented) value = 0x%x"%(divisor - 1))
self.x393_axi_tasks.write_control_register(vrlg.LOGGER_ADDR + self.ADDR_REG, vrlg.LOGGER_BIT_DURATION)
self.x393_axi_tasks.write_control_register(vrlg.LOGGER_ADDR + self.DATA_REG, divisor - 1)
def logger_set_rs232div(self,divisor):
"""
Set RS232 clock divisor
@param divisor: clock divisor for 1/2 RS232 sample period from 100MHz (divisor -1 will be written to FPGA)
"""
print("Setting RS232 clock divisor (decremented) value = 0x%x"%(divisor - 1))
self.x393_axi_tasks.write_control_register(vrlg.LOGGER_ADDR + self.ADDR_REG, vrlg.LOGGER_BIT_HALF_PERIOD)
self.x393_axi_tasks.write_control_register(vrlg.LOGGER_ADDR + self.DATA_REG, divisor - 1)
def zterm(self,l):
return ''.join(l[:l.index(chr(0))])
def logger_set_nmea(self, nmea_format):
"""
Set RS232 clock divisor
@param nmea_format: encoded NMEA sentences as a string
"""
# int nmea_sel[16];
# int nmea_fpga_frmt[16];
nmea_chars=list(nmea_format)
nmea_sel = [0]*16
nmea_fpga_frmt = [0]*16
for n in range(4):
nmea_chars[32*n+27]=0; # just in case
print("Setting NMEA sentence format for $GP%s"%(self.zterm(nmea_chars[32*n:])))
print("(0x%x, 0x%x, 0x%x\n"%(ord(nmea_chars[32*n]),ord(nmea_chars[32*n+1]),ord(nmea_chars[32*n+2])));
f=0;
for i in range(2,-1,-1):
b=ord(nmea_chars[32*n+i]) # first 3 letters in each sentence
print("n=%d, i=%d, b=0x%x"%(n,i,b))
for j in range (4,-1,-1): # (j=4; j>=0; j--) {
f<<=1;
if ((b & (1<<j)) != 0):
f += 1
print("n=%d, f=0x%x"%(n,f))
for i in range(15):
if ((f & (1<<i))!=0):
nmea_sel[i] |= (1<<n);
f=0
nmea_fpga_frmt[n*4]=0;
#for (i=0; (i<24) && (nmea_format[32*n+3+i]!=0);i++ ) {
for i in range(24):
if nmea_chars[32*n+3+i]==chr(0):
break
b=nmea_chars[32*n+3+i]
if (b=='b') or (b=='B'):
f |= (1<<i);
nmea_fpga_frmt[n*4] += 1
nmea_fpga_frmt[n*4+1] = f & 0xff;
nmea_fpga_frmt[n*4+2] = (f >> 8) & 0xff;
nmea_fpga_frmt[n*4+3] = (f >> 16) & 0xff;
print("Selection data is %x%x%x%x%x%x%x%x%x%x%x%x%x%x%x"%(nmea_sel[0],nmea_sel[1],nmea_sel[2],
nmea_sel[3],nmea_sel[4],nmea_sel[5],nmea_sel[6],nmea_sel[7],nmea_sel[8],nmea_sel[9],
nmea_sel[10],nmea_sel[11],nmea_sel[12],nmea_sel[13],nmea_sel[14]))
print("Format data for sentence 1 is %02x %02x %02x %02x\n"%(nmea_fpga_frmt[ 0],nmea_fpga_frmt[ 1],nmea_fpga_frmt[ 2],nmea_fpga_frmt[ 3]))
print("Format data for sentence 2 is %02x %02x %02x %02x\n"%(nmea_fpga_frmt[ 4],nmea_fpga_frmt[ 5],nmea_fpga_frmt[ 6],nmea_fpga_frmt[ 7]))
print("Format data for sentence 3 is %02x %02x %02x %02x\n"%(nmea_fpga_frmt[ 8],nmea_fpga_frmt[ 9],nmea_fpga_frmt[10],nmea_fpga_frmt[11]))
print("Format data for sentence 4 is %02x %02x %02x %02x\n"%(nmea_fpga_frmt[12],nmea_fpga_frmt[13],nmea_fpga_frmt[14],nmea_fpga_frmt[15]))
self.x393_axi_tasks.write_control_register(vrlg.LOGGER_ADDR + self.ADDR_REG, self.X313_IMU_NMEA_FORMAT_ADDR);
for i in range(16):
self.x393_axi_tasks.write_control_register(vrlg.LOGGER_ADDR + self.DATA_REG, nmea_sel[i])
print("Loaded imu fpga register 0x%x with 0x%x"%(self.X313_IMU_NMEA_FORMAT_ADDR + i, nmea_sel[i] ))
for i in range(16):
self.x393_axi_tasks.write_control_register(vrlg.LOGGER_ADDR + self.DATA_REG, nmea_fpga_frmt[i])
print("Loaded imu fpga register 0x%x with 0x%x"%(self.X313_IMU_NMEA_FORMAT_ADDR + i + 16, nmea_fpga_frmt[i]))
def logger_config(self,config):
"""
Write configuration word to logger module
@param config - logger configuration word
"""
print("Writing logger configuration word: 0x%08x to register 0x%x"%(config & 0x3ffffff, vrlg.LOGGER_CONFIG))
self.x393_axi_tasks.write_control_register(vrlg.LOGGER_ADDR + self.ADDR_REG, vrlg.LOGGER_CONFIG);
self.x393_axi_tasks.write_control_register(vrlg.LOGGER_ADDR + self.DATA_REG, config & 0x3ffffff);
def logger_registers(self,registers):
"""
Specify IMU registers to log data for
@param registers - list of IMU register addresses to write to the logger
"""
self.x393_axi_tasks.write_control_register(vrlg.LOGGER_ADDR + self.ADDR_REG, self.X313_IMU_REGISTERS_ADDR);
for i,c in enumerate(registers):
d = ord(c)
print("%d: logging IMU register with 0x%lx"%(i+1, d))
self.x393_axi_tasks.write_control_register(vrlg.LOGGER_ADDR + self.DATA_REG, d);
def logger_message(self,message):
"""
Set odometer message (up to 56 bytes)
@param message - odometer message as a string
"""
lmessage = list(message)
if len(lmessage) < 56:
lmessage +=chnr(0)*(56-len(lmessage))
lmessage = lmessage[:56]
print("Setting odometer message %56s"%(self.zterm(lmessage)))
self.x393_axi_tasks.write_control_register(vrlg.LOGGER_ADDR + self.ADDR_REG, self.X313_IMU_REGISTERS_ADDR)
for i in range(0,56,4):
d=ord(lmessage[i]) + (ord(lmessage[i+1]) << 8) + (ord(lmessage[i+1]) << 16) + (ord(lmessage[i+1]) << 24)
print("%d: message 4 bytes= 0x%08x"%((i//4)+1,d))
self.x393_axi_tasks.write_control_register(vrlg.LOGGER_ADDR + self.DATA_REG, d)
def logger_en_dma(self):
"""
Turn on DMA
"""
self.logger_dma_ctrl (mode = 2, chn = 0) # mode = 2 - enable and run
print("Turn on DMA here")
def logger_en_logger(self):
"""
Enable logger (turn off reset)
"""
print("Turning off logger reset")
self.logger_reset(0)
def set_logger_params(self, which,wbuf):
"""
Set logger parameters from the string buffer (same as in the driver)
@param which - bitmask of parameters to set:
WHICH_INIT = 1
WHICH_RESET = 2
WHICH_RESET_SPI = 4
WHICH_DIVISOR = 8
WHICH_RS232DIV = 16
WHICH_NMEA = 32
WHICH_CONFIG = 64
WHICH_REGISTERS = 128
WHICH_MESSAGE = 256
WHICH_PERIOD = 512
WHICH_EN_DMA = 1024
WHICH_EN_LOGGER = 2048
@param wbuf - string with configuration data (as generated by start_gps_compas.php
"""
period = struct.unpack_from("<I", wbuf, offset=self.X313_IMU_PERIOD_OFFS)[0]
divisor = struct.unpack_from("<I", wbuf, offset=self.X313_IMU_DIVISOR_OFFS)[0]
rs232_div = struct.unpack_from("<I", wbuf, offset=self.X313_IMU_RS232DIV_OFFS)[0]
if (self.DRY_MODE):
rs232_div = 8
config = struct.unpack_from("<I", wbuf, offset=self.X313_IMU_CONFIGURE_OFFS)[0]
message = wbuf[self.X313_IMU_MESSAGE_OFFS: self.X313_IMU_MESSAGE_OFFS+56]
nmea_format = wbuf[self.X313_IMU_NMEA_FORMAT_OFFS:self.X313_IMU_NMEA_FORMAT_OFFS+128]
registers = wbuf[self.X313_IMU_REGISTERS_OFFS: self.X313_IMU_NMEA_FORMAT_OFFS]
for i, d in enumerate(wbuf):
if (i & 0x1f) == 0:
print("\n %03x"%(i), end = "")
print(" %02x"%(ord(wbuf[i])),end="")
if which & self.WHICH_RESET:
self.logger_reset(1)
if which & self.WHICH_INIT:
self.logger_init(config)
if which & self.WHICH_RESET_SPI:
self.logger_reset_spi()
if which & self.WHICH_DIVISOR:
self.logger_set_divisor(divisor)
if which & self.WHICH_RS232DIV:
self.logger_set_rs232div(rs232_div)
if which & self.WHICH_NMEA:
self.logger_set_nmea(nmea_format)
if which & self.WHICH_CONFIG:
self.logger_config(config)
if which & self.WHICH_REGISTERS:
self.logger_registers(registers)
if which & self.WHICH_MESSAGE:
self.logger_message(message)
if which & self.WHICH_PERIOD:
self.logger_set_period(period)
if which & self.WHICH_EN_DMA:
self.logger_en_dma()
if which & self.WHICH_EN_LOGGER:
self.logger_en_logger()
def set_logger_params_file(self, file_path="/home/eyesis/git/x393-neon/attic/imu_config.bin", which = 0x7fb): # 0x3f9):
"""
Set logger parameters from the string buffer (same as in the driver)
@param which - bitmask of parameters to set:
WHICH_INIT = 1
WHICH_RESET = 2
WHICH_RESET_SPI = 4
WHICH_DIVISOR = 8
WHICH_RS232DIV = 16
WHICH_NMEA = 32
WHICH_CONFIG = 64
WHICH_REGISTERS = 128
WHICH_MESSAGE = 256
WHICH_PERIOD = 512
WHICH_EN_DMA = 1024
WHICH_EN_LOGGER = 2048
@param wbuf - string with configuration data (as generated by start_gps_compas.php
"""
with open (file_path,"r") as f:
wbuf=f.read()
self.set_logger_params(which = which, wbuf=wbuf)
"""
def logger_reset(self, rst):
def logger_init(self,config):
def logger_reset_spi(self):
def logger_set_divisor(self,divisor):
def logger_set_rs232div(self,divisor):
def zterm(self,l):
def logger_set_nmea(self, nmea_format):
def logger_config(self,config):
def logger_registers(self,registers):
def logger_message(self,message):
def logger_en_dma(self):
def logger_en_logger(self):
unsigned long * period= (unsigned long *) &wbuf[X313_IMU_PERIOD_OFFS];
unsigned long * divisor= (unsigned long *) &wbuf[X313_IMU_DIVISOR_OFFS];
unsigned long * rs232_div= (unsigned long *) &wbuf[X313_IMU_RS232DIV_OFFS];
unsigned long * config= (unsigned long *) &wbuf[X313_IMU_CONFIGURE_OFFS];
unsigned long * message= (unsigned long *) &wbuf[X313_IMU_MESSAGE_OFFS];
char * nmea_format= (char *) &wbuf[X313_IMU_NMEA_FORMAT_OFFS];
period = struct.unpack_from("<I", wbuf, offset=X313_IMU_PERIOD_OFFS)[0]
divisor = struct.unpack_from("<I", wbuf, offset=X313_IMU_DIVISOR_OFFS)[0]
rs232_div = struct.unpack_from("<I", wbuf, offset=X313_IMU_RS232DIV_OFFS)[0]
config = struct.unpack_from("<I", wbuf, offset=X313_IMU_CONFIGURE_OFFS)[0]
hex(period) '0xffffffff'
hex(divisor) '0x140a'
hex(rs232_div) '0x364'
hex(config) '0x350eab5'
>>> with open ("/home/eyesis/git/x393-neon/attic/aaa","r") as f:
... aaa=f.read()
which= 0x3f9
WHICH_INIT = 1
WHICH_RESET = 2
WHICH_RESET_SPI = 4
WHICH_DIVISOR = 8
WHICH_RS232DIV = 16
WHICH_NMEA = 32
WHICH_CONFIG = 64
WHICH_REGISTERS = 128
WHICH_MESSAGE = 256
WHICH_PERIOD = 512
WHICH_EN_DMA = 1024
WHICH_EN_LOGGER = 2048
#define X313_IMU_REGISTERS_ADDR 0x4
#define X313_IMU_NMEA_FORMAT_ADDR 0x20
#define X313_IMU_MESSAGE_ADDR 0x40 ///< 40..4f, only first 0xe visible
// offsets in the file (during write)
#define X313_IMU_PERIOD_OFFS 0x0
#define X313_IMU_DIVISOR_OFFS 0x4
#define X313_IMU_RS232DIV_OFFS 0x8
#define X313_IMU_CONFIGURE_OFFS 0xc
#define X313_IMU_SLEEP_OFFS 0x10
#define X313_IMU_REGISTERS_OFFS 0x14 // .. 0x2f
#define X313_IMU_NMEA_FORMAT_OFFS 0x30
#define X313_IMU_MESSAGE_OFFS 0xB0 // 0xB0..0xE7
def set_gpio_ports(self,
port_soft = None,
port_a = None,
port_b = None,
port_c = None):
Set status GPIO ports (None - no change, False - disable, True - enable)
@param port_soft - software-controlled port
@param port_a - port A : camsync
@param port_b - port B : motors on 10353, unused on 10393
@param port_c - port C : logger (IMU/GPS, external)
data = 0
if not port_soft is None:
data |= (2,3)[port_soft]
if not port_a is None:
data |= (2,3)[port_a] << 2
if not port_b is None:
data |= (2,3)[port_a] << 4
if not port_c is None:
data |= (2,3)[port_a] << 6
self.x393_axi_tasks.write_control_register(vrlg.GPIO_ADDR + vrlg.GPIO_SET_PINS, data << vrlg.GPIO_PORTEN)
parameter LOGGER_ADDR = 'h720, //..'h721
parameter LOGGER_STATUS = 'h722, // .. 'h722
parameter LOGGER_STATUS_REG_ADDR = 'h39, // just 1 location)
parameter LOGGER_MASK = 'h7fe,
parameter LOGGER_STATUS_MASK = 'h7ff,
//First 4 registers are not used (it is when time stamps are sent)
parameter LOGGER_PAGE_IMU = 0, // 'h04..'h1f - overlaps with period/duration/halfperiod/config? (was so in x353)
parameter LOGGER_PAGE_GPS = 1, // 'h20..'h3f
parameter LOGGER_PAGE_MSG = 2, // 'h40..'h5f
parameter LOGGER_PERIOD = 0,
parameter LOGGER_BIT_DURATION = 1,
parameter LOGGER_BIT_HALF_PERIOD = 2, //rs232 half bit period
parameter LOGGER_CONFIG = 3,
parameter LOGGER_CONF_IMU = 2,
parameter LOGGER_CONF_IMU_BITS = 2,
parameter LOGGER_CONF_GPS = 7,
parameter LOGGER_CONF_GPS_BITS = 4,
parameter LOGGER_CONF_MSG = 13,
parameter LOGGER_CONF_MSG_BITS = 5,
parameter LOGGER_CONF_SYN = 18, // 15,
parameter LOGGER_CONF_SYN_BITS = 4, // 1,
parameter LOGGER_CONF_EN = 20, // 17,
parameter LOGGER_CONF_EN_BITS = 1,
parameter LOGGER_CONF_DBG = 25, // 22,
parameter LOGGER_CONF_DBG_BITS = 4,
parameter GPIO_N = 10 // number of GPIO bits to control
X313_IMU_PERIOD_OFFS = 0x0
X313_IMU_DIVISOR_OFFS = 0x4
X313_IMU_RS232DIV_OFFS = 0x8
X313_IMU_CONFIGURE_OFFS = 0xc
X313_IMU_SLEEP_OFFS = 0x10
X313_IMU_REGISTERS_OFFS = 0x14 # .. 0x2f
X313_IMU_NMEA_FORMAT_OFFS = 0x30
X313_IMU_MESSAGE_OFFS = 0xB0 # 0xB0..0xE7
"""
\ No newline at end of file
x393.v
View file @ e4592ccb
......@@ -2314,7 +2314,8 @@ assign axi_grst = axi_rst_pre;
.ts_local_data (ts_logegr_data), // input[7:0]
.ext_di (gpio_rd), // input[9:0]
.ext_do (gpio_logger), // output[9:0]
.ext_en (gpio_logger_en), // output[9:0]
.ext_en (gpio_logger_en), // output[9:0]
.sof_mclk (sof_out_mclk), // input[3:0]
.ts_stb_chn0 (ts_pre_stb[0]), // input
.ts_data_chn0 (ts_data[0 * 8 +: 8]), // input[7:0]
.ts_stb_chn1 (ts_pre_stb[1]), // input
......
x393_parallel.bit
View file @ e4592ccb
No preview for this file type
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment