merged with framepars for the event logger (e4592ccb) · Commits · Elphel / x393

.settings/com.elphel.vdt.cocotb.prefs

+1 −1

Original line number	Diff line number	Diff line
		@@ -4,7 +4,7 @@ cocotb_@_CocotbExtraFiles=glbl.v<-@\#\#@->
		cocotb_@_CocotbIncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
		cocotb_@_CocotbMODULE=x393_cocotb_server<-@\#\#@->
		cocotb_@_CocotbTESTCASE=run_test<-@\#\#@->
		cocotb_@_GTKWaveSavFile=x393_cocotb_02.sav
		cocotb_@_GTKWaveSavFile=x393_cocotb_03.sav
		cocotb_@_GrepFindErr=error\|ERROR
		cocotb_@_GrepFindErrWarn=error\|warning\|ERROR\|WARNING
		cocotb_@_PatternInfo=.[\\s.](\\w\\.py)\:([0-9]+)\\s\\S\\s\\S\\s(.)

axi/mult_saxi_wr.v

+3 −1

Original line number	Diff line number	Diff line
		@@ -427,7 +427,9 @@ module mult_saxi_wr #(
		.MULT_SAXI_BSLOG3 (MULT_SAXI_BSLOG3)
		) mult_saxi_wr_pointers_i (
		.mclk (mclk), // input
		.mrst (mrst), // input
		.aclk (aclk), // input
		.arst (arst), // input
		.chn_en_mclk (en_chn_mclk), // input[3:0]
		.sa_len_di (cmd_data[29:0]), // input[29:0]
		.sa_len_wa (cmd_a[2:0]), // input[2:0]
		@@ -549,7 +551,7 @@ module mult_saxi_wr #(
		.stb (cmd_stb), // input
		.addr (cmd_a), // output[3:0]
		.data (cmd_data), // output[31:0]
		.we ({cmd_we_sa_len,we_ctrl,irq_log_we}) // output
		.we ({irq_log_we,we_ctrl,cmd_we_sa_len}) // output
		);

		// now - converting all to parallel (TODO: use RAM for multi-word status data)

axi/mult_saxi_wr_pointers.v

+10 −2

Original line number	Diff line number	Diff line
		@@ -45,7 +45,9 @@ module mult_saxi_wr_pointers#(
		parameter MULT_SAXI_BSLOG3 = 4
		)(
		input mclk, // system clock
		input mrst, //
		input aclk, // global clock to run s_axi (@150MHz?)
		input arst, //
		input [3:0] chn_en_mclk, // enable this channle ( 0 - reset)
		input [29:0] sa_len_di, // input data to write pointers address/data
		input [ 2:0] sa_len_wa, // channel address to write sa/lengths
		@@ -57,7 +59,7 @@ module mult_saxi_wr_pointers#(
		// provide address and burst length for AXI @aclk, will stay until ackn
		output reg [29:0] axi_addr,
		output reg [3:0] axi_len,
		// write data to external pointre memory (to be read out by PIO) @ aclk
		// write data to external pointer memory (to be read out by PIO) @ aclk
		// alternatively - read out directly from ptr_ram?
		output [29:0] pntr_wd, // @aclk
		output [1:0] pntr_wa,
		@@ -92,6 +94,7 @@ module mult_saxi_wr_pointers#(
		reg [30:0] ptr_rollover;
		reg [4:0] burst_size; // ROM
		wire [29:0] ptr_wd;
		reg arst_d; //delayed version of arst

		assign reset_rq_enc = {reset_rq_pri[3] \| reset_rq_pri[2],
		reset_rq_pri[3] \| reset_rq_pri[1]};
		@@ -134,7 +137,12 @@ module mult_saxi_wr_pointers#(

		always @ (posedge aclk) begin
		chn_en_aclk <= chn_en_mclk;
		reset_rq <= rst_pntr_aclk \| (reset_rq & ~({4{resetting[0] &~ resetting[1]}} & reset_rq_pri));
		arst_d <= arst; // probably not needed?

		if (arst) reset_rq <= ~0; // or ~0 ? Add auto reset after
		// else reset_rq <= {4{arst_d}} \| rst_pntr_aclk \| (reset_rq & ~({4{resetting[0] &~ resetting[1]}} & reset_rq_pri));
		else reset_rq <= rst_pntr_aclk \| (reset_rq & ~({4{resetting[0] &~ resetting[1]}} & reset_rq_pri));

		if (start_resetting_w) reset_rq_pri <= {reset_rq[3] & ~(\|reset_rq[2:0]),
		reset_rq[2] & ~(\|reset_rq[1:0]),
		reset_rq[1] & ~reset_rq[0],

Admin message