continue playing (b721ae66) · Commits · Elphel / x393

axi/axibram_read.v

+17 −20

Original line number	Original line	Diff line number	Diff line
	@@ -25,20 +25,16 @@ module axibram_read #(
	parameter ADDRESS_BITS = 10 // number of memory address bits		parameter ADDRESS_BITS = 10 // number of memory address bits
	)(		)(
	input aclk, // clock - should be buffered		input aclk, // clock - should be buffered
	// input aresetn, // reset, active low		// input rst, // reset, active high
	input rst, // reset, active high		input arst, // @posedge aclk sync reset, active high
	// AXI Read Address		// AXI Read Address
	input [31:0] araddr, // ARADDR[31:0], input		input [31:0] araddr, // ARADDR[31:0], input
	input arvalid, // ARVALID, input		input arvalid, // ARVALID, input
	output arready, // ARREADY, output		output arready, // ARREADY, output
	input [11:0] arid, // ARID[11:0], input		input [11:0] arid, // ARID[11:0], input
	// input [ 1:0] arlock, // ARLOCK[1:0], input
	// input [ 3:0] archache,// ARCACHE[3:0], input
	// input [ 2:0] arprot, // ARPROT[2:0], input
	input [ 3:0] arlen, // ARLEN[3:0], input		input [ 3:0] arlen, // ARLEN[3:0], input
	input [ 1:0] arsize, // ARSIZE[1:0], input		input [ 1:0] arsize, // ARSIZE[1:0], input
	input [ 1:0] arburst, // ARBURST[1:0], input		input [ 1:0] arburst, // ARBURST[1:0], input
	// input [ 3:0] adqos, // ARQOS[3:0], input
	// AXI Read Data		// AXI Read Data
	output [31:0] rdata, // RDATA[31:0], output		output [31:0] rdata, // RDATA[31:0], output
	output reg rvalid, // RVALID, output		output reg rvalid, // RVALID, output
	@@ -145,30 +141,30 @@ module axibram_read #(

	assign rdata[31:0] = bram_rdata; // data out		assign rdata[31:0] = bram_rdata; // data out

	always @ (posedge aclk or posedge rst) begin		always @ (posedge aclk) begin
	`ifdef USE_SHORT_REN_REGEN		`ifdef USE_SHORT_REN_REGEN
	if (rst) bram_regen_r <= 0;		if (arst) bram_regen_r <= 0;
	else bram_regen_r <= bram_ren;		else bram_regen_r <= bram_ren;
	`endif		`endif

	if (rst) pre_last_in_burst_r <= 0;		if (arst) pre_last_in_burst_r <= 0;
	// else if (start_read_burst_w) pre_last_in_burst_r <= (read_left==4'b0);		// else if (start_read_burst_w) pre_last_in_burst_r <= (read_left==4'b0);
	else if (bram_reg_re_w) pre_last_in_burst_r <= (read_left==4'b0);		else if (bram_reg_re_w) pre_last_in_burst_r <= (read_left==4'b0);

	if (rst) rburst[1:0] <= 0;		if (arst) rburst[1:0] <= 0;
	else if (start_read_burst_w) rburst[1:0] <= arburst_out[1:0];		else if (start_read_burst_w) rburst[1:0] <= arburst_out[1:0];

	if (rst) rlen[3:0] <= 0;		if (arst) rlen[3:0] <= 0;
	else if (start_read_burst_w) rlen[3:0] <= arlen_out[3:0];		else if (start_read_burst_w) rlen[3:0] <= arlen_out[3:0];

	if (rst) read_in_progress <= 0;		if (arst) read_in_progress <= 0;
	else read_in_progress <= read_in_progress_w;		else read_in_progress <= read_in_progress_w;

	if (rst) read_in_progress_d <= 0;		if (arst) read_in_progress_d <= 0;
	// else read_in_progress_d <= read_in_progress_d_w;		// else read_in_progress_d <= read_in_progress_d_w;
	else if (bram_reg_re_w) read_in_progress_d <= read_in_progress_d_w;		else if (bram_reg_re_w) read_in_progress_d <= read_in_progress_d_w;

	if (rst) read_in_progress_or <= 0;		if (arst) read_in_progress_or <= 0;
	// else read_in_progress_or <= read_in_progress_d_w \|\| read_in_progress_w;		// else read_in_progress_or <= read_in_progress_d_w \|\| read_in_progress_w;
	// else if (bram_reg_re_w) read_in_progress_or <= read_in_progress_d_w \|\| read_in_progress_w;		// else if (bram_reg_re_w) read_in_progress_or <= read_in_progress_d_w \|\| read_in_progress_w;
	// FIXME:		// FIXME:
	@@ -177,22 +173,23 @@ module axibram_read #(
	// reg read_in_progress_d=0; // delayed by one active cycle (not skipped)		// reg read_in_progress_d=0; // delayed by one active cycle (not skipped)
	// reg read_in_progress_or=0; // read_in_progress \|\| read_in_progress_d		// reg read_in_progress_or=0; // read_in_progress \|\| read_in_progress_d

	if (rst) read_left <= 0;		if (arst) read_left <= 0;
	else if (start_read_burst_w) read_left <= arlen_out[3:0]; // precedence over inc		else if (start_read_burst_w) read_left <= arlen_out[3:0]; // precedence over inc
	else if (bram_reg_re_w) read_left <= read_left-1; //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target.		else if (bram_reg_re_w) read_left <= read_left-1; //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target.

	if (rst) read_address <= {ADDRESS_BITS{1'b0}};		if (arst) read_address <= {ADDRESS_BITS{1'b0}};
	else if (start_read_burst_w) read_address <= araddr_out[ADDRESS_BITS-1:0]; // precedence over inc		else if (start_read_burst_w) read_address <= araddr_out[ADDRESS_BITS-1:0]; // precedence over inc
	else if (bram_reg_re_w) read_address <= next_rd_address_w;		else if (bram_reg_re_w) read_address <= next_rd_address_w;

	if (rst) rvalid <= 1'b0;		if (arst) rvalid <= 1'b0;
	else if (bram_reg_re_w && read_in_progress_d) rvalid <= 1'b1;		else if (bram_reg_re_w && read_in_progress_d) rvalid <= 1'b1;
	else if (rready) rvalid <= 1'b0;		else if (rready) rvalid <= 1'b0;

	if (rst) rlast <= 1'b0;		if (arst) rlast <= 1'b0;
	else if (last_in_burst_d_w) rlast <= 1'b1;		else if (last_in_burst_d_w) rlast <= 1'b1;
	else if (rready) rlast <= 1'b0;		else if (rready) rlast <= 1'b0;
	end		end

	always @ (posedge aclk) begin //SuppressThisWarning ISExst Assignment to bram_reg_re_0 ignored, since the identifier is never used		always @ (posedge aclk) begin //SuppressThisWarning ISExst Assignment to bram_reg_re_0 ignored, since the identifier is never used
	// bram_reg_re_0 <= read_in_progress_w && !pre_rvalid_w;		// bram_reg_re_0 <= read_in_progress_w && !pre_rvalid_w;

	@@ -240,9 +237,9 @@ module axibram_read #(

	fifo_same_clock #( .DATA_WIDTH(ADDRESS_BITS+20),.DATA_DEPTH(4))		fifo_same_clock #( .DATA_WIDTH(ADDRESS_BITS+20),.DATA_DEPTH(4))
	raddr_i (		raddr_i (
	.rst(rst),		.rst(1'b0),
	.clk(aclk),		.clk(aclk),
	.sync_rst(1'b0), // input		.sync_rst(arst),
	.we(arvalid && arready),		.we(arvalid && arready),
	.re(start_read_burst_w),		.re(start_read_burst_w),
	.data_in({arid[11:0], arburst[1:0],arsize[1:0],arlen[3:0],araddr[ADDRESS_BITS+1:2]}),		.data_in({arid[11:0], arburst[1:0],arsize[1:0],arlen[3:0],araddr[ADDRESS_BITS+1:2]}),

axi/axibram_write.v

+19 −38

Original line number	Original line	Diff line number	Diff line
	@@ -26,21 +26,16 @@ module axibram_write #(
	parameter ADDRESS_BITS = 10 // number of memory address bits		parameter ADDRESS_BITS = 10 // number of memory address bits
	)(		)(
	input aclk, // clock - should be buffered		input aclk, // clock - should be buffered
	// input aresetn, // reset, active low		input arst, // @aclk sync reset, active high
	input rst, // reset, active highw

	// AXI Write Address		// AXI Write Address
	input [31:0] awaddr, // AWADDR[31:0], input		input [31:0] awaddr, // AWADDR[31:0], input
	input awvalid, // AWVALID, input		input awvalid, // AWVALID, input
	output awready, // AWREADY, output		output awready, // AWREADY, output
	input [11:0] awid, // AWID[11:0], input		input [11:0] awid, // AWID[11:0], input
	// input [ 1:0] awlock, // AWLOCK[1:0], input
	// input [ 3:0] awcache, // AWCACHE[3:0], input
	// input [ 2:0] awprot, // AWPROT[2:0], input
	input [ 3:0] awlen, // AWLEN[3:0], input		input [ 3:0] awlen, // AWLEN[3:0], input
	input [ 1:0] awsize, // AWSIZE[1:0], input		input [ 1:0] awsize, // AWSIZE[1:0], input
	input [ 1:0] awburst, // AWBURST[1:0], input		input [ 1:0] awburst, // AWBURST[1:0], input
	// input [ 3:0] awqos, // AWQOS[3:0], input
	// AXI PS Master GP0: Write Data		// AXI PS Master GP0: Write Data
	input [31:0] wdata, // WDATA[31:0], input		input [31:0] wdata, // WDATA[31:0], input
	input wvalid, // WVALID, input		input wvalid, // WVALID, input
	@@ -141,45 +136,31 @@ module axibram_write #(
	assign start_write_burst_w=w_nempty_ready && aw_nempty_ready && (!write_in_progress \|\| (w_nempty_ready && ((write_left[3:0]==4'b0) \|\| wlast_out)));		assign start_write_burst_w=w_nempty_ready && aw_nempty_ready && (!write_in_progress \|\| (w_nempty_ready && ((write_left[3:0]==4'b0) \|\| wlast_out)));
	assign write_in_progress_w=w_nempty_ready && aw_nempty_ready \|\| (write_in_progress && !(w_nempty_ready && ((write_left[3:0]==4'b0) \|\| wlast_out)));		assign write_in_progress_w=w_nempty_ready && aw_nempty_ready \|\| (write_in_progress && !(w_nempty_ready && ((write_left[3:0]==4'b0) \|\| wlast_out)));

	always @ (posedge aclk or posedge rst) begin		always @ (posedge aclk) begin
	if (rst) wburst[1:0] <= 0;		if (arst) wburst[1:0] <= 0;
	else if (start_write_burst_w) wburst[1:0] <= awburst_out[1:0];		else if (start_write_burst_w) wburst[1:0] <= awburst_out[1:0];

	if (rst) wlen[3:0] <= 0;		if (arst) wlen[3:0] <= 0;
	else if (start_write_burst_w) wlen[3:0] <= awlen_out[3:0];		else if (start_write_burst_w) wlen[3:0] <= awlen_out[3:0];

	if (rst) write_in_progress <= 0;		if (arst) write_in_progress <= 0;
	else write_in_progress <= write_in_progress_w;		else write_in_progress <= write_in_progress_w;

	if (rst) write_left <= 0;		if (arst) write_left <= 0;
	else if (start_write_burst_w) write_left <= awlen_out[3:0]; // precedence over inc		else if (start_write_burst_w) write_left <= awlen_out[3:0]; // precedence over inc
	else if (bram_we_w) write_left <= write_left-1; //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target.		else if (bram_we_w) write_left <= write_left-1; //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target.

	if (rst) write_address <= {ADDRESS_BITS{1'b0}};		if (arst) write_address <= {ADDRESS_BITS{1'b0}};
	else if (start_write_burst_w) write_address <= awaddr_out[ADDRESS_BITS-1:0]; // precedence over inc		else if (start_write_burst_w) write_address <= awaddr_out[ADDRESS_BITS-1:0]; // precedence over inc
	else if (bram_we_w) write_address <= next_wr_address_w;		else if (bram_we_w) write_address <= next_wr_address_w;

	if (rst) dev_ready_r <= 1'b0;		if (arst) dev_ready_r <= 1'b0;
	else dev_ready_r <= dev_ready;		else dev_ready_r <= dev_ready;
	end		end
	// ** Write response channel **		// ** Write response channel **
	wire [ 1:0] bresp_in;		wire [ 1:0] bresp_in;
	assign bresp_in=2'b0;		assign bresp_in=2'b0;

	/*
	output bvalid, // BVALID, output
	input bready, // BREADY, input
	output [11:0] bid, // BID[11:0], output
	output [ 1:0] bresp // BRESP[1:0], output

	*/
	/*
	reg bram_reg_re_r;
	always @ (posedge aclk) begin
	bram_reg_re_r <= bram_reg_re_w;
	end
	*/

	// external memory interface (write only)		// external memory interface (write only)
	assign pre_awaddr=awaddr_out[ADDRESS_BITS-1:0];		assign pre_awaddr=awaddr_out[ADDRESS_BITS-1:0];
	assign start_burst=start_write_burst_w;		assign start_burst=start_write_burst_w;
	@@ -199,9 +180,9 @@ module axibram_write #(
	`endif		`endif
	fifo_same_clock #( .DATA_WIDTH(20+ADDRESS_BITS),.DATA_DEPTH(4))		fifo_same_clock #( .DATA_WIDTH(20+ADDRESS_BITS),.DATA_DEPTH(4))
	waddr_i (		waddr_i (
	.rst (rst),		.rst (1'b0), //rst),
	.clk (aclk),		.clk (aclk),
	.sync_rst (1'b0),		.sync_rst (arst),
	.we (awvalid && awready),		.we (awvalid && awready),
	.re (start_write_burst_w),		.re (start_write_burst_w),
	.data_in ({awid[11:0], awburst[1:0],awsize[1:0],awlen[3:0],awaddr[ADDRESS_BITS+1:2]}),		.data_in ({awid[11:0], awburst[1:0],awsize[1:0],awlen[3:0],awaddr[ADDRESS_BITS+1:2]}),
	@@ -219,9 +200,9 @@ fifo_same_clock #( .DATA_WIDTH(20+ADDRESS_BITS),.DATA_DEPTH(4))
	);		);
	fifo_same_clock #( .DATA_WIDTH(49),.DATA_DEPTH(4))		fifo_same_clock #( .DATA_WIDTH(49),.DATA_DEPTH(4))
	wdata_i (		wdata_i (
	.rst(rst),		.rst(1'b0), //rst),
	.clk(aclk),		.clk(aclk),
	.sync_rst (1'b0),		.sync_rst (arst),
	.we(wvalid && wready),		.we(wvalid && wready),
	.re(bram_we_w), //start_write_burst_w), // wrong		.re(bram_we_w), //start_write_burst_w), // wrong
	.data_in({wid[11:0],wlast,wstb[3:0],wdata[31:0]}),		.data_in({wid[11:0],wlast,wstb[3:0],wdata[31:0]}),
	@@ -241,16 +222,16 @@ fifo_same_clock #( .DATA_WIDTH(49),.DATA_DEPTH(4))
	reg was_bresp_re=0;		reg was_bresp_re=0;
	wire bresp_re;		wire bresp_re;
	assign bresp_re=bready && bvalid && !was_bresp_re;		assign bresp_re=bready && bvalid && !was_bresp_re;
	always @ (posedge rst or posedge aclk) begin		always @ (posedge aclk) begin
	if (rst) was_bresp_re<=0;		if (arst) was_bresp_re<=0;
	else was_bresp_re <= bresp_re;		else was_bresp_re <= bresp_re;
	end		end

	fifo_same_clock #( .DATA_WIDTH(14),.DATA_DEPTH(4))		fifo_same_clock #( .DATA_WIDTH(14),.DATA_DEPTH(4))
	wresp_i (		wresp_i (
	.rst(rst),		.rst(1'b0), //rst),
	.clk(aclk),		.clk(aclk),
	.sync_rst (1'b0),		.sync_rst (arst),
	.we(bram_we_w &&((write_left[3:0]==4'b0) \|\| wlast_out)), // added ((write_left[3:0]==4'b0) \|\| wlast_out) - only last wrtite -> bresp		.we(bram_we_w &&((write_left[3:0]==4'b0) \|\| wlast_out)), // added ((write_left[3:0]==4'b0) \|\| wlast_out) - only last wrtite -> bresp
	// .re(bready && bvalid),		// .re(bready && bvalid),
	.re(bresp_re), // not allowing RE next cycle after bvalid		.re(bresp_re), // not allowing RE next cycle after bvalid

axi/cmprs_afi_mux.v

+8 −3

Original line number	Original line	Diff line number	Diff line
	@@ -34,9 +34,11 @@ module cmprs_afi_mux#(
	parameter CMPRS_AFIMUX_CYCBITS = 3,		parameter CMPRS_AFIMUX_CYCBITS = 3,
	parameter AFI_MUX_BUF_LATENCY = 2 // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used		parameter AFI_MUX_BUF_LATENCY = 2 // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
	)(		)(
	input rst,		// input rst,
	input mclk, // for command/status		input mclk, // for command/status
	input hclk, // global clock to run axi_hp @ 150MHz, shared by all compressor channels		input hclk, // global clock to run axi_hp @ 150MHz, shared by all compressor channels
			input mrst, // @posedge mclk, sync reset
			input hrst, // @posedge xclk, sync reset
	// programming interface		// programming interface
	input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3		input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
	input cmd_stb, // strobe (with first byte) for the command a/d		input cmd_stb, // strobe (with first byte) for the command a/d
	@@ -386,8 +388,9 @@ module cmprs_afi_mux#(
	.ADDR_WIDTH (4),		.ADDR_WIDTH (4),
	.DATA_WIDTH (32)		.DATA_WIDTH (32)
	) cmd_deser_32bit_i (		) cmd_deser_32bit_i (
	.rst (rst), // input		.rst (1'b0), // rst), // input
	.clk (mclk), // input		.clk (mclk), // input
			.srst (mrst), // input
	.ad (cmd_ad), // input[7:0]		.ad (cmd_ad), // input[7:0]
	.stb (cmd_stb), // input		.stb (cmd_stb), // input
	.addr (cmd_a), // output[3:0]		.addr (cmd_a), // output[3:0]
	@@ -436,9 +439,11 @@ module cmprs_afi_mux#(
	.CMPRS_AFIMUX_WIDTH(CMPRS_AFIMUX_WIDTH),		.CMPRS_AFIMUX_WIDTH(CMPRS_AFIMUX_WIDTH),
	.CMPRS_AFIMUX_CYCBITS(CMPRS_AFIMUX_CYCBITS)		.CMPRS_AFIMUX_CYCBITS(CMPRS_AFIMUX_CYCBITS)
	) cmprs_afi_mux_status_i (		) cmprs_afi_mux_status_i (
	.rst (rst), // input		// .rst (rst), // input
	.hclk (hclk), // input		.hclk (hclk), // input
	.mclk (mclk), // input		.mclk (mclk), // input
			.mrst (mrst), // input
			.hrst (hrst), // input
	.cmd_data (cmd_data[15:0]), // input[15:0]		.cmd_data (cmd_data[15:0]), // input[15:0]
	.cmd_a (cmd_a[1:0]), // input[1:0]		.cmd_a (cmd_a[1:0]), // input[1:0]
	.status_we (cmd_we_status_w), // input		.status_we (cmd_we_status_w), // input

axi/cmprs_afi_mux_status.v

+15 −8

Original line number	Original line	Diff line number	Diff line
	@@ -29,9 +29,11 @@ module cmprs_afi_mux_status #(
	parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26)		parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26)
	parameter CMPRS_AFIMUX_CYCBITS = 3		parameter CMPRS_AFIMUX_CYCBITS = 3
	) (		) (
	input rst,		// input rst,
	input hclk, // global clock to run axi_hp @ 150MHz, shared by all compressor channels		input hclk, // global clock to run axi_hp @ 150MHz, shared by all compressor channels
	input mclk, // for command/status		input mclk, // for command/status
			input mrst, // @posedge mclk, sync reset
			input hrst, // @posedge xclk, sync reset
	// mclk domain		// mclk domain
	input [15:0] cmd_data, //		input [15:0] cmd_data, //
	input [ 1:0] cmd_a, //		input [ 1:0] cmd_a, //
	@@ -100,11 +102,12 @@ module cmprs_afi_mux_status #(

	end		end

	pulse_cross_clock mode_we_hclk_i (.rst(rst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(mode_we), .out_pulse(mode_we_hclk),.busy());		pulse_cross_clock mode_we_hclk_i (.rst(mrst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(mode_we), .out_pulse(mode_we_hclk),.busy());
	pulse_cross_clock stb_mclk_i (.rst(rst), .src_clk(hclk), .dst_clk(mclk), .in_pulse(stb_r), .out_pulse(stb_mclk), .busy());		pulse_cross_clock stb_mclk_i (.rst(hrst), .src_clk(hclk), .dst_clk(mclk), .in_pulse(stb_r), .out_pulse(stb_mclk), .busy());
	status_router4 status_router4_i (		status_router4 status_router4_i (
	.rst (rst), // input		.rst (1'b0), // rst), // input
	.clk (mclk), // input		.clk (mclk), // input
			.srst (mrst), // input
	.db_in0 (ad[0 * 8 +: 8]), // input[7:0]		.db_in0 (ad[0 * 8 +: 8]), // input[7:0]
	.rq_in0 (rq[0]), // input		.rq_in0 (rq[0]), // input
	.start_in0 (start[0]), // output		.start_in0 (start[0]), // output
	@@ -127,8 +130,9 @@ module cmprs_afi_mux_status #(
	.STATUS_REG_ADDR (CMPRS_AFIMUX_STATUS_REG_ADDR+0),		.STATUS_REG_ADDR (CMPRS_AFIMUX_STATUS_REG_ADDR+0),
	.PAYLOAD_BITS (CMPRS_AFIMUX_WIDTH)		.PAYLOAD_BITS (CMPRS_AFIMUX_WIDTH)
	) status_generate0_i (		) status_generate0_i (
	.rst (rst), // input		.rst (1'b0), //rst), // input
	.clk (mclk), // input		.clk (mclk), // input
			.srst (mrst), // input
	.we (status_we && (cmd_a==0)), // input		.we (status_we && (cmd_a==0)), // input
	.wd (cmd_data[7:0]), // input[7:0]		.wd (cmd_data[7:0]), // input[7:0]
	.status (status_data[0 * CMPRS_AFIMUX_WIDTH +: CMPRS_AFIMUX_WIDTH]), // input[25:0]		.status (status_data[0 * CMPRS_AFIMUX_WIDTH +: CMPRS_AFIMUX_WIDTH]), // input[25:0]
	@@ -141,8 +145,9 @@ module cmprs_afi_mux_status #(
	.STATUS_REG_ADDR (CMPRS_AFIMUX_STATUS_REG_ADDR+0),		.STATUS_REG_ADDR (CMPRS_AFIMUX_STATUS_REG_ADDR+0),
	.PAYLOAD_BITS (CMPRS_AFIMUX_WIDTH)		.PAYLOAD_BITS (CMPRS_AFIMUX_WIDTH)
	) status_generate1_i (		) status_generate1_i (
	.rst (rst), // input		.rst (1'b0), //rst), // input
	.clk (mclk), // input		.clk (mclk), // input
			.srst (mrst), // input
	.we (status_we && (cmd_a==1)), // input		.we (status_we && (cmd_a==1)), // input
	.wd (cmd_data[7:0]), // input[7:0]		.wd (cmd_data[7:0]), // input[7:0]
	.status (status_data[1 * CMPRS_AFIMUX_WIDTH +: CMPRS_AFIMUX_WIDTH]), // input[25:0]		.status (status_data[1 * CMPRS_AFIMUX_WIDTH +: CMPRS_AFIMUX_WIDTH]), // input[25:0]
	@@ -155,8 +160,9 @@ module cmprs_afi_mux_status #(
	.STATUS_REG_ADDR (CMPRS_AFIMUX_STATUS_REG_ADDR+0),		.STATUS_REG_ADDR (CMPRS_AFIMUX_STATUS_REG_ADDR+0),
	.PAYLOAD_BITS (CMPRS_AFIMUX_WIDTH)		.PAYLOAD_BITS (CMPRS_AFIMUX_WIDTH)
	) status_generate2_i (		) status_generate2_i (
	.rst (rst), // input		.rst (1'b0), //rst), // input
	.clk (mclk), // input		.clk (mclk), // input
			.srst (mrst), // input
	.we (status_we && (cmd_a==2)), // input		.we (status_we && (cmd_a==2)), // input
	.wd (cmd_data[7:0]), // input[7:0]		.wd (cmd_data[7:0]), // input[7:0]
	.status (status_data[2 * CMPRS_AFIMUX_WIDTH +: CMPRS_AFIMUX_WIDTH]), // input[25:0]		.status (status_data[2 * CMPRS_AFIMUX_WIDTH +: CMPRS_AFIMUX_WIDTH]), // input[25:0]
	@@ -169,8 +175,9 @@ module cmprs_afi_mux_status #(
	.STATUS_REG_ADDR (CMPRS_AFIMUX_STATUS_REG_ADDR+0),		.STATUS_REG_ADDR (CMPRS_AFIMUX_STATUS_REG_ADDR+0),
	.PAYLOAD_BITS (CMPRS_AFIMUX_WIDTH)		.PAYLOAD_BITS (CMPRS_AFIMUX_WIDTH)
	) status_generate3_i (		) status_generate3_i (
	.rst (rst), // input		.rst (1'b0), // rst), // input
	.clk (mclk), // input		.clk (mclk), // input
			.srst (mrst), // input
	.we (status_we && (cmd_a==3)), // input		.we (status_we && (cmd_a==3)), // input
	.wd (cmd_data[7:0]), // input[7:0]		.wd (cmd_data[7:0]), // input[7:0]
	.status (status_data[3 * CMPRS_AFIMUX_WIDTH +: CMPRS_AFIMUX_WIDTH]), // input[25:0]		.status (status_data[3 * CMPRS_AFIMUX_WIDTH +: CMPRS_AFIMUX_WIDTH]), // input[25:0]

axi/histogram_saxi.v

+33 −28

Original line number	Original line	Diff line number	Diff line
	@@ -37,9 +37,12 @@ module histogram_saxi#(
	// parameter HIST_SAXI_STATUS_REG = 'h34,		// parameter HIST_SAXI_STATUS_REG = 'h34,
	parameter NUM_FRAME_BITS = 4 // number of bits use for frame number		parameter NUM_FRAME_BITS = 4 // number of bits use for frame number
	)(		)(
	input rst,		// input rst,
	input mclk, // for command/status		input mclk, // for command/status
	input aclk, // global clock to run s_axi (@150MHz?)		input aclk, // global clock to run s_axi (@150MHz?)
			input mrst, // @posedge mclk, sync reset
			input arst, // @posedge aclk, sync reset

	// sensor 0, data valid @posedge mclk		// sensor 0, data valid @posedge mclk
	input [NUM_FRAME_BITS-1:0] frame0, // frame number for which the histogram is provided		input [NUM_FRAME_BITS-1:0] frame0, // frame number for which the histogram is provided
	input hist_request0, // request to transfer a burst		input hist_request0, // request to transfer a burst
	@@ -248,8 +251,8 @@ module histogram_saxi#(
	assign page_sent_aclk = block_run[1] && !block_run[0];		assign page_sent_aclk = block_run[1] && !block_run[0];

	// command interface		// command interface
	always @(posedge rst or posedge mclk) begin		always @(posedge mclk) begin
	if (rst) mode <= 0;		if (mrst) mode <= 0;
	else if (we_mode) mode <= cmd_data[HIST_SAXI_MODE_WIDTH-1:0];		else if (we_mode) mode <= cmd_data[HIST_SAXI_MODE_WIDTH-1:0];
	end		end
	always @(posedge mclk) begin		always @(posedge mclk) begin
	@@ -357,7 +360,7 @@ module histogram_saxi#(


	pulse_cross_clock pulse_cross_clock_page_sent_i (		pulse_cross_clock pulse_cross_clock_page_sent_i (
	.rst (rst), // input		.rst (arst), // input
	.src_clk (aclk), // input		.src_clk (aclk), // input
	.dst_clk (mclk), // input		.dst_clk (mclk), // input
	.in_pulse (page_sent_aclk), // input		.in_pulse (page_sent_aclk), // input
	@@ -365,7 +368,7 @@ module histogram_saxi#(
	.busy() // output		.busy() // output
	);		);
	pulse_cross_clock pulse_cross_clock_page_written_aclk_i (		pulse_cross_clock pulse_cross_clock_page_written_aclk_i (
	.rst (rst), // input		.rst (mrst), // input
	.src_clk (mclk), // input		.src_clk (mclk), // input
	.dst_clk (aclk), // input		.dst_clk (aclk), // input
	.in_pulse (burst_done_w), // input		.in_pulse (burst_done_w), // input
	@@ -384,8 +387,9 @@ module histogram_saxi#(
	.ADDR2 (0),		.ADDR2 (0),
	.ADDR_MASK2 (0)		.ADDR_MASK2 (0)
	) cmd_deser_sens_i2c_i (		) cmd_deser_sens_i2c_i (
	.rst (rst), // input		.rst (1'b0), // input
	.clk (mclk), // input		.clk (mclk), // input
			.srst (mrst), // input
	.ad (cmd_ad), // input[7:0]		.ad (cmd_ad), // input[7:0]
	.stb (cmd_stb), // input		.stb (cmd_stb), // input
	.addr (cmd_wa), // output[3:0]		.addr (cmd_wa), // output[3:0]
	@@ -415,8 +419,9 @@ module histogram_saxi#(
	.DATA_WIDTH(32),		.DATA_WIDTH(32),
	.DATA_DEPTH(4)		.DATA_DEPTH(4)
	) fifo_same_clock_i (		) fifo_same_clock_i (
	.rst (rst), // input		.rst (1'b0), // input
	.clk (aclk), // input		.clk (aclk), // input
			.sync_rst (arst), // input
	.sync_rst (!en_aclk), // input		.sync_rst (!en_aclk), // input
	.we (buf_re[2]), // input		.we (buf_re[2]), // input
	.re (fifo_re), // input		.re (fifo_re), // input

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