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Commit b721ae66 authored by Andrey Filippov's avatar Andrey Filippov
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axi/axibram_read.v
View file @ b721ae66
......@@ -25,20 +25,16 @@ module axibram_read #(
parameter ADDRESS_BITS = 10 // number of memory address bits
)(
input aclk, // clock - should be buffered
// input aresetn, // reset, active low
input rst, // reset, active high
// input rst, // reset, active high
input arst, // @posedge aclk sync reset, active high
// AXI Read Address
input [31:0] araddr, // ARADDR[31:0], input
input arvalid, // ARVALID, input
output arready, // ARREADY, output
input [11:0] arid, // ARID[11:0], input
// input [ 1:0] arlock, // ARLOCK[1:0], input
// input [ 3:0] archache,// ARCACHE[3:0], input
// input [ 2:0] arprot, // ARPROT[2:0], input
input [ 3:0] arlen, // ARLEN[3:0], input
input [ 1:0] arsize, // ARSIZE[1:0], input
input [ 1:0] arburst, // ARBURST[1:0], input
// input [ 3:0] adqos, // ARQOS[3:0], input
// AXI Read Data
output [31:0] rdata, // RDATA[31:0], output
output reg rvalid, // RVALID, output
......@@ -145,30 +141,30 @@ module axibram_read #(
assign rdata[31:0] = bram_rdata; // data out
always @ (posedge aclk or posedge rst) begin
always @ (posedge aclk) begin
`ifdef USE_SHORT_REN_REGEN
if (rst) bram_regen_r <= 0;
if (arst) bram_regen_r <= 0;
else bram_regen_r <= bram_ren;
`endif
if (rst) pre_last_in_burst_r <= 0;
if (arst) pre_last_in_burst_r <= 0;
// else if (start_read_burst_w) pre_last_in_burst_r <= (read_left==4'b0);
else if (bram_reg_re_w) pre_last_in_burst_r <= (read_left==4'b0);
if (rst) rburst[1:0] <= 0;
if (arst) rburst[1:0] <= 0;
else if (start_read_burst_w) rburst[1:0] <= arburst_out[1:0];
if (rst) rlen[3:0] <= 0;
if (arst) rlen[3:0] <= 0;
else if (start_read_burst_w) rlen[3:0] <= arlen_out[3:0];
if (rst) read_in_progress <= 0;
if (arst) read_in_progress <= 0;
else read_in_progress <= read_in_progress_w;
if (rst) read_in_progress_d <= 0;
if (arst) read_in_progress_d <= 0;
// else read_in_progress_d <= read_in_progress_d_w;
else if (bram_reg_re_w) read_in_progress_d <= read_in_progress_d_w;
if (rst) read_in_progress_or <= 0;
if (arst) read_in_progress_or <= 0;
// else read_in_progress_or <= read_in_progress_d_w || read_in_progress_w;
// else if (bram_reg_re_w) read_in_progress_or <= read_in_progress_d_w || read_in_progress_w;
// FIXME:
......@@ -177,22 +173,23 @@ module axibram_read #(
// reg read_in_progress_d=0; // delayed by one active cycle (not skipped)
// reg read_in_progress_or=0; // read_in_progress || read_in_progress_d
if (rst) read_left <= 0;
if (arst) read_left <= 0;
else if (start_read_burst_w) read_left <= arlen_out[3:0]; // precedence over inc
else if (bram_reg_re_w) read_left <= read_left-1; //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target.
if (rst) read_address <= {ADDRESS_BITS{1'b0}};
if (arst) read_address <= {ADDRESS_BITS{1'b0}};
else if (start_read_burst_w) read_address <= araddr_out[ADDRESS_BITS-1:0]; // precedence over inc
else if (bram_reg_re_w) read_address <= next_rd_address_w;
if (rst) rvalid <= 1'b0;
if (arst) rvalid <= 1'b0;
else if (bram_reg_re_w && read_in_progress_d) rvalid <= 1'b1;
else if (rready) rvalid <= 1'b0;
if (rst) rlast <= 1'b0;
if (arst) rlast <= 1'b0;
else if (last_in_burst_d_w) rlast <= 1'b1;
else if (rready) rlast <= 1'b0;
end
always @ (posedge aclk) begin //SuppressThisWarning ISExst Assignment to bram_reg_re_0 ignored, since the identifier is never used
// bram_reg_re_0 <= read_in_progress_w && !pre_rvalid_w;
......@@ -240,9 +237,9 @@ module axibram_read #(
fifo_same_clock #( .DATA_WIDTH(ADDRESS_BITS+20),.DATA_DEPTH(4))
raddr_i (
.rst(rst),
.rst(1'b0),
.clk(aclk),
.sync_rst(1'b0), // input
.sync_rst(arst),
.we(arvalid && arready),
.re(start_read_burst_w),
.data_in({arid[11:0], arburst[1:0],arsize[1:0],arlen[3:0],araddr[ADDRESS_BITS+1:2]}),
......
axi/axibram_write.v
View file @ b721ae66
......@@ -26,21 +26,16 @@ module axibram_write #(
parameter ADDRESS_BITS = 10 // number of memory address bits
)(
input aclk, // clock - should be buffered
// input aresetn, // reset, active low
input rst, // reset, active highw
input arst, // @aclk sync reset, active high
// AXI Write Address
input [31:0] awaddr, // AWADDR[31:0], input
input awvalid, // AWVALID, input
output awready, // AWREADY, output
input [11:0] awid, // AWID[11:0], input
// input [ 1:0] awlock, // AWLOCK[1:0], input
// input [ 3:0] awcache, // AWCACHE[3:0], input
// input [ 2:0] awprot, // AWPROT[2:0], input
input [ 3:0] awlen, // AWLEN[3:0], input
input [ 1:0] awsize, // AWSIZE[1:0], input
input [ 1:0] awburst, // AWBURST[1:0], input
// input [ 3:0] awqos, // AWQOS[3:0], input
// AXI PS Master GP0: Write Data
input [31:0] wdata, // WDATA[31:0], input
input wvalid, // WVALID, input
......@@ -141,44 +136,30 @@ module axibram_write #(
assign start_write_burst_w=w_nempty_ready && aw_nempty_ready && (!write_in_progress || (w_nempty_ready && ((write_left[3:0]==4'b0) || wlast_out)));
assign write_in_progress_w=w_nempty_ready && aw_nempty_ready || (write_in_progress && !(w_nempty_ready && ((write_left[3:0]==4'b0) || wlast_out)));
always @ (posedge aclk or posedge rst) begin
if (rst) wburst[1:0] <= 0;
always @ (posedge aclk) begin
if (arst) wburst[1:0] <= 0;
else if (start_write_burst_w) wburst[1:0] <= awburst_out[1:0];
if (rst) wlen[3:0] <= 0;
if (arst) wlen[3:0] <= 0;
else if (start_write_burst_w) wlen[3:0] <= awlen_out[3:0];
if (rst) write_in_progress <= 0;
else write_in_progress <= write_in_progress_w;
if (arst) write_in_progress <= 0;
else write_in_progress <= write_in_progress_w;
if (rst) write_left <= 0;
if (arst) write_left <= 0;
else if (start_write_burst_w) write_left <= awlen_out[3:0]; // precedence over inc
else if (bram_we_w) write_left <= write_left-1; //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target.
if (rst) write_address <= {ADDRESS_BITS{1'b0}};
if (arst) write_address <= {ADDRESS_BITS{1'b0}};
else if (start_write_burst_w) write_address <= awaddr_out[ADDRESS_BITS-1:0]; // precedence over inc
else if (bram_we_w) write_address <= next_wr_address_w;
if (rst) dev_ready_r <= 1'b0;
else dev_ready_r <= dev_ready;
if (arst) dev_ready_r <= 1'b0;
else dev_ready_r <= dev_ready;
end
// **** Write response channel ****
wire [ 1:0] bresp_in;
assign bresp_in=2'b0;
/*
output bvalid, // BVALID, output
input bready, // BREADY, input
output [11:0] bid, // BID[11:0], output
output [ 1:0] bresp // BRESP[1:0], output
*/
/*
reg bram_reg_re_r;
always @ (posedge aclk) begin
bram_reg_re_r <= bram_reg_re_w;
end
*/
// external memory interface (write only)
assign pre_awaddr=awaddr_out[ADDRESS_BITS-1:0];
......@@ -199,9 +180,9 @@ module axibram_write #(
`endif
fifo_same_clock #( .DATA_WIDTH(20+ADDRESS_BITS),.DATA_DEPTH(4))
waddr_i (
.rst (rst),
.rst (1'b0), //rst),
.clk (aclk),
.sync_rst (1'b0),
.sync_rst (arst),
.we (awvalid && awready),
.re (start_write_burst_w),
.data_in ({awid[11:0], awburst[1:0],awsize[1:0],awlen[3:0],awaddr[ADDRESS_BITS+1:2]}),
......@@ -219,9 +200,9 @@ fifo_same_clock #( .DATA_WIDTH(20+ADDRESS_BITS),.DATA_DEPTH(4))
);
fifo_same_clock #( .DATA_WIDTH(49),.DATA_DEPTH(4))
wdata_i (
.rst(rst),
.rst(1'b0), //rst),
.clk(aclk),
.sync_rst (1'b0),
.sync_rst (arst),
.we(wvalid && wready),
.re(bram_we_w), //start_write_burst_w), // wrong
.data_in({wid[11:0],wlast,wstb[3:0],wdata[31:0]}),
......@@ -241,16 +222,16 @@ fifo_same_clock #( .DATA_WIDTH(49),.DATA_DEPTH(4))
reg was_bresp_re=0;
wire bresp_re;
assign bresp_re=bready && bvalid && !was_bresp_re;
always @ (posedge rst or posedge aclk) begin
if (rst) was_bresp_re<=0;
else was_bresp_re <= bresp_re;
always @ (posedge aclk) begin
if (arst) was_bresp_re<=0;
else was_bresp_re <= bresp_re;
end
fifo_same_clock #( .DATA_WIDTH(14),.DATA_DEPTH(4))
wresp_i (
.rst(rst),
.rst(1'b0), //rst),
.clk(aclk),
.sync_rst (1'b0),
.sync_rst (arst),
.we(bram_we_w &&((write_left[3:0]==4'b0) || wlast_out)), // added ((write_left[3:0]==4'b0) || wlast_out) - only last wrtite -> bresp
// .re(bready && bvalid),
.re(bresp_re), // not allowing RE next cycle after bvalid
......
axi/cmprs_afi_mux.v
View file @ b721ae66
......@@ -34,9 +34,11 @@ module cmprs_afi_mux#(
parameter CMPRS_AFIMUX_CYCBITS = 3,
parameter AFI_MUX_BUF_LATENCY = 2 // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
)(
input rst,
// input rst,
input mclk, // for command/status
input hclk, // global clock to run axi_hp @ 150MHz, shared by all compressor channels
input mrst, // @posedge mclk, sync reset
input hrst, // @posedge xclk, sync reset
// programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
......@@ -386,8 +388,9 @@ module cmprs_afi_mux#(
.ADDR_WIDTH (4),
.DATA_WIDTH (32)
) cmd_deser_32bit_i (
.rst (rst), // input
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[3:0]
......@@ -436,9 +439,11 @@ module cmprs_afi_mux#(
.CMPRS_AFIMUX_WIDTH(CMPRS_AFIMUX_WIDTH),
.CMPRS_AFIMUX_CYCBITS(CMPRS_AFIMUX_CYCBITS)
) cmprs_afi_mux_status_i (
.rst (rst), // input
// .rst (rst), // input
.hclk (hclk), // input
.mclk (mclk), // input
.mrst (mrst), // input
.hrst (hrst), // input
.cmd_data (cmd_data[15:0]), // input[15:0]
.cmd_a (cmd_a[1:0]), // input[1:0]
.status_we (cmd_we_status_w), // input
......
axi/cmprs_afi_mux_status.v
View file @ b721ae66
......@@ -29,9 +29,11 @@ module cmprs_afi_mux_status #(
parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26)
parameter CMPRS_AFIMUX_CYCBITS = 3
) (
input rst,
// input rst,
input hclk, // global clock to run axi_hp @ 150MHz, shared by all compressor channels
input mclk, // for command/status
input mrst, // @posedge mclk, sync reset
input hrst, // @posedge xclk, sync reset
// mclk domain
input [15:0] cmd_data, //
input [ 1:0] cmd_a, //
......@@ -100,11 +102,12 @@ module cmprs_afi_mux_status #(
end
pulse_cross_clock mode_we_hclk_i (.rst(rst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(mode_we), .out_pulse(mode_we_hclk),.busy());
pulse_cross_clock stb_mclk_i (.rst(rst), .src_clk(hclk), .dst_clk(mclk), .in_pulse(stb_r), .out_pulse(stb_mclk), .busy());
pulse_cross_clock mode_we_hclk_i (.rst(mrst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(mode_we), .out_pulse(mode_we_hclk),.busy());
pulse_cross_clock stb_mclk_i (.rst(hrst), .src_clk(hclk), .dst_clk(mclk), .in_pulse(stb_r), .out_pulse(stb_mclk), .busy());
status_router4 status_router4_i (
.rst (rst), // input
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.db_in0 (ad[0 * 8 +: 8]), // input[7:0]
.rq_in0 (rq[0]), // input
.start_in0 (start[0]), // output
......@@ -127,8 +130,9 @@ module cmprs_afi_mux_status #(
.STATUS_REG_ADDR (CMPRS_AFIMUX_STATUS_REG_ADDR+0),
.PAYLOAD_BITS (CMPRS_AFIMUX_WIDTH)
) status_generate0_i (
.rst (rst), // input
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (status_we && (cmd_a==0)), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_data[0 * CMPRS_AFIMUX_WIDTH +: CMPRS_AFIMUX_WIDTH]), // input[25:0]
......@@ -141,8 +145,9 @@ module cmprs_afi_mux_status #(
.STATUS_REG_ADDR (CMPRS_AFIMUX_STATUS_REG_ADDR+0),
.PAYLOAD_BITS (CMPRS_AFIMUX_WIDTH)
) status_generate1_i (
.rst (rst), // input
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (status_we && (cmd_a==1)), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_data[1 * CMPRS_AFIMUX_WIDTH +: CMPRS_AFIMUX_WIDTH]), // input[25:0]
......@@ -155,8 +160,9 @@ module cmprs_afi_mux_status #(
.STATUS_REG_ADDR (CMPRS_AFIMUX_STATUS_REG_ADDR+0),
.PAYLOAD_BITS (CMPRS_AFIMUX_WIDTH)
) status_generate2_i (
.rst (rst), // input
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (status_we && (cmd_a==2)), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_data[2 * CMPRS_AFIMUX_WIDTH +: CMPRS_AFIMUX_WIDTH]), // input[25:0]
......@@ -169,8 +175,9 @@ module cmprs_afi_mux_status #(
.STATUS_REG_ADDR (CMPRS_AFIMUX_STATUS_REG_ADDR+0),
.PAYLOAD_BITS (CMPRS_AFIMUX_WIDTH)
) status_generate3_i (
.rst (rst), // input
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (status_we && (cmd_a==3)), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_data[3 * CMPRS_AFIMUX_WIDTH +: CMPRS_AFIMUX_WIDTH]), // input[25:0]
......
axi/histogram_saxi.v
View file @ b721ae66
......@@ -37,9 +37,12 @@ module histogram_saxi#(
// parameter HIST_SAXI_STATUS_REG = 'h34,
parameter NUM_FRAME_BITS = 4 // number of bits use for frame number
)(
input rst,
// input rst,
input mclk, // for command/status
input aclk, // global clock to run s_axi (@150MHz?)
input mrst, // @posedge mclk, sync reset
input arst, // @posedge aclk, sync reset
// sensor 0, data valid @posedge mclk
input [NUM_FRAME_BITS-1:0] frame0, // frame number for which the histogram is provided
input hist_request0, // request to transfer a burst
......@@ -248,8 +251,8 @@ module histogram_saxi#(
assign page_sent_aclk = block_run[1] && !block_run[0];
// command interface
always @(posedge rst or posedge mclk) begin
if (rst) mode <= 0;
always @(posedge mclk) begin
if (mrst) mode <= 0;
else if (we_mode) mode <= cmd_data[HIST_SAXI_MODE_WIDTH-1:0];
end
always @(posedge mclk) begin
......@@ -357,7 +360,7 @@ module histogram_saxi#(
pulse_cross_clock pulse_cross_clock_page_sent_i (
.rst (rst), // input
.rst (arst), // input
.src_clk (aclk), // input
.dst_clk (mclk), // input
.in_pulse (page_sent_aclk), // input
......@@ -365,7 +368,7 @@ module histogram_saxi#(
.busy() // output
);
pulse_cross_clock pulse_cross_clock_page_written_aclk_i (
.rst (rst), // input
.rst (mrst), // input
.src_clk (mclk), // input
.dst_clk (aclk), // input
.in_pulse (burst_done_w), // input
......@@ -384,12 +387,13 @@ module histogram_saxi#(
.ADDR2 (0),
.ADDR_MASK2 (0)
) cmd_deser_sens_i2c_i (
.rst (rst), // input
.clk (mclk), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_wa), // output[3:0]
.data (cmd_data), // output[31:0]
.rst (1'b0), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_wa), // output[3:0]
.data (cmd_data), // output[31:0]
.we ({we_mode,we_addr}) // output
);
......@@ -399,31 +403,32 @@ module histogram_saxi#(
.LOG2WIDTH_RD(5),
.DUMMY(0)
) ram_var_w_var_r_i (
.rclk (aclk), // input
.raddr ({page_rd[1:0],page_ra[7:0]}), // input[9:0]
.ren (buf_re[0]), // input
.regen (buf_re[1]), // input
.data_out (inter_buf_data), // output[31:0]
.wclk (mclk), // input
.rclk (aclk), // input
.raddr ({page_rd[1:0],page_ra[7:0]}), // input[9:0]
.ren (buf_re[0]), // input
.regen (buf_re[1]), // input
.data_out (inter_buf_data), // output[31:0]
.wclk (mclk), // input
.waddr ({page_wr[1:0], page_wa[7:0]}), // input[9:0]
.we (dav_r), // input
.web (8'hff), // input[7:0]
.data_in (din_r) // input[31:0]
.we (dav_r), // input
.web (8'hff), // input[7:0]
.data_in (din_r) // input[31:0]
);
// Small extra FIFO to tolerate ram_var_w_var_r latency
fifo_same_clock #(
.DATA_WIDTH(32),
.DATA_DEPTH(4)
) fifo_same_clock_i (
.rst (rst), // input
.clk (aclk), // input
.sync_rst (!en_aclk), // input
.we (buf_re[2]), // input
.re (fifo_re), // input
.rst (1'b0), // input
.clk (aclk), // input
.sync_rst (arst), // input
.sync_rst (!en_aclk), // input
.we (buf_re[2]), // input
.re (fifo_re), // input
.data_in (inter_buf_data), // input[31:0]
.data_out (saxi_wdata), // output[31:0]
.nempty (fifo_nempty), // output
.half_full (fifo_half_full) // output reg
.data_out (saxi_wdata), // output[31:0]
.nempty (fifo_nempty), // output
.half_full (fifo_half_full) // output reg
);
endmodule
axi/membridge.v
View file @ b721ae66
This diff is collapsed.
axi/mult_saxi_wr.v
View file @ b721ae66
......@@ -39,9 +39,11 @@ module mult_saxi_wr #(
parameter MULT_SAXI_ADV_RD = 3 // number of clock cycles before end of write to genearte adv_wr_done
) (
input rst, // global reset
// input rst, // global reset
input mclk, // system clock
input aclk, // global clock to run s_axi (@150MHz?)
input mrst, // @mclk sync reset
input arst, // @aclk sync reset
// command interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
......@@ -161,8 +163,8 @@ module mult_saxi_wr #(
assign en_chn_mclk = mode_reg[3:0];
assign run_chn_mclk = mode_reg[7:4];
always @ (posedge rst or posedge mclk) begin
if (rst) mode_reg <= 0;
always @ (posedge mclk) begin
if (mrst) mode_reg <= 0;
else if (we_ctrl && !cmd_a[0]) mode_reg <= cmd_data[7:0];
end
......@@ -420,15 +422,15 @@ module mult_saxi_wr #(
.DATA_WIDTH(35),
.DATA_DEPTH(4)
) fifo_same_clock_i (
.rst (rst), // input
.clk (aclk), // input
.sync_rst (!en_aclk), // input
.we (buf_re[2]), // input
.re (fifo_re), // input
.rst (1'b0), // rst), // input
.clk (aclk), // input
.sync_rst (!en_aclk || arst), // input
.we (buf_re[2]), // input
.re (fifo_re), // input
.data_in ({chn_rd_data,is_last_rd[1],inter_buf_data}), // input[31:0]
.data_out ({chn_fifo_out,saxi_wlast, saxi_wdata}), // output[31:0]
.nempty (fifo_nempty), // output
.half_full (fifo_half_full) // output reg
.nempty (fifo_nempty), // output
.half_full (fifo_half_full) // output reg
);
generate
......@@ -481,8 +483,9 @@ module mult_saxi_wr #(
.ADDR2 (0),
.ADDR_MASK2 (0)
) cmd_deser_sens_i2c_i (
.rst (rst), // input
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[3:0]
......@@ -509,7 +512,7 @@ module mult_saxi_wr #(
if (pntr_we_mclk && (pntr_wa == 2'h3)) status_pntr3 <= pntr_wd;
end
pulse_cross_clock status_wr_i (.rst(rst), .src_clk(aclk), .dst_clk(mclk), .in_pulse(pntr_we), .out_pulse(pntr_we_mclk),.busy());
pulse_cross_clock status_wr_i (.rst(arst), .src_clk(aclk), .dst_clk(mclk), .in_pulse(pntr_we), .out_pulse(pntr_we_mclk),.busy());
status_generate #(
.STATUS_REG_ADDR (MULT_SAXI_STATUS_REG+4), // not used
......@@ -518,8 +521,9 @@ module mult_saxi_wr #(
.EXTRA_WORDS (4),
.EXTRA_REG_ADDR (MULT_SAXI_STATUS_REG)
) status_generate_i (
.rst (rst), // input
.clk (mclk), // input
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (we_ctrl && cmd_a[0]), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_data), // input[128:0]
......
cmd_mux.v
View file @ b721ae66
......@@ -61,7 +61,8 @@ module cmd_mux #(
) (
input axi_clk,
input mclk,
input rst,
input mrst, // @posedge mclk - sync reset
input arst, // @posedge axi_clk - sync reset
// direct commands from AXI. No wait but for multi-cycle output and command sequencer (having higher priority)
input [AXI_WR_ADDR_BITS-1:0] pre_waddr, // AXI write address, before actual writes (to generate busy), valid@start_burst
input start_wburst, // burst start - should generate ~ready (should be AND-ed with !busy internally)
......@@ -114,10 +115,10 @@ module cmd_mux #(
assign seq_length_rom_a=par_ad[NUM_CYCLES_LOW_BIT+:5];
assign ss= seq_length[3];
always @ (posedge axi_clk or posedge rst) begin
if (rst) selected <= 1'b0;
always @ (posedge axi_clk) begin
if (arst) selected <= 1'b0;
else if (start_wburst) selected <= selected_w;
if (rst) busy_r <= 1'b0;
if (arst) busy_r <= 1'b0;
else busy_r <= !fifo_half_empty;
end
......@@ -158,8 +159,8 @@ module cmd_mux #(
5'h1e:seq_length <= NUM_CYCLES_30;
5'h1f:seq_length <= NUM_CYCLES_31;
endcase
always @ (posedge rst or posedge mclk) begin
if (rst) seq_busy_r<=0;
always @ (posedge mclk) begin
if (mrst) seq_busy_r<=0;
else begin
if (ad_stb) begin
case (seq_length)
......@@ -177,9 +178,9 @@ module cmd_mux #(
assign can_start_w= ad_stb_r? ss: !seq_busy_r[1];
assign start_axi_w= can_start_w && ~cmdseq_full_r && fifo_nempty;
assign start_w= can_start_w && (cmdseq_full_r || fifo_nempty);
always @ (posedge rst or posedge mclk) begin
if (rst) ad_stb_r <= 0;
else ad_stb_r <= start_w;
always @ (posedge mclk) begin
if (mrst) ad_stb_r <= 0;
else ad_stb_r <= start_w;
end
always @ (posedge mclk) begin
if (start_w) par_ad <={cmdseq_full_r?cseq_wdata_r:wdata_fifo_out,{(16-AXI_WR_ADDR_BITS){1'b0}},cmdseq_full_r?cseq_waddr_r:waddr_fifo_out};
......@@ -188,8 +189,8 @@ module cmd_mux #(
assign cseq_ackn= cseq_wr_en && (!cmdseq_full_r || can_start_w); // cmddseq_full has priority over axi, so (can_start_w && cmdseq_full_r)
always @ (posedge rst or posedge mclk) begin
if (rst) cmdseq_full_r <= 0;
always @ (posedge mclk) begin
if (mrst) cmdseq_full_r <= 0;
else cmdseq_full_r <= cseq_ackn || (cmdseq_full_r && !can_start_w);
end
always @ (posedge mclk) begin
......@@ -204,7 +205,9 @@ module cmd_mux #(
.DATA_WIDTH (AXI_WR_ADDR_BITS+32),
.DATA_DEPTH (4)
) fifo_cross_clocks_i (
.rst (rst), // input
.rst (1'b0), // input
.rrst (mrst), // input
.wrst (arst), // input
.rclk (mclk), // input
.wclk (axi_clk), // input
.we (wr_en && selected), // input
......
cmd_readback.v
View file @ b721ae66
......@@ -30,7 +30,8 @@ module cmd_readback#(
parameter CONTROL_RBACK_ADDR = 'h0000, // AXI write address of control write registers
parameter CONTROL_RBACK_ADDR_MASK = 'h3800 // AXI write address of control registers
)(
input rst,
input mrst, // @posedge mclk - sync reset
input arst, // @posedge axi_clk - sync reset
input mclk,
input axi_clk,
input [AXI_WR_ADDR_BITS-1:0] par_waddr, // parallel address
......@@ -71,11 +72,11 @@ module cmd_readback#(
assign axird_selected = select_r;
always @ (posedge rst or posedge axi_clk) begin
if (rst) axird_regen <= 0;
else axird_regen <= axird_ren;
always @ (posedge axi_clk) begin
if (arst) axird_regen <= 0;
else axird_regen <= axird_ren;
if (rst) select_r <= 0;
if (arst) select_r <= 0;
else if (axird_start_burst) select_r <= select_w;
end
......@@ -85,9 +86,9 @@ module cmd_readback#(
select_d <= select_r;
end
always @ (posedge rst or posedge mclk) begin
if (rst) we <= 0;
else we <= we_w;
always @ (posedge mclk) begin
if (mrst) we <= 0;
else we <= we_w;
end
always @ (posedge mclk) begin
if (we_w) wdata <= par_data;
......
compressor_jp/cmprs_cmd_decode.v
View file @ b721ae66
......@@ -132,16 +132,16 @@ module cmprs_cmd_decode#(
parameter CMPRS_CSAT_CB_BITS = 10, // number of bits in blue scale field in color saturation word
parameter CMPRS_CSAT_CR = 12, // bit # of number of red scale field in color saturation word
parameter CMPRS_CSAT_CR_BITS = 10, // number of bits in red scale field in color saturation word
parameter CMPRS_CORING_BITS = 3, // number of bits in coring mode
parameter CMPRS_CORING_BITS = 3 // number of bits in coring mode
parameter CMPRS_STUFFER_NEG = 1 // stuffer runs @ negedge xclk2x
//parameter CMPRS_STUFFER_NEG = 1 // stuffer runs @ negedge xclk2x
)(
input rst,
// input rst,
input xclk, // global clock input, compressor single clock rate
// input xclk2x, // global clock input, compressor double clock rate, nominally rising edge aligned
input mclk, // global system/memory clock
input mrst, // @posedge mclk, sync reset
input ctrl_we, // input - @mclk control register write enable
input format_we, // input - @mclk write number of tiles and left margin
input color_sat_we, // input - @mclk write color saturation values
......@@ -236,57 +236,57 @@ module cmprs_cmd_decode#(
wire frame_start_xclk;
assign cmprs_en_mclk = cmprs_en_mclk_r;
always @ (posedge rst or posedge mclk) begin
if (rst) ctrl_we_r <= 0;
else ctrl_we_r <= ctrl_we;
always @ (posedge mclk) begin
if (mrst) ctrl_we_r <= 0;
else ctrl_we_r <= ctrl_we;
if (rst) format_we_r <= 0;
else format_we_r <= format_we;
if (mrst) format_we_r <= 0;
else format_we_r <= format_we;
if (rst) color_sat_we_r <= 0;
else color_sat_we_r <= color_sat_we;
if (mrst) color_sat_we_r <= 0;
else color_sat_we_r <= color_sat_we;
if (rst) coring_we_r <= 0;
else coring_we_r <= coring_we;
if (mrst) coring_we_r <= 0;
else coring_we_r <= coring_we;
if (rst) di_r <= 0;
if (mrst) di_r <= 0;
else if (ctrl_we || format_we || color_sat_we || coring_we) di_r <= di[30:0];
if (rst) cmprs_en_mclk_r <= 0;
if (mrst) cmprs_en_mclk_r <= 0;
else if (ctrl_we_r && di_r[CMPRS_CBIT_RUN]) cmprs_en_mclk_r <= (di_r[CMPRS_CBIT_RUN-1 -:CMPRS_CBIT_RUN_BITS] != CMPRS_CBIT_RUN_RST);
if (rst) cmprs_run_mclk <= 0;
if (mrst) cmprs_run_mclk <= 0;
else if (ctrl_we_r && di_r[CMPRS_CBIT_RUN]) cmprs_run_mclk <= (di_r[CMPRS_CBIT_RUN-1 -:CMPRS_CBIT_RUN_BITS] == CMPRS_CBIT_RUN_ENABLE);
if (rst) cmprs_standalone <= 0;
if (mrst) cmprs_standalone <= 0;
else if (ctrl_we_r) cmprs_standalone <= ctrl_we_r && di_r[CMPRS_CBIT_RUN] && (di_r[CMPRS_CBIT_RUN-1 -:CMPRS_CBIT_RUN_BITS] == CMPRS_CBIT_RUN_STANDALONE);
if (rst) sigle_frame_buf <= 0;
if (mrst) sigle_frame_buf <= 0;
else if (ctrl_we_r && di_r[CMPRS_CBIT_FRAMES]) sigle_frame_buf <= (di_r[CMPRS_CBIT_FRAMES-1 -:CMPRS_CBIT_FRAMES_BITS] == CMPRS_CBIT_FRAMES_SINGLE);
if (rst) cmprs_qpage_mclk <= 0;
if (mrst) cmprs_qpage_mclk <= 0;
else if (ctrl_we_r && di_r[CMPRS_CBIT_QBANK]) cmprs_qpage_mclk <= di_r[CMPRS_CBIT_QBANK-1 -:CMPRS_CBIT_QBANK_BITS];
if (rst) cmprs_dcsub_mclk <= 0;
if (mrst) cmprs_dcsub_mclk <= 0;
else if (ctrl_we_r && di_r[CMPRS_CBIT_DCSUB]) cmprs_dcsub_mclk <= di_r[CMPRS_CBIT_DCSUB-1 -:CMPRS_CBIT_DCSUB_BITS];
if (rst) cmprs_mode_mclk <= 0;
if (mrst) cmprs_mode_mclk <= 0;
else if (ctrl_we_r && di_r[CMPRS_CBIT_CMODE]) cmprs_mode_mclk <= di_r[CMPRS_CBIT_CMODE-1 -:CMPRS_CBIT_CMODE_BITS];
if (rst) cmprs_fmode_mclk <= 0;
if (mrst) cmprs_fmode_mclk <= 0;
else if (ctrl_we_r && di_r[CMPRS_CBIT_FOCUS]) cmprs_fmode_mclk <= di_r[CMPRS_CBIT_FOCUS-1 -:CMPRS_CBIT_FOCUS_BITS];
if (rst) bayer_shift_mclk <= 0;
if (mrst) bayer_shift_mclk <= 0;
else if (ctrl_we_r && di_r[CMPRS_CBIT_BAYER]) bayer_shift_mclk <= di_r[CMPRS_CBIT_BAYER-1 -:CMPRS_CBIT_BAYER_BITS];
if (rst) format_mclk <= 0;
if (mrst) format_mclk <= 0;
else if (format_we_r) format_mclk <= di_r[30:0];
if (rst) color_sat_mclk <= 0;
if (mrst) color_sat_mclk <= 0;
else if (color_sat_we_r) color_sat_mclk <= di_r[23:0];
if (rst) coring_mclk <= 0;
if (mrst) coring_mclk <= 0;
else if (coring_we_r) coring_mclk <= di_r[2:0];
end
......@@ -438,11 +438,11 @@ module cmprs_cmd_decode#(
end
//frame_start_xclk
pulse_cross_clock ctrl_we_xclk_i (.rst(rst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(ctrl_we_r), .out_pulse(ctrl_we_xclk),.busy());
pulse_cross_clock format_we_xclk_i (.rst(rst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(format_we_r), .out_pulse(format_we_xclk),.busy());
pulse_cross_clock color_sat_we_xclk_i (.rst(rst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(color_sat_we_r), .out_pulse(color_sat_we_xclk),.busy());
pulse_cross_clock coring__we_xclk_i (.rst(rst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(coring_we_r), .out_pulse(coring_we_xclk),.busy());
pulse_cross_clock ctrl_we_xclk_i (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(ctrl_we_r), .out_pulse(ctrl_we_xclk),.busy());
pulse_cross_clock format_we_xclk_i (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(format_we_r), .out_pulse(format_we_xclk),.busy());
pulse_cross_clock color_sat_we_xclk_i (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(color_sat_we_r), .out_pulse(color_sat_we_xclk),.busy());
pulse_cross_clock coring__we_xclk_i (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(coring_we_r), .out_pulse(coring_we_xclk),.busy());
pulse_cross_clock frame_start_xclk_i (.rst(rst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(frame_start), .out_pulse(frame_start_xclk),.busy());
pulse_cross_clock frame_start_xclk_i (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(frame_start), .out_pulse(frame_start_xclk),.busy());
endmodule
compressor_jp/cmprs_frame_sync.v
View file @ b721ae66
......@@ -27,10 +27,12 @@ module cmprs_frame_sync#(
parameter CMPRS_TIMEOUT= 1000 // mclk cycles
)(
input rst,
// input rst,
input xclk, // global clock input, compressor single clock rate
// input xclk2x, // global clock input, compressor double clock rate, nominally rising edge aligned
input mclk, // global system/memory clock
input mrst, // @posedge mclk, sync reset
input xrst, // @posedge xclk, sync reset
input cmprs_en, // @mclk 0 resets immediately
output cmprs_en_extend, // @mclk keep compressor enabled for graceful shutdown
......@@ -90,9 +92,9 @@ module cmprs_frame_sync#(
assign stuffer_running_mclk = stuffer_running_mclk_r;
assign reading_frame = reading_frame_r;
always @ (posedge rst or posedge mclk) begin
if (rst) cmprs_en_extend_r <= 0;
else if (cmprs_en) cmprs_en_extend_r <= 1;
always @ (posedge mclk) begin
if (mrst) cmprs_en_extend_r <= 0;
else if (cmprs_en) cmprs_en_extend_r <= 1;
else if ((timeout == 0) || !stuffer_running_mclk_r) cmprs_en_extend_r <= 0;
end
......@@ -132,8 +134,8 @@ module cmprs_frame_sync#(
end
pulse_cross_clock vsync_late_mclk_i (.rst(rst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(vsync_late), .out_pulse(vsync_late_mclk),.busy());
pulse_cross_clock frame_started_i (.rst(rst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(frame_started), .out_pulse(frame_started_mclk),.busy());
pulse_cross_clock vsync_late_mclk_i (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(vsync_late), .out_pulse(vsync_late_mclk),.busy());
pulse_cross_clock frame_started_i (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(frame_started), .out_pulse(frame_started_mclk),.busy());
endmodule
compressor_jp/cmprs_macroblock_buf_iface.v
View file @ b721ae66
......@@ -25,10 +25,13 @@
module cmprs_macroblock_buf_iface #(
)(
input rst,
// input rst,
input xclk, // global clock input, compressor single clock rate
input mclk, // global clock for commands (posedge) and write side of the memory buffer (negedge)
input mrst, // @posedge mclk, sync reset
input xrst, // @posedge xclk, sync reset
// buffer interface, DDR3 memory read
input xfer_reset_page_rd, // @ negedge mclk - reset ddr3 memory buffer. Use it to reset the read buffer too
input page_ready_chn, // single mclk (posedge)
......@@ -200,18 +203,19 @@ module cmprs_macroblock_buf_iface #(
end
reg nmrst;
always @(negedge mclk) nmrst <= mrst;
// synchronization between mclk and xclk clock domains
// negedge mclk -> xclk (verify clock inversion is absorbed)
pulse_cross_clock reset_page_rd_i (.rst(rst), .src_clk(~mclk),.dst_clk(xclk), .in_pulse(xfer_reset_page_rd), .out_pulse(reset_page_rd),.busy());
pulse_cross_clock reset_page_rd_i (.rst(nmrst), .src_clk(~mclk),.dst_clk(xclk), .in_pulse(xfer_reset_page_rd), .out_pulse(reset_page_rd),.busy());
// mclk -> xclk
pulse_cross_clock page_ready_i (.rst(rst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(page_ready_chn), .out_pulse(page_ready),.busy());
pulse_cross_clock page_ready_i (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(page_ready_chn), .out_pulse(page_ready),.busy());
multipulse_cross_clock #(
.WIDTH(3),
.EXTRA_DLY(0)
) multipulse_cross_clock_i (
.rst (rst), // input
.rst (xrst), // input
.src_clk (xclk), // input
.dst_clk (mclk), // input
.num_pulses ({1'b0,add_invalid}), // input[0:0]
......
compressor_jp/cmprs_out_fifo.v
View file @ b721ae66
......@@ -21,9 +21,11 @@
`timescale 1ns/1ps
module cmprs_out_fifo(
input rst, // mostly for simulation
// input rst, // mostly for simulation
// wclk domain
input wclk, // source clock (2x pixel clock, inverted)
input wrst, // @posedge wclk, sync reset
input we,
input [15:0] wdata,
input wa_rst, // reset low address bits when stuffer is disabled (to make sure it is multiple of 32 bytes
......@@ -32,13 +34,14 @@ module cmprs_out_fifo(
// rclk domain
input rclk,
input rst_fifo, // reset FIFO (set read address to write, reset count)
input rrst, // @posedge rclk, sync reset
input rst_fifo, // reset FIFO (set read address to write, reset count)
input ren,
output [63:0] rdata,
output eof, // single rclk pulse signalling EOF
input eof_written, // confirm frame written ofer AFI to the system memory (single rclk pulse)
output flush_fifo, // EOF, need to output all what is in FIFO (Stays active until enough data chunks are read)
output [7:0] fifo_count // number of 32-byte chunks in FIFO
output eof, // single rclk pulse signalling EOF
input eof_written, // confirm frame written ofer AFI to the system memory (single rclk pulse)
output flush_fifo, // EOF, need to output all what is in FIFO (Stays active until enough data chunks are read)
output [7:0] fifo_count // number of 32-byte chunks in FIFO
);
reg regen;
......@@ -54,8 +57,8 @@ module cmprs_out_fifo(
assign fifo_count = count32;
assign eof = wlast_rclk;
always @ (posedge rst or posedge wclk) begin
if (rst) waddr <= 0;
always @ (posedge wclk) begin
if (wrst) waddr <= 0;
else if (wa_rst) waddr <= waddr & 11'h7f0; // reset 4 LSBs only
else if (we) waddr <= waddr + 1;
end
......@@ -82,10 +85,10 @@ module cmprs_out_fifo(
end
// wclk -> rclk
pulse_cross_clock written32b_i (.rst(rst), .src_clk(wclk), .dst_clk(rclk), .in_pulse(we && (&waddr[3:0])), .out_pulse(written32b),.busy());
pulse_cross_clock wlast_rclk_i (.rst(rst), .src_clk(wclk), .dst_clk(rclk), .in_pulse(wlast), .out_pulse(wlast_rclk),.busy());
pulse_cross_clock written32b_i (.rst(wrst), .src_clk(wclk), .dst_clk(rclk), .in_pulse(we && (&waddr[3:0])), .out_pulse(written32b),.busy());
pulse_cross_clock wlast_rclk_i (.rst(wrst), .src_clk(wclk), .dst_clk(rclk), .in_pulse(wlast), .out_pulse(wlast_rclk),.busy());
// rclk -> wclk
pulse_cross_clock eof_written_wclk_i (.rst(rst), .src_clk(rclk), .dst_clk(wclk), .in_pulse(eof_written), .out_pulse(eof_written_wclk),.busy());
pulse_cross_clock eof_written_wclk_i (.rst(rrst), .src_clk(rclk), .dst_clk(wclk), .in_pulse(eof_written), .out_pulse(eof_written_wclk),.busy());
ram_var_w_var_r #(
.REGISTERS(1),
.LOG2WIDTH_WR(4),
......
compressor_jp/compressor393.v
View file @ b721ae66
......@@ -113,9 +113,13 @@ module compressor393 # (
parameter AFI_MUX_BUF_LATENCY = 2 // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
)(
input rst, // global reset
// input rst, // global reset
input xclk, // global clock input, compressor single clock rate
input xclk2x, // global clock input, compressor double clock rate, nominally rising edge aligned
input mrst, // @posedge mclk, sync reset
input xrst, // @posedge xclk, sync reset
input hrst, // @posedge hclk, sync reset
// programming interface
input mclk, // global system/memory clock
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
......@@ -244,8 +248,9 @@ module compressor393 # (
/* Instance template for module status_router8 */
status_router8 status_router8_i (
.rst (rst), // input
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.db_in0 (status_ad_mux[ 0 +: 8]), // input[7:0]
.rq_in0 (status_rq_mux[0]), // input
.start_in0 (status_start_mux[0]), // output
......@@ -354,9 +359,12 @@ module compressor393 # (
.CMPRS_TIMEOUT_BITS (CMPRS_TIMEOUT_BITS),
.CMPRS_TIMEOUT (CMPRS_TIMEOUT)
) jp_channel_i (
.rst (rst), // input
// .rst (rst), // input
.xclk (xclk), // input
.xclk2x (xclk2x), // input
.mrst (mrst), // input
.xrst (xrst), // input
.hrst (hrst), // input
.mclk (mclk), // input
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
......@@ -417,9 +425,11 @@ module compressor393 # (
.CMPRS_AFIMUX_CYCBITS (CMPRS_AFIMUX_CYCBITS),
.AFI_MUX_BUF_LATENCY (AFI_MUX_BUF_LATENCY)
) cmprs_afi0_mux_i (
.rst (rst), // input
// .rst (rst), // input
.mclk (mclk), // input
.hclk (hclk), // input
.mrst (mrst), // input
.hrst (hrst), // input
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
.status_ad (status_ad_mux[32 +: 8]), // output[7:0]
......@@ -490,9 +500,11 @@ module compressor393 # (
.CMPRS_AFIMUX_CYCBITS (CMPRS_AFIMUX_CYCBITS),
.AFI_MUX_BUF_LATENCY (AFI_MUX_BUF_LATENCY)
) cmprs_afi1_mux_i (
.rst (rst), // input
// .rst (rst), // input
.mclk (mclk), // input
.hclk (hclk), // input
.mrst (mrst), // input
.hrst (hrst), // input
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
.status_ad (status_ad_mux[40 +: 8]), // output[7:0]
......@@ -561,9 +573,11 @@ module compressor393 # (
.CMPRS_AFIMUX_CYCBITS (CMPRS_AFIMUX_CYCBITS),
.AFI_MUX_BUF_LATENCY (AFI_MUX_BUF_LATENCY)
) cmprs_afi0_mux_i (
.rst (rst), // input
// .rst (rst), // input
.mclk (mclk), // input
.hclk (hclk), // input
.mrst (mrst), // input
.hrst (hrst), // input
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
.status_ad (status_ad_mux[32 +: 8]), // output[7:0]
......
compressor_jp/jp_channel.v
View file @ b721ae66
This diff is collapsed.
compressor_jp/stuffer393.v
View file @ b721ae66
......@@ -42,8 +42,11 @@
// Or make FIFO outside of the stuffer?
module stuffer393 (
input rst, // global reset
// input rst, // global reset
input mclk,
input mrst, // @posedge mclk, sync reset
input xrst, // @posedge xclk, sync reset
// time stamping - will copy time at the end of color_first (later than the first hact after vact in the current frame, but before the next one
// and before the data is needed for output
input ts_pre_stb, // @mclk - 1 cycle before receiving 8 bytes of timestamp data
......@@ -414,17 +417,23 @@ end
// extract strart of frame run from different clock, re-clock from the source
always @ (posedge fradv_clk) color_first_r <= color_first;
pulse_cross_clock stb_start_i (.rst(rst), .src_clk(fradv_clk), .dst_clk(~clk), .in_pulse(!color_first && color_first_r), .out_pulse(stb_start),.busy());
pulse_cross_clock stb_start_i (.rst(xrst), .src_clk(fradv_clk), .dst_clk(~clk), .in_pulse(!color_first && color_first_r), .out_pulse(stb_start),.busy());
reg rst_nclk;
always @ (negedge clk) rst_nclk <= xrst;
timestamp_fifo timestamp_fifo_i (
.rst (rst), // input
// .rst (rst), // input
.sclk (mclk), // input
.srst (mrst), // input
.pre_stb (ts_pre_stb), // input
.din (ts_data), // input[7:0]
// may use stb_start @ negedge clk
.aclk (~clk), //fradv_clk), // input
.arst (rst_nclk), //fradv_clk), // input
.advance (stb_start), // color_first), // input
.rclk (~clk), // input
.rrst (rst_nclk), //fradv_clk), // input
.rstb (ts_rstb), // input
.dout (ts_dout) // output[7:0] reg
);
......
logger/event_logger.v
View file @ b721ae66
......@@ -51,9 +51,11 @@ module event_logger#(
parameter GPIO_N = 10 // number of GPIO bits to control
)(
input rst,
// input rst,
input mclk, // system clock
input xclk, // half frequency (80 MHz nominal)
input xclk, // was in 353: half frequency (80 MHz nominal)
input mrst, // @ posedge mclk - sync reset
input xrst, // @ posedge xclk - sync reset
// programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
......@@ -296,12 +298,12 @@ module event_logger#(
end
// generate strobes to copy configuration data from mclk to xclk domain
pulse_cross_clock i_we_config_imu_xclk (.rst(1'b0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_imu), .out_pulse(we_config_imu_xclk),.busy());
pulse_cross_clock i_we_config_gps_xclk (.rst(1'b0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_gps), .out_pulse(we_config_gps_xclk),.busy());
pulse_cross_clock i_we_config_msg_xclk (.rst(1'b0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_msg), .out_pulse(we_config_msg_xclk),.busy());
pulse_cross_clock i_we_config_rst_xclk (.rst(1'b0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_rst), .out_pulse(we_config_rst_xclk),.busy());
pulse_cross_clock i_we_config_debug_xclk (.rst(1'b0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_debug), .out_pulse(we_config_debug_xclk),.busy());
pulse_cross_clock i_we_bitHalfPeriod_xclk (.rst(1'b0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_bitHalfPeriod), .out_pulse(we_bitHalfPeriod_xclk),.busy());
pulse_cross_clock i_we_config_imu_xclk (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_imu), .out_pulse(we_config_imu_xclk),.busy());
pulse_cross_clock i_we_config_gps_xclk (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_gps), .out_pulse(we_config_gps_xclk),.busy());
pulse_cross_clock i_we_config_msg_xclk (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_msg), .out_pulse(we_config_msg_xclk),.busy());
pulse_cross_clock i_we_config_rst_xclk (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_rst), .out_pulse(we_config_rst_xclk),.busy());
pulse_cross_clock i_we_config_debug_xclk (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_debug), .out_pulse(we_config_debug_xclk),.busy());
pulse_cross_clock i_we_bitHalfPeriod_xclk (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_bitHalfPeriod), .out_pulse(we_bitHalfPeriod_xclk),.busy());
cmd_deser #(
.ADDR (LOGGER_ADDR),
......@@ -313,8 +315,9 @@ module event_logger#(
.ADDR_MASK1 (LOGGER_STATUS_MASK)
) cmd_deser_32bit_i (
.rst (rst), // input
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[3:0]
......@@ -327,8 +330,9 @@ module event_logger#(
.PAYLOAD_BITS (26),
.REGISTER_STATUS (1)
) status_generate_i (
.rst (rst), // input
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (cmd_status), // input
.wd (cmd_data[7:0]), // input[7:0]
.status ({sample_counter,2'b0}), // input[25:0] // 2 LSBs - may add "real" status
......@@ -378,9 +382,11 @@ fixed-length de-noise circuitry with latency 256*T(xclk) (~3usec)
/* logs frame synchronization data from other camera (same as frame sync) */
// ts_stb (mclk) -> trig)
imu_exttime393 i_imu_exttime(
.rst (rst), // input global reset
// .rst (rst), // input global reset
.mclk (mclk), // system clock, negedge
.xclk (xclk), // half frequency (80 MHz nominal)
.mrst (mrst), // @mclk - sync reset
.xrst (xrst), // @xclk - sync reset
.en_chn_mclk (enable_syn_mclk), // enable module operation, if 0 - reset
.ts_stb_chn0 (ts_stb_chn0), // input
.ts_data_chn0 (ts_data_chn0), // input[7:0]
......
logger/imu_exttime393.v
View file @ b721ae66
......@@ -25,9 +25,11 @@ When sensors are running in free running mode, each sensor may provide individua
*/
module imu_exttime393(
input rst,
// input rst,
input mclk, // system clock, negedge TODO:COnvert to posedge!
input xclk, // half frequency (80 MHz nominal)
input mrst, // @ posedge mclk - sync reset
input xrst, // @ posedge xclk - sync reset
input [3:0] en_chn_mclk, // enable per-channel module operation, if all 0 - reset
// byte-parallel timestamps from 4 sensors channels (in triggered mode all are the same, different only in free running mode)
// each may generate logger event, channel number encoded in bits 25:24 of the external microseconds
......@@ -128,58 +130,70 @@ module imu_exttime393(
timestamp_fifo timestamp_fifo_chn0_i (
.rst (rst), // input
// .rst (rst), // input
.sclk (mclk), // input
.srst (mrst), // input
.pre_stb (ts_stb[0]), // input
.din (ts_data_chn0), // input[7:0]
.aclk (mclk), // input
.arst (mrst), // input
.advance (ts_stb[0]), // enough time
.rclk (mclk), // input
.rrst (mrst), // input
.rstb (pre_copy_started && (sel_chn == 2'h0)),// input
.dout (dout_chn[0 * 8 +: 8]) // output[7:0] reg valid with copy_selected[1]
);
timestamp_fifo timestamp_fifo_chn1_i (
.rst (rst), // input
// .rst (rst), // input
.sclk (mclk), // input
.srst (mrst), // input
.pre_stb (ts_stb[1]), // input
.din (ts_data_chn1), // input[7:0]
.aclk (mclk), // input
.arst (mrst), // input
.advance (ts_stb[1]), // enough time
.rclk (mclk), // input
.rrst (mrst), // input
.rstb (pre_copy_started && (sel_chn == 2'h1)),// input
.dout (dout_chn[1 * 8 +: 8]) // output[7:0] reg valid with copy_selected[1]
);
timestamp_fifo timestamp_fifo_chn2_i (
.rst (rst), // input
// .rst (rst), // input
.sclk (mclk), // input
.srst (mrst), // input
.pre_stb (ts_stb[2]), // input
.din (ts_data_chn2), // input[7:0]
.aclk (mclk), // input
.arst (mrst), // input
.advance (ts_stb[2]), // enough time
.rclk (mclk), // input
.rrst (mrst), // input
.rstb (pre_copy_started && (sel_chn == 2'h2)),// input
.dout (dout_chn[2 * 8 +: 8]) // output[7:0] reg valid with copy_selected[1]
);
timestamp_fifo timestamp_fifo_chn3_i (
.rst (rst), // input
// .rst (rst), // input
.sclk (mclk), // input
.srst (mrst), // input
.pre_stb (ts_stb[3]), // input
.din (ts_data_chn3), // input[7:0]
.aclk (mclk), // input
.arst (mrst), // input
.advance (ts_stb[3]), // enough time
.rclk (mclk), // input
.rrst (mrst), // input
.rstb (pre_copy_started && (sel_chn == 2'h3)),// input
.dout (dout_chn[3 * 8 +: 8]) // output[7:0] reg valid with copy_selected[1]
);
pulse_cross_clock i_rd_start_mclk (.rst(1'b0), .src_clk(xclk), .dst_clk(mclk), .in_pulse(rd_start), .out_pulse(rd_start_mclk),.busy());
pulse_cross_clock i_rd_start_mclk (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(rd_start), .out_pulse(rd_start_mclk),.busy());
// generate timestamp request as soon as one of the sub-channels starts copying. That time stamp will be stored for this (ext) channel
pulse_cross_clock i_ts (.rst(1'b0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(pre_copy_w), .out_pulse(ts),.busy());
pulse_cross_clock i_ts (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(pre_copy_w), .out_pulse(ts),.busy());
endmodule
memctrl/cmd_encod_linear_rd.v
View file @ b721ae66
......@@ -30,7 +30,7 @@ module cmd_encod_linear_rd #(
parameter CMD_DONE_BIT= 10, // VDT BUG: CMD_DONE_BIT is used in a function call parameter!
parameter RSEL= 1'b1
) (
input rst,
input mrst,
input clk,
// programming interface
// input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
......@@ -90,20 +90,18 @@ module cmd_encod_linear_rd #(
assign rom_skip= rom_r[ENC_PAUSE_SHIFT+:2];
assign full_cmd= rom_cmd[1]?(rom_cmd[0]?CMD_ACTIVATE:CMD_PRECHARGE):(rom_cmd[0]?CMD_READ:CMD_NOP);
always @ (posedge rst or posedge clk) begin
if (rst) gen_run <= 0;
always @ (posedge clk) begin
if (mrst) gen_run <= 0;
else if (start) gen_run<= 1;
else if (pre_done) gen_run<= 0;
// if (rst) gen_run_d <= 0;
// else gen_run_d <= gen_run;
if (rst) gen_addr <= 0;
if (mrst) gen_addr <= 0;
else if (!start && !gen_run) gen_addr <= 0;
else if ((gen_addr==(REPEAT_ADDR-1)) && (num128[NUM_XFER_BITS-1:1]==0)) gen_addr <= REPEAT_ADDR+1; // skip loop alltogeter
else if ((gen_addr !=REPEAT_ADDR) || (num128[NUM_XFER_BITS-1:1]==0)) gen_addr <= gen_addr+1; // not in a loop
//counting loops?
if (rst) num128 <= 0;
if (mrst) num128 <= 0;
else if (start) num128 <= num128_in;
else if (!gen_run) num128 <= 0; //
else if ((gen_addr == (REPEAT_ADDR-1)) || (gen_addr == REPEAT_ADDR)) num128 <= num128 -1;
......@@ -121,8 +119,8 @@ module cmd_encod_linear_rd #(
end
// ROM-based (registered output) encoded sequence
always @ (posedge rst or posedge clk) begin
if (rst) rom_r <= 0;
always @ (posedge clk) begin
if (mrst) rom_r <= 0;
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT);
4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PAUSE_SHIFT);
......@@ -136,17 +134,15 @@ module cmd_encod_linear_rd #(
default:rom_r <= 0;
endcase
end
always @ (posedge rst or posedge clk) begin
// if (rst) done <= 0;
// else done <= pre_done;
always @ (posedge clk) begin
if (rst) enc_wr <= 0;
if (mrst) enc_wr <= 0;
else enc_wr <= gen_run; // || gen_run_d;
if (rst) enc_done <= 0;
if (mrst) enc_done <= 0;
else enc_done <= enc_wr && !gen_run; // !gen_run_d;
if (rst) enc_cmd <= 0;
if (mrst) enc_cmd <= 0;
else if (gen_run) begin
if (rom_cmd==0) enc_cmd <= func_encode_skip ( // encode pause
{{CMD_PAUSE_BITS-2{1'b0}},rom_skip[1:0]}, // skip; // number of extra cycles to skip (and keep all the other outputs)
......@@ -184,74 +180,5 @@ module cmd_encod_linear_rd #(
// move to include?
`include "includes/x393_mcontr_encode_cmd.vh"
/*
function [31:0] func_encode_skip;
input [CMD_PAUSE_BITS-1:0] skip; // number of extra cycles to skip (and keep all the other outputs)
input done; // end of sequence
input [2:0] bank; // bank (here OK to be any)
input odt_en; // enable ODT
input cke; // disable CKE
input sel; // first/second half-cycle, other will be nop (cke+odt applicable to both)
input dq_en; // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
input dqs_en; // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
input dqs_toggle; // enable toggle DQS according to the pattern
input dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
input buf_wr; // connect to external buffer (but only if not paused)
input buf_rd; // connect to external buffer (but only if not paused)
input buf_rst; // connect to external buffer (but only if not paused)
begin
func_encode_skip= func_encode_cmd (
{{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]}, // 15-bit row/column address
bank[2:0], // bank (here OK to be any)
3'b0, // RAS/CAS/WE, positive logic
odt_en, // enable ODT
cke, // disable CKE
sel, // first/second half-cycle, other will be nop (cke+odt applicable to both)
dq_en, // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
dqs_en, // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
dqs_toggle, // enable toggle DQS according to the pattern
dci, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
buf_wr, // connect to external buffer (but only if not paused)
buf_rd, // connect to external buffer (but only if not paused)
1'b0, // nop
buf_rst);
end
endfunction
function [31:0] func_encode_cmd;
input [14:0] addr; // 15-bit row/column address
input [2:0] bank; // bank (here OK to be any)
input [2:0] rcw; // RAS/CAS/WE, positive logic
input odt_en; // enable ODT
input cke; // disable CKE
input sel; // first/second half-cycle, other will be nop (cke+odt applicable to both)
input dq_en; // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
input dqs_en; // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
input dqs_toggle; // enable toggle DQS according to the pattern
input dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
input buf_wr; // connect to external buffer (but only if not paused)
input buf_rd; // connect to external buffer (but only if not paused)
input nop; // add NOP after the current command, keep other data
input buf_rst; // connect to external buffer (but only if not paused)
begin
func_encode_cmd={
addr[14:0], // 15-bit row/column address
bank [2:0], // bank
rcw[2:0], // RAS/CAS/WE
odt_en, // enable ODT
cke, // may be optimized (removed from here)?
sel, // first/second half-cycle, other will be nop (cke+odt applicable to both)
dq_en, // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
dqs_en, // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
dqs_toggle, // enable toggle DQS according to the pattern
dci, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
buf_wr, // phy_buf_wr, // connect to external buffer (but only if not paused)
buf_rd, // phy_buf_rd, // connect to external buffer (but only if not paused)
nop, // add NOP after the current command, keep other data
buf_rst // Reserved for future use
};
end
endfunction
*/
endmodule
/endmodule
memctrl/cmd_encod_linear_rw.v
View file @ b721ae66
......@@ -30,7 +30,7 @@ module cmd_encod_linear_rw#(
parameter RSEL= 1'b1, // late/early READ commands (to adjust timing by 1 SDCLK period)
parameter WSEL= 1'b0 // late/early WRITE commands (to adjust timing by 1 SDCLK period)
) (
input rst,
input mrst,
input clk,
// programming interface
// input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
......@@ -63,7 +63,7 @@ module cmd_encod_linear_rw#(
.CMD_DONE_BIT (CMD_DONE_BIT),
.RSEL (RSEL)
) cmd_encod_linear_rd_i (
.rst (rst), // input
.mrst (mrst), // input
.clk (clk), // input
.bank_in (bank_in), // input[2:0]
.row_in (row_in), // input[14:0]
......@@ -84,7 +84,7 @@ module cmd_encod_linear_rw#(
.CMD_DONE_BIT (CMD_DONE_BIT),
.WSEL (WSEL)
) cmd_encod_linear_wr_i (
.rst (rst), // input
.mrst (mrst), // input
.clk (clk), // input
.bank_in (bank_in), // input[2:0]
.row_in (row_in), // input[14:0]
......@@ -97,11 +97,11 @@ module cmd_encod_linear_rw#(
.enc_done (enc_done_wr) // output reg
);
always @(posedge rst or posedge clk) begin
if (rst) start <= 0;
always @(posedge clk) begin
if (mrst) start <= 0;
else start <= start_rd || start_wr;
if (rst) select_wr <= 0;
if (mrst) select_wr <= 0;
else if (start_rd) select_wr <= 0;
else if (start_wr) select_wr <= 1;
end
......
memctrl/cmd_encod_linear_wr.v
View file @ b721ae66
......@@ -29,7 +29,7 @@ module cmd_encod_linear_wr #(
parameter CMD_DONE_BIT= 10, // VDT BUG: CMD_DONE_BIT is used in a function call parameter!
parameter WSEL= 1'b0
) (
input rst,
input mrst,
input clk,
// programming interface
input [2:0] bank_in, // bank address
......@@ -117,58 +117,39 @@ module cmd_encod_linear_wr #(
start_d <= start;
cut_buf_rd <= rom_r[ENC_BUF_RD] && (cut_buf_rd || next_zero_w);
end
always @ (posedge rst or posedge clk) begin
always @ (posedge clk) begin
if (rst) gen_run <= 0;
if (mrst) gen_run <= 0;
else if (start) gen_run<= 1;
else if (pre_done) gen_run<= 0;
// if (rst) gen_run_d <= 0;
// else gen_run_d <= gen_run;
if (rst) gen_addr <= 0;
if (mrst) gen_addr <= 0;
else if (!start && !gen_run) gen_addr <= 0;
else if ((gen_addr==(REPEAT_ADDR-1)) && few_write) gen_addr <= jump_gen_addr;
// else if ((gen_addr !=REPEAT_ADDR) || (num128[NUM_XFER_BITS:1]==0)) gen_addr <= gen_addr+1; // not in a loop
// else if ((gen_addr !=REPEAT_ADDR) || (num128==2)) gen_addr <= gen_addr+1; // not in a loop
else if ((gen_addr !=REPEAT_ADDR) || (num128[NUM_XFER_BITS:2]==0)) gen_addr <= gen_addr+1; // not in a loop
//counting loops
if (rst) num128 <= 0;
if (mrst) num128 <= 0;
else if (start) num128 <= {(num128_in==0)?1'b1:1'b0,num128_in};
else if (!gen_run) num128 <= 0; //
// else if ((gen_addr == (REPEAT_ADDR-1)) || (gen_addr == REPEAT_ADDR)) num128 <= num128 -1; // ????? - FIXME
else if (write_addr_w) num128 <= num128 -1;
if (rst) single_write <= 0;
if (mrst) single_write <= 0;
else if (start_d) single_write <= (num128[NUM_XFER_BITS:1]==0); // could not be 0
if (rst) dual_write <= 0;
if (mrst) dual_write <= 0;
else if (start_d) dual_write <= (num128==2);
// if (rst) triple_write <= 0;
// else if (start_d) triple_write <= (num128==3);
if (rst) few_write <= 0;
if (mrst) few_write <= 0;
else if (start_d) few_write <=(num128[NUM_XFER_BITS:2]==0); // (0,)1,2 or3
//
// if (rst) few_write <= 0;
// else few_write <= single_write | dual_write | triple_write;
if (rst) jump_gen_addr <= 0;
else jump_gen_addr <= single_write ? NO_WRITE_ADDR : (dual_write ? LAST_WRITE_ADDR : PRELAST_WRITE_ADDR);
//triple_write
// reg single_write; // only one burst has to be written
// reg dual_write; // Two bursts have to be written
if (mrst) jump_gen_addr <= 0;
else jump_gen_addr <= single_write ? NO_WRITE_ADDR : (dual_write ? LAST_WRITE_ADDR : PRELAST_WRITE_ADDR);
end
always @ (posedge clk) if (start) begin
row<=row_in;
// col <= start_col;
bank <= bank_in;
skip_next_page <= skip_next_page_in;
end
......@@ -180,8 +161,8 @@ module cmd_encod_linear_wr #(
// ROM-based (registered output) encoded sequence
// TODO: Remove last ENC_BUF_RD
always @ (posedge rst or posedge clk) begin
if (rst) rom_r <= 0;
always @ (posedge clk) begin
if (mrst) rom_r <= 0;
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD);// | (1 << ENC_NOP);
4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD);
......@@ -203,18 +184,16 @@ module cmd_encod_linear_wr #(
default:rom_r <= 0;
endcase
end
always @ (posedge rst or posedge clk) begin
// if (rst) done <= 0;
// else done <= pre_done;
always @ (posedge clk) begin
if (rst) enc_wr <= 0;
if (mrst) enc_wr <= 0;
else enc_wr <= gen_run; // || gen_run_d;
if (rst) enc_done <= 0;
// else enc_done <= enc_wr || !gen_run_d;
else enc_done <= enc_wr && !gen_run; // !gen_run_d;
if (mrst) enc_done <= 0;
// else enc_done <= enc_wr || !gen_run_d;
else enc_done <= enc_wr && !gen_run; // !gen_run_d;
if (rst) enc_cmd <= 0;
if (mrst) enc_cmd <= 0;
else if (gen_run) begin
if (rom_cmd==0) enc_cmd <= func_encode_skip ( // encode pause
{{CMD_PAUSE_BITS-2{1'b0}},rom_skip[1:0]}, // skip; // number of extra cycles to skip (and keep all the other outputs)
......
memctrl/cmd_encod_tiled_rd.v
View file @ b721ae66
......@@ -51,7 +51,7 @@ module cmd_encod_tiled_rd #(
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter RSEL= 1'b1
) (
input rst,
input mrst,
input clk,
// programming interface
input [2:0] start_bank, // bank address
......@@ -157,59 +157,55 @@ module cmd_encod_tiled_rd #(
assign pre_read= rom_r[ENC_CMD_SHIFT]; //1 cycle before READ command
always @ (posedge rst or posedge clk) begin
if (rst) gen_run <= 0;
always @ (posedge clk) begin
if (mrst) gen_run <= 0;
else if (start_d) gen_run<= 1; // delaying
else if (pre_done) gen_run<= 0;
// if (rst) gen_run_d <= 0;
// else gen_run_d <= gen_run;
if (rst) num_rows_m1 <= 0;
else if (start) num_rows_m1 <= num_rows_in_m1; // number of rows
if (rst) num_cols128_m1 <= 0;
else if (start) num_cols128_m1 <= num_cols_in_m1; // number of r16-byte columns
if (mrst) num_rows_m1 <= 0;
else if (start ) num_rows_m1 <= num_rows_in_m1; // number of rows
if (mrst) num_cols128_m1 <= 0;
else if (start) num_cols128_m1 <= num_cols_in_m1; // number of r16-byte columns
if (rst) start_d <=0;
else start_d <= start;
if (mrst) start_d <=0;
else start_d <= start;
if (rst) top_rc <= 0;
if (mrst) top_rc <= 0;
else if (start_d) top_rc <= {row,col}+1;
else if (pre_act && last_row) top_rc <= top_rc+1; // may increment RA
if (rst) row_col_bank <= 0;
else if (start_d) row_col_bank <= {row,col,bank}; // TODO: Use start_col,... and start, not start_d?
else if (pre_act) row_col_bank <= row_col_bank_next_w;
if (mrst) row_col_bank <= 0;
else if (start_d) row_col_bank <= {row,col,bank}; // TODO: Use start_col,... and start, not start_d?
else if (pre_act) row_col_bank <= row_col_bank_next_w;
if (rst) scan_row <= 0;
if (mrst) scan_row <= 0;
else if (start_d) scan_row <= 0;
else if (pre_act) scan_row <= last_row?0:scan_row+1;
if (rst) scan_col <= 0;
if (mrst) scan_col <= 0;
else if (start_d) scan_col <= 0;
else if (pre_act && last_row) scan_col <= scan_col+1; // for ACTIVATE, not for READ
if (rst) first_col <= 0;
if (mrst) first_col <= 0;
else if (start_d) first_col <= 1;
else if (pre_act && last_row) first_col <= 0;
if (rst) last_col <= 0;
if (mrst) last_col <= 0;
else if (start_d) last_col <= num_cols128_m1==0; // if single column - will start with 1'b1;
else if (pre_act) last_col <= (scan_col==num_cols128_m1); // too early for READ ?
if (rst) enable_autopre <= 0;
if (mrst) enable_autopre <= 0;
else if (start_d) enable_autopre <= 0;
else if (pre_act) enable_autopre <= last_col || !keep_open; // delayed by 2 pre_act tacts form last_col, OK with a single column
if (rst) loop_continue<=0;
else loop_continue <= (scan_col==num_cols128_m1) && last_row;
if (mrst) loop_continue<=0;
else loop_continue <= (scan_col==num_cols128_m1) && last_row;
if (rst) gen_addr <= 0;
else if (!start_d && !gen_run) gen_addr <= 0;
if (mrst) gen_addr <= 0;
else if (!start_d && !gen_run) gen_addr <= 0;
else if ((gen_addr==LOOP_LAST) && !loop_continue) gen_addr <= LOOP_FIRST; // skip loop alltogeter
else gen_addr <= gen_addr+1; // not in a loop
else gen_addr <= gen_addr+1; // not in a loop
end
always @ (posedge clk) if (start) begin
......@@ -222,8 +218,8 @@ module cmd_encod_tiled_rd #(
end
// ROM-based (registered output) encoded sequence
always @ (posedge rst or posedge clk) begin
if (rst) rom_r <= 0;
always @ (posedge clk) begin
if (mrst) rom_r <= 0;
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_PAUSE_SHIFT); // here does not matter, just to work with masked ACTIVATE
4'h1: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT);
......@@ -241,18 +237,15 @@ module cmd_encod_tiled_rd #(
default:rom_r <= 0;
endcase
end
always @ (posedge rst or posedge clk) begin
// if (rst) done <= 0;
// else done <= pre_done;
always @ (posedge clk) begin
if (rst) enc_wr <= 0;
if (mrst) enc_wr <= 0;
else enc_wr <= gen_run; // || gen_run_d;
if (rst) enc_done <= 0;
if (mrst) enc_done <= 0;
else enc_done <= enc_wr && !gen_run; // !gen_run_d;
if (rst) enc_cmd <= 0;
// else if ((rom_cmd==0) || (rom_cmd[1] && !enable_act)) enc_cmd <= func_encode_skip ( // encode pause
if (mrst) enc_cmd <= 0;
else if (gen_run) begin
if (rom_cmd[0] || (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
rom_cmd[1]? // activate
......@@ -295,13 +288,13 @@ module cmd_encod_tiled_rd #(
fifo_2regs #(
.WIDTH(COLADDR_NUMBER)
) fifo_2regs_i (
.rst (rst), // input
.clk (clk), // input
.mrst (mrst), // input
.clk (clk), // input
.din (row_col_bank[COLADDR_NUMBER-1:0]), // input[15:0]
.wr(pre_act), // input
.rd(pre_read), // input
.srst(start_d), // input
.dout(col_bank) // output[15:0]
.wr(pre_act), // input
.rd(pre_read), // input
.srst(start_d), // input
.dout(col_bank) // output[15:0]
);
`include "includes/x393_mcontr_encode_cmd.vh"
......
memctrl/cmd_encod_tiled_rw.v
View file @ b721ae66
......@@ -29,7 +29,7 @@ module cmd_encod_tiled_rw #(
parameter RSEL= 1'b1, // late/early READ commands (to adjust timing by 1 SDCLK period)
parameter WSEL= 1'b0 // late/early WRITE commands (to adjust timing by 1 SDCLK period)
) (
input rst,
input mrst,
input clk,
// programming interface
input [2:0] start_bank, // bank address
......@@ -62,21 +62,21 @@ module cmd_encod_tiled_rw #(
.CMD_DONE_BIT (CMD_DONE_BIT),
.RSEL (RSEL)
) cmd_encod_tiled_rd_i (
.rst (rst), // input
.clk (clk), // input
.start_bank (start_bank), // input[2:0]
.start_row (start_row), // input[14:0]
.start_col (start_col), // input[6:0]
.rowcol_inc_in (rowcol_inc_in), // input[13:0] // [21:0]
.num_rows_in_m1 (num_rows_in_m1), // input[5:0]
.num_cols_in_m1 (num_cols_in_m1), // input[5:0]
.keep_open_in (keep_open_in), // input
.mrst (mrst), // input
.clk (clk), // input
.start_bank (start_bank), // input[2:0]
.start_row (start_row), // input[14:0]
.start_col (start_col), // input[6:0]
.rowcol_inc_in (rowcol_inc_in), // input[13:0] // [21:0]
.num_rows_in_m1 (num_rows_in_m1), // input[5:0]
.num_cols_in_m1 (num_cols_in_m1), // input[5:0]
.keep_open_in (keep_open_in), // input
.skip_next_page_in (skip_next_page_in), // input
.start (start_rd), // input
.enc_cmd (enc_cmd_rd), // output[31:0] reg
.enc_wr (enc_wr_rd), // output reg
.enc_done (enc_done_rd) // output reg
.start (start_rd), // input
.enc_cmd (enc_cmd_rd), // output[31:0] reg
.enc_wr (enc_wr_rd), // output reg
.enc_done (enc_done_rd) // output reg
);
cmd_encod_tiled_wr #(
......@@ -86,7 +86,7 @@ module cmd_encod_tiled_rw #(
.CMD_DONE_BIT (CMD_DONE_BIT),
.WSEL (WSEL)
) cmd_encod_tiled_wr_i (
.rst (rst), // input
.mrst (mrst), // input
.clk (clk), // input
.start_bank (start_bank), // input[2:0]
.start_row (start_row), // input[14:0]
......@@ -94,7 +94,7 @@ module cmd_encod_tiled_rw #(
.rowcol_inc_in (rowcol_inc_in), // input[13:0] // [21:0]
.num_rows_in_m1 (num_rows_in_m1), // input[5:0]
.num_cols_in_m1 (num_cols_in_m1), // input[5:0]
.keep_open_in (keep_open_in), // input
.keep_open_in (keep_open_in), // input
.skip_next_page_in (skip_next_page_in), // input
.start (start_wr), // input
......@@ -103,11 +103,11 @@ module cmd_encod_tiled_rw #(
.enc_done (enc_done_wr) // output reg
);
always @(posedge rst or posedge clk) begin
if (rst) start <= 0;
always @(posedge clk) begin
if (mrst) start <= 0;
else start <= start_rd || start_wr;
if (rst) select_wr <= 0;
if (mrst) select_wr <= 0;
else if (start_rd) select_wr <= 0;
else if (start_wr) select_wr <= 1;
end
......
memctrl/cmd_encod_tiled_wr.v
View file @ b721ae66
......@@ -52,7 +52,7 @@ module cmd_encod_tiled_wr #(
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter WSEL= 1'b0
) (
input rst,
input mrst,
input clk,
// programming interface
input [2:0] start_bank, // bank address
......@@ -164,57 +164,54 @@ module cmd_encod_tiled_wr #(
assign pre_write= rom_r[ENC_CMD_SHIFT]; //1 cycle before READ command
always @ (posedge rst or posedge clk) begin
if (rst) gen_run <= 0;
always @ (posedge clk) begin
if (mrst) gen_run <= 0;
else if (start_d) gen_run<= 1; // delaying
else if (pre_done) gen_run<= 0;
// if (rst) gen_run_d <= 0;
// else gen_run_d <= gen_run;
if (rst) num_rows_m1 <= 0;
if (mrst) num_rows_m1 <= 0;
else if (start) num_rows_m1 <= num_rows_in_m1; // number of rows
if (rst) num_cols128_m1 <= 0;
if (mrst) num_cols128_m1 <= 0;
else if (start) num_cols128_m1 <= num_cols_in_m1; // number of r16-byte columns
if (rst) start_d <=0;
if (mrst) start_d <=0;
else start_d <= start;
if (rst) top_rc <= 0;
if (mrst) top_rc <= 0;
else if (start_d) top_rc <= {row,col}+1;
else if (pre_act && last_row) top_rc <= top_rc+1; // may increment RA
if (rst) row_col_bank <= 0;
if (mrst) row_col_bank <= 0;
else if (start_d) row_col_bank <= {row,col,bank}; // TODO: Use start_col,... and start, not start_d?
else if (pre_act) row_col_bank <= row_col_bank_next_w;
if (rst) scan_row <= 0;
if (mrst) scan_row <= 0;
else if (start_d) scan_row <= 0;
else if (pre_act) scan_row <= last_row?0:scan_row+1;
if (rst) scan_col <= 0;
if (mrst) scan_col <= 0;
else if (start_d) scan_col <= 0;
else if (pre_act && last_row) scan_col <= scan_col+1; // for ACTIVATE, not for READ
if (rst) first_col <= 0;
if (mrst) first_col <= 0;
else if (start_d) first_col <= 1;
else if (pre_act && last_row) first_col <= 0;
if (rst) last_col <= 0;
if (mrst) last_col <= 0;
else if (start_d) last_col <= num_cols128_m1==0; // if single column - will start with 1'b1;
else if (pre_act) last_col <= (scan_col==num_cols128_m1); // too early for READ ?
if (rst) enable_autopre <= 0;
if (mrst) enable_autopre <= 0;
else if (start_d) enable_autopre <= 0;
else if (pre_act) enable_autopre <= last_col || !keep_open; // delayed by 2 pre_act tacts form last_col, OK with a single column
if (rst) loop_continue<=0;
if (mrst) loop_continue<=0;
else loop_continue <= (scan_col==num_cols128_m1) && last_row;
if (rst) gen_addr <= 0;
if (mrst) gen_addr <= 0;
else if (!start_d && !gen_run) gen_addr <= 0;
else if ((gen_addr==LOOP_LAST) && !loop_continue) gen_addr <= LOOP_FIRST; // skip loop alltogeter
else gen_addr <= gen_addr+1; // not in a loop
......@@ -230,14 +227,13 @@ module cmd_encod_tiled_wr #(
end
// ROM-based (registered output) encoded sequence
always @ (posedge rst or posedge clk) begin
if (rst) rom_r <= 0;
always @ (posedge clk) begin
if (mrst) rom_r <= 0;
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) ; // here does not matter, just to work with masked ACTIVATE
4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) ;
4'h2: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL);
4'h3: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT);
// 4'h4: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN);
4'h4: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT);
4'h5: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
// start loop
......@@ -252,16 +248,14 @@ module cmd_encod_tiled_wr #(
default:rom_r <= 0;
endcase
end
always @ (posedge rst or posedge clk) begin
// if (rst) done <= 0;
// else done <= pre_done;
if (rst) enc_wr <= 0;
always @ (posedge clk) begin
if (mrst) enc_wr <= 0;
else enc_wr <= gen_run || gen_run; // gen_run_d; *****
if (rst) enc_done <= 0;
if (mrst) enc_done <= 0;
else enc_done <= enc_wr && !gen_run; // !gen_run_d; *****
if (rst) enc_cmd <= 0;
if (mrst) enc_cmd <= 0;
else if (gen_run) begin
if (rom_cmd[0] || (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
rom_cmd[1]? // activate
......@@ -304,7 +298,7 @@ module cmd_encod_tiled_wr #(
fifo_2regs #(
.WIDTH(COLADDR_NUMBER)
) fifo_2regs_i (
.rst (rst), // input
.mrst (rst), // input
.clk (clk), // input
.din (row_col_bank[COLADDR_NUMBER-1:0]), // input[15:0]
.wr(pre_act), // input
......
memctrl/ddr_refresh.v
View file @ b721ae66
......@@ -21,7 +21,7 @@
`timescale 1ns/1ps
module ddr_refresh(
input rst,
input mrst,
input clk,
input en,
input [7:0] refresh_period, // in 16*clk, 0 - disable refresh, turn off requests
......@@ -39,39 +39,39 @@ module ddr_refresh(
reg en_refresh;
reg en_r;
always @ (posedge rst or posedge clk) begin
if (rst) en_r <= 0;
always @ (posedge clk) begin
if (mrst) en_r <= 0;
else en_r <= en;
if (rst) en_refresh <= 0;
if (mrst) en_refresh <= 0;
else if (set) en_refresh <= (refresh_period != 0);
if (rst) pre_div <= 0;
if (mrst) pre_div <= 0;
else if (set || !en_refresh) pre_div <= 0;
else pre_div <= pre_div +1;
if (rst) cry <= 0;
if (mrst) cry <= 0;
else if (set) cry <= 0;
else cry <= (pre_div == 4'hf);
if (rst) period_cntr <= 0;
if (mrst) period_cntr <= 0;
else if (set) period_cntr <= 0;
else if (over) period_cntr <= refresh_period;
else if (cry) period_cntr <= period_cntr -1;
if (rst) refresh_due <= 0;
if (mrst) refresh_due <= 0;
else refresh_due <= over;
if (rst) pending_rq <= 0;
if (mrst) pending_rq <= 0;
else if (set) pending_rq <= 0;
else if ( refresh_due && !grant) pending_rq <= pending_rq+1;
else if (!refresh_due && grant) pending_rq <= pending_rq-1;
if (rst) want <= 0;
else want<= en_refresh && en_r && (pending_rq != 0);
if (mrst) want <= 0;
else want<= en_refresh && en_r && (pending_rq != 0);
if (rst) need <= 0;
else need <= en_refresh && en_r && (pending_rq[4:3] != 0);
if (mrst) need <= 0;
else need <= en_refresh && en_r && (pending_rq[4:3] != 0);
end
endmodule
memctrl/mcntrl393.v
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memctrl/mcntrl393_test01.v
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memctrl/mcntrl_linear_rw.v
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memctrl/mcntrl_ps_pio.v
View file @ b721ae66
......@@ -30,7 +30,7 @@ module mcntrl_ps_pio#(
parameter MCNTRL_PS_CMD= 'h1,
parameter MCNTRL_PS_STATUS_CNTRL= 'h2
)(
input rst,
input mrst,
input mclk,
// programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
......@@ -136,21 +136,23 @@ reg page_w_set_negedge;
assign set_status_w = cmd_we && (cmd_a== MCNTRL_PS_STATUS_CNTRL);
assign set_en_rst = cmd_we && (cmd_a== MCNTRL_PS_EN_RST);
//PAGE_CNTR_BITS
always @ (posedge rst or posedge mclk) begin
always @ (posedge mclk) begin
if (rst) pending_pages <= 0;
if (mrst) pending_pages <= 0;
else if (chn_rst) pending_pages <= 0;
else if ( cmd_set && !seq_done) pending_pages <= pending_pages + 1;
else if (!cmd_set && seq_done) pending_pages <= pending_pages - 1;
if (rst) nreset_page_fifo <= 0;
else nreset_page_fifo <= cmd_nempty | busy;
if (rst) cmd_wait_r <= 0;
if (mrst) nreset_page_fifo <= 0;
else nreset_page_fifo <= cmd_nempty | busy;
if (mrst) cmd_wait_r <= 0;
else if (channel_pgm_en) cmd_wait_r <= cmd_wait;
if (rst) en_reset <= 0;
if (mrst) en_reset <= 0;
else if (set_en_rst) en_reset <= cmd_data[1:0];
if (rst) begin
if (mrst) begin
want_rq <= 0;
need_rq <= 0;
end else if (chn_rst || channel_pgm_en) begin
......@@ -162,13 +164,12 @@ reg page_w_set_negedge;
end
if (rst) cmd_set <= 0;
if (mrst) cmd_set <= 0;
else if (chn_rst) cmd_set <= 0;
else cmd_set <= channel_pgm_en;
if (rst) cmd_set_d <= 0;
// else cmd_set_d <= {cmd_set_d[0],cmd_set& ~cmd_chn}; // only for channel0 (memory read)
if (mrst) cmd_set_d <= 0;
else cmd_set_d <= {cmd_set_d[0],cmd_set & ~cmd_wr}; // only for channel0 (memory read)
end
......@@ -180,36 +181,38 @@ reg page_w_set_negedge;
.ADDR_WIDTH (5),
.DATA_WIDTH (32)
) cmd_deser_mcontr_32bit_i (
.rst (rst), // input
.clk (mclk), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[15:0]
.data (cmd_data), // output[31:0]
.we (cmd_we) // output
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[15:0]
.data (cmd_data), // output[31:0]
.we (cmd_we) // output
);
status_generate #(
.STATUS_REG_ADDR (MCNTRL_PS_STATUS_REG_ADDR),
.PAYLOAD_BITS (2)
) status_generate_i (
.rst (rst), // input
.clk (mclk), // input
.we (set_status_w), // input
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (set_status_w), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_data), // input[25:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
.status (status_data), // input[25:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
);
fifo_same_clock #(
.DATA_WIDTH(CMD_WIDTH),
.DATA_DEPTH(CMD_FIFO_DEPTH)
) cmd_fifo_i (
.rst (rst),
.rst (1'b0),
.clk (mclk),
.sync_rst(chn_rst), // synchronously reset fifo;
.sync_rst (chn_rst), // synchronously reset fifo;
.we (set_cmd_w),
.re (cmd_set),
.data_in (cmd_data[CMD_WIDTH-1:0]),
......@@ -266,9 +269,9 @@ fifo_same_clock #(
.DATA_WIDTH(3),
.DATA_DEPTH(PAGE_FIFO_DEPTH)
) page_fifo1_i (
.rst (rst),
.rst (1'b0),
.clk (mclk), // posedge
.sync_rst (!nreset_page_fifo), // synchronously reset fifo;
.sync_rst (mrst || !nreset_page_fifo), // synchronously reset fifo;
.we (channel_pgm_en),
.re (buf_run),
.data_in ({cmd_wr,cmd_page}), //page),
......@@ -277,8 +280,8 @@ fifo_same_clock #(
.half_full ()
);
always @ (posedge rst or posedge mclk) begin
if (rst) page_out_r <= 0;
always @ (posedge mclk) begin
if (mrst) page_out_r <= 0;
else if (buf_run) page_out_r <= page_out;
......
memctrl/mcntrl_tiled_rw.v
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memctrl/memctrl16.v
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memctrl/phy/mcontr_sequencer.v
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memctrl/phy/phy_cmd.v
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memctrl/phy/phy_top.v
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memctrl/scheduler16.v
View file @ b721ae66
......@@ -24,7 +24,7 @@ module scheduler16 #(
parameter width=16, // counter number of bits
parameter n_chn=16 // number of channels
)(
input rst,
input mrst,
input clk,
input [n_chn-1:0] chn_en, // channel enable mask
input [n_chn-1:0] want_rq, // both want_rq and need_rq should go inactive after being granted
......@@ -60,8 +60,8 @@ module scheduler16 #(
generate
genvar i;
for (i=0;i<n_chn;i=i+1) begin: pri_reg_block
always @ (posedge rst or posedge clk) begin
if (rst) pri_reg[width*i +: width] <= 0;
always @ (posedge clk) begin
if (mrst) pri_reg[width*i +: width] <= 0;
else if (pgm_en && (pgm_addr==i)) pri_reg[width*i +: width] <= pgm_data;
end
end
......@@ -81,8 +81,8 @@ module scheduler16 #(
assign next_want_conf= (want_conf & want_rq & chn_en) | want_set;
assign next_need_conf= (need_conf & need_rq & chn_en) | need_set;
assign need_want_conf_w=need_some? next_need_conf: next_want_conf;
always @(posedge rst or posedge clk) begin
if (rst) begin
always @(posedge clk) begin
if (mrst) begin
want_conf <= 0;
need_conf <= 0;
end else begin
......@@ -126,8 +126,8 @@ module scheduler16 #(
.index (index[3:0]),
.valid (index_valid),
.need_out (need));
always @(posedge rst or posedge clk) begin
if (rst) begin
always @(posedge clk) begin
if (mrst) begin
grant_r <=0;
grant_sent <=0;
grant_chn_r <=0;
......
sensor/pxd_single.v
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sensor/sens_gamma.v
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sensor/sens_histogram.v
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sensor/sens_parallel12.v
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sensor/sens_sync.v
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sensor/sensor_channel.v
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sensor/sensor_fifo.v
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sensor/sensor_i2c.v
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......@@ -30,7 +30,7 @@ module sensor_i2c#(
parameter SENSI2C_STATUS = 'h1,
parameter SENSI2C_STATUS_REG = 'h30
)(
input rst,
input mrst, // @ posedge mclk
input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
......@@ -207,8 +207,9 @@ module sensor_i2c#(
.ADDR2 (SENSI2C_CTRL_ADDR),
.ADDR_MASK2 (SENSI2C_CTRL_MASK)
) cmd_deser_sens_i2c_i (
.rst (rst), // input
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (wa), // output[15:0]
......@@ -220,8 +221,9 @@ module sensor_i2c#(
.STATUS_REG_ADDR(SENSI2C_STATUS_REG),
.PAYLOAD_BITS(7) // STATUS_PAYLOAD_BITS)
) status_generate_sens_i2c_i (
.rst (rst), // input
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (set_status_w), // input
.wd (di[7:0]), // input[7:0]
.status ({busy, frame_num, sda_in, scl_in}), // input[25:0]
......
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status_read.v
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timing/rtc393.v
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timing/timestamp_fifo.v
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timing/timing393.v
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x393.v
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