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Commit b721ae66 authored by Andrey Filippov's avatar Andrey Filippov
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axi/axibram_read.v
View file @ b721ae66
......@@ -25,20 +25,16 @@ module axibram_read #(
parameter ADDRESS_BITS = 10 // number of memory address bits
)(
input aclk, // clock - should be buffered
// input aresetn, // reset, active low
input rst, // reset, active high
// input rst, // reset, active high
input arst, // @posedge aclk sync reset, active high
// AXI Read Address
input [31:0] araddr, // ARADDR[31:0], input
input arvalid, // ARVALID, input
output arready, // ARREADY, output
input [11:0] arid, // ARID[11:0], input
// input [ 1:0] arlock, // ARLOCK[1:0], input
// input [ 3:0] archache,// ARCACHE[3:0], input
// input [ 2:0] arprot, // ARPROT[2:0], input
input [ 3:0] arlen, // ARLEN[3:0], input
input [ 1:0] arsize, // ARSIZE[1:0], input
input [ 1:0] arburst, // ARBURST[1:0], input
// input [ 3:0] adqos, // ARQOS[3:0], input
// AXI Read Data
output [31:0] rdata, // RDATA[31:0], output
output reg rvalid, // RVALID, output
......@@ -145,30 +141,30 @@ module axibram_read #(
assign rdata[31:0] = bram_rdata; // data out
always @ (posedge aclk or posedge rst) begin
always @ (posedge aclk) begin
`ifdef USE_SHORT_REN_REGEN
if (rst) bram_regen_r <= 0;
if (arst) bram_regen_r <= 0;
else bram_regen_r <= bram_ren;
`endif
if (rst) pre_last_in_burst_r <= 0;
if (arst) pre_last_in_burst_r <= 0;
// else if (start_read_burst_w) pre_last_in_burst_r <= (read_left==4'b0);
else if (bram_reg_re_w) pre_last_in_burst_r <= (read_left==4'b0);
if (rst) rburst[1:0] <= 0;
if (arst) rburst[1:0] <= 0;
else if (start_read_burst_w) rburst[1:0] <= arburst_out[1:0];
if (rst) rlen[3:0] <= 0;
if (arst) rlen[3:0] <= 0;
else if (start_read_burst_w) rlen[3:0] <= arlen_out[3:0];
if (rst) read_in_progress <= 0;
if (arst) read_in_progress <= 0;
else read_in_progress <= read_in_progress_w;
if (rst) read_in_progress_d <= 0;
if (arst) read_in_progress_d <= 0;
// else read_in_progress_d <= read_in_progress_d_w;
else if (bram_reg_re_w) read_in_progress_d <= read_in_progress_d_w;
if (rst) read_in_progress_or <= 0;
if (arst) read_in_progress_or <= 0;
// else read_in_progress_or <= read_in_progress_d_w || read_in_progress_w;
// else if (bram_reg_re_w) read_in_progress_or <= read_in_progress_d_w || read_in_progress_w;
// FIXME:
......@@ -177,22 +173,23 @@ module axibram_read #(
// reg read_in_progress_d=0; // delayed by one active cycle (not skipped)
// reg read_in_progress_or=0; // read_in_progress || read_in_progress_d
if (rst) read_left <= 0;
if (arst) read_left <= 0;
else if (start_read_burst_w) read_left <= arlen_out[3:0]; // precedence over inc
else if (bram_reg_re_w) read_left <= read_left-1; //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target.
if (rst) read_address <= {ADDRESS_BITS{1'b0}};
if (arst) read_address <= {ADDRESS_BITS{1'b0}};
else if (start_read_burst_w) read_address <= araddr_out[ADDRESS_BITS-1:0]; // precedence over inc
else if (bram_reg_re_w) read_address <= next_rd_address_w;
if (rst) rvalid <= 1'b0;
if (arst) rvalid <= 1'b0;
else if (bram_reg_re_w && read_in_progress_d) rvalid <= 1'b1;
else if (rready) rvalid <= 1'b0;
if (rst) rlast <= 1'b0;
if (arst) rlast <= 1'b0;
else if (last_in_burst_d_w) rlast <= 1'b1;
else if (rready) rlast <= 1'b0;
end
always @ (posedge aclk) begin //SuppressThisWarning ISExst Assignment to bram_reg_re_0 ignored, since the identifier is never used
// bram_reg_re_0 <= read_in_progress_w && !pre_rvalid_w;
......@@ -240,9 +237,9 @@ module axibram_read #(
fifo_same_clock #( .DATA_WIDTH(ADDRESS_BITS+20),.DATA_DEPTH(4))
raddr_i (
.rst(rst),
.rst(1'b0),
.clk(aclk),
.sync_rst(1'b0), // input
.sync_rst(arst),
.we(arvalid && arready),
.re(start_read_burst_w),
.data_in({arid[11:0], arburst[1:0],arsize[1:0],arlen[3:0],araddr[ADDRESS_BITS+1:2]}),
......
axi/axibram_write.v
View file @ b721ae66
......@@ -26,21 +26,16 @@ module axibram_write #(
parameter ADDRESS_BITS = 10 // number of memory address bits
)(
input aclk, // clock - should be buffered
// input aresetn, // reset, active low
input rst, // reset, active highw
input arst, // @aclk sync reset, active high
// AXI Write Address
input [31:0] awaddr, // AWADDR[31:0], input
input awvalid, // AWVALID, input
output awready, // AWREADY, output
input [11:0] awid, // AWID[11:0], input
// input [ 1:0] awlock, // AWLOCK[1:0], input
// input [ 3:0] awcache, // AWCACHE[3:0], input
// input [ 2:0] awprot, // AWPROT[2:0], input
input [ 3:0] awlen, // AWLEN[3:0], input
input [ 1:0] awsize, // AWSIZE[1:0], input
input [ 1:0] awburst, // AWBURST[1:0], input
// input [ 3:0] awqos, // AWQOS[3:0], input
// AXI PS Master GP0: Write Data
input [31:0] wdata, // WDATA[31:0], input
input wvalid, // WVALID, input
......@@ -141,44 +136,30 @@ module axibram_write #(
assign start_write_burst_w=w_nempty_ready && aw_nempty_ready && (!write_in_progress || (w_nempty_ready && ((write_left[3:0]==4'b0) || wlast_out)));
assign write_in_progress_w=w_nempty_ready && aw_nempty_ready || (write_in_progress && !(w_nempty_ready && ((write_left[3:0]==4'b0) || wlast_out)));
always @ (posedge aclk or posedge rst) begin
if (rst) wburst[1:0] <= 0;
always @ (posedge aclk) begin
if (arst) wburst[1:0] <= 0;
else if (start_write_burst_w) wburst[1:0] <= awburst_out[1:0];
if (rst) wlen[3:0] <= 0;
if (arst) wlen[3:0] <= 0;
else if (start_write_burst_w) wlen[3:0] <= awlen_out[3:0];
if (rst) write_in_progress <= 0;
else write_in_progress <= write_in_progress_w;
if (arst) write_in_progress <= 0;
else write_in_progress <= write_in_progress_w;
if (rst) write_left <= 0;
if (arst) write_left <= 0;
else if (start_write_burst_w) write_left <= awlen_out[3:0]; // precedence over inc
else if (bram_we_w) write_left <= write_left-1; //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target.
if (rst) write_address <= {ADDRESS_BITS{1'b0}};
if (arst) write_address <= {ADDRESS_BITS{1'b0}};
else if (start_write_burst_w) write_address <= awaddr_out[ADDRESS_BITS-1:0]; // precedence over inc
else if (bram_we_w) write_address <= next_wr_address_w;
if (rst) dev_ready_r <= 1'b0;
else dev_ready_r <= dev_ready;
if (arst) dev_ready_r <= 1'b0;
else dev_ready_r <= dev_ready;
end
// **** Write response channel ****
wire [ 1:0] bresp_in;
assign bresp_in=2'b0;
/*
output bvalid, // BVALID, output
input bready, // BREADY, input
output [11:0] bid, // BID[11:0], output
output [ 1:0] bresp // BRESP[1:0], output
*/
/*
reg bram_reg_re_r;
always @ (posedge aclk) begin
bram_reg_re_r <= bram_reg_re_w;
end
*/
// external memory interface (write only)
assign pre_awaddr=awaddr_out[ADDRESS_BITS-1:0];
......@@ -199,9 +180,9 @@ module axibram_write #(
`endif
fifo_same_clock #( .DATA_WIDTH(20+ADDRESS_BITS),.DATA_DEPTH(4))
waddr_i (
.rst (rst),
.rst (1'b0), //rst),
.clk (aclk),
.sync_rst (1'b0),
.sync_rst (arst),
.we (awvalid && awready),
.re (start_write_burst_w),
.data_in ({awid[11:0], awburst[1:0],awsize[1:0],awlen[3:0],awaddr[ADDRESS_BITS+1:2]}),
......@@ -219,9 +200,9 @@ fifo_same_clock #( .DATA_WIDTH(20+ADDRESS_BITS),.DATA_DEPTH(4))
);
fifo_same_clock #( .DATA_WIDTH(49),.DATA_DEPTH(4))
wdata_i (
.rst(rst),
.rst(1'b0), //rst),
.clk(aclk),
.sync_rst (1'b0),
.sync_rst (arst),
.we(wvalid && wready),
.re(bram_we_w), //start_write_burst_w), // wrong
.data_in({wid[11:0],wlast,wstb[3:0],wdata[31:0]}),
......@@ -241,16 +222,16 @@ fifo_same_clock #( .DATA_WIDTH(49),.DATA_DEPTH(4))
reg was_bresp_re=0;
wire bresp_re;
assign bresp_re=bready && bvalid && !was_bresp_re;
always @ (posedge rst or posedge aclk) begin
if (rst) was_bresp_re<=0;
else was_bresp_re <= bresp_re;
always @ (posedge aclk) begin
if (arst) was_bresp_re<=0;
else was_bresp_re <= bresp_re;
end
fifo_same_clock #( .DATA_WIDTH(14),.DATA_DEPTH(4))
wresp_i (
.rst(rst),
.rst(1'b0), //rst),
.clk(aclk),
.sync_rst (1'b0),
.sync_rst (arst),
.we(bram_we_w &&((write_left[3:0]==4'b0) || wlast_out)), // added ((write_left[3:0]==4'b0) || wlast_out) - only last wrtite -> bresp
// .re(bready && bvalid),
.re(bresp_re), // not allowing RE next cycle after bvalid
......
axi/cmprs_afi_mux.v
View file @ b721ae66
......@@ -34,9 +34,11 @@ module cmprs_afi_mux#(
parameter CMPRS_AFIMUX_CYCBITS = 3,
parameter AFI_MUX_BUF_LATENCY = 2 // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
)(
input rst,
// input rst,
input mclk, // for command/status
input hclk, // global clock to run axi_hp @ 150MHz, shared by all compressor channels
input mrst, // @posedge mclk, sync reset
input hrst, // @posedge xclk, sync reset
// programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
......@@ -386,8 +388,9 @@ module cmprs_afi_mux#(
.ADDR_WIDTH (4),
.DATA_WIDTH (32)
) cmd_deser_32bit_i (
.rst (rst), // input
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[3:0]
......@@ -436,9 +439,11 @@ module cmprs_afi_mux#(
.CMPRS_AFIMUX_WIDTH(CMPRS_AFIMUX_WIDTH),
.CMPRS_AFIMUX_CYCBITS(CMPRS_AFIMUX_CYCBITS)
) cmprs_afi_mux_status_i (
.rst (rst), // input
// .rst (rst), // input
.hclk (hclk), // input
.mclk (mclk), // input
.mrst (mrst), // input
.hrst (hrst), // input
.cmd_data (cmd_data[15:0]), // input[15:0]
.cmd_a (cmd_a[1:0]), // input[1:0]
.status_we (cmd_we_status_w), // input
......
axi/cmprs_afi_mux_status.v
View file @ b721ae66
......@@ -29,9 +29,11 @@ module cmprs_afi_mux_status #(
parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26)
parameter CMPRS_AFIMUX_CYCBITS = 3
) (
input rst,
// input rst,
input hclk, // global clock to run axi_hp @ 150MHz, shared by all compressor channels
input mclk, // for command/status
input mrst, // @posedge mclk, sync reset
input hrst, // @posedge xclk, sync reset
// mclk domain
input [15:0] cmd_data, //
input [ 1:0] cmd_a, //
......@@ -100,11 +102,12 @@ module cmprs_afi_mux_status #(
end
pulse_cross_clock mode_we_hclk_i (.rst(rst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(mode_we), .out_pulse(mode_we_hclk),.busy());
pulse_cross_clock stb_mclk_i (.rst(rst), .src_clk(hclk), .dst_clk(mclk), .in_pulse(stb_r), .out_pulse(stb_mclk), .busy());
pulse_cross_clock mode_we_hclk_i (.rst(mrst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(mode_we), .out_pulse(mode_we_hclk),.busy());
pulse_cross_clock stb_mclk_i (.rst(hrst), .src_clk(hclk), .dst_clk(mclk), .in_pulse(stb_r), .out_pulse(stb_mclk), .busy());
status_router4 status_router4_i (
.rst (rst), // input
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.db_in0 (ad[0 * 8 +: 8]), // input[7:0]
.rq_in0 (rq[0]), // input
.start_in0 (start[0]), // output
......@@ -127,8 +130,9 @@ module cmprs_afi_mux_status #(
.STATUS_REG_ADDR (CMPRS_AFIMUX_STATUS_REG_ADDR+0),
.PAYLOAD_BITS (CMPRS_AFIMUX_WIDTH)
) status_generate0_i (
.rst (rst), // input
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (status_we && (cmd_a==0)), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_data[0 * CMPRS_AFIMUX_WIDTH +: CMPRS_AFIMUX_WIDTH]), // input[25:0]
......@@ -141,8 +145,9 @@ module cmprs_afi_mux_status #(
.STATUS_REG_ADDR (CMPRS_AFIMUX_STATUS_REG_ADDR+0),
.PAYLOAD_BITS (CMPRS_AFIMUX_WIDTH)
) status_generate1_i (
.rst (rst), // input
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (status_we && (cmd_a==1)), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_data[1 * CMPRS_AFIMUX_WIDTH +: CMPRS_AFIMUX_WIDTH]), // input[25:0]
......@@ -155,8 +160,9 @@ module cmprs_afi_mux_status #(
.STATUS_REG_ADDR (CMPRS_AFIMUX_STATUS_REG_ADDR+0),
.PAYLOAD_BITS (CMPRS_AFIMUX_WIDTH)
) status_generate2_i (
.rst (rst), // input
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (status_we && (cmd_a==2)), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_data[2 * CMPRS_AFIMUX_WIDTH +: CMPRS_AFIMUX_WIDTH]), // input[25:0]
......@@ -169,8 +175,9 @@ module cmprs_afi_mux_status #(
.STATUS_REG_ADDR (CMPRS_AFIMUX_STATUS_REG_ADDR+0),
.PAYLOAD_BITS (CMPRS_AFIMUX_WIDTH)
) status_generate3_i (
.rst (rst), // input
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (status_we && (cmd_a==3)), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_data[3 * CMPRS_AFIMUX_WIDTH +: CMPRS_AFIMUX_WIDTH]), // input[25:0]
......
axi/histogram_saxi.v
View file @ b721ae66
......@@ -37,9 +37,12 @@ module histogram_saxi#(
// parameter HIST_SAXI_STATUS_REG = 'h34,
parameter NUM_FRAME_BITS = 4 // number of bits use for frame number
)(
input rst,
// input rst,
input mclk, // for command/status
input aclk, // global clock to run s_axi (@150MHz?)
input mrst, // @posedge mclk, sync reset
input arst, // @posedge aclk, sync reset
// sensor 0, data valid @posedge mclk
input [NUM_FRAME_BITS-1:0] frame0, // frame number for which the histogram is provided
input hist_request0, // request to transfer a burst
......@@ -248,8 +251,8 @@ module histogram_saxi#(
assign page_sent_aclk = block_run[1] && !block_run[0];
// command interface
always @(posedge rst or posedge mclk) begin
if (rst) mode <= 0;
always @(posedge mclk) begin
if (mrst) mode <= 0;
else if (we_mode) mode <= cmd_data[HIST_SAXI_MODE_WIDTH-1:0];
end
always @(posedge mclk) begin
......@@ -357,7 +360,7 @@ module histogram_saxi#(
pulse_cross_clock pulse_cross_clock_page_sent_i (
.rst (rst), // input
.rst (arst), // input
.src_clk (aclk), // input
.dst_clk (mclk), // input
.in_pulse (page_sent_aclk), // input
......@@ -365,7 +368,7 @@ module histogram_saxi#(
.busy() // output
);
pulse_cross_clock pulse_cross_clock_page_written_aclk_i (
.rst (rst), // input
.rst (mrst), // input
.src_clk (mclk), // input
.dst_clk (aclk), // input
.in_pulse (burst_done_w), // input
......@@ -384,12 +387,13 @@ module histogram_saxi#(
.ADDR2 (0),
.ADDR_MASK2 (0)
) cmd_deser_sens_i2c_i (
.rst (rst), // input
.clk (mclk), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_wa), // output[3:0]
.data (cmd_data), // output[31:0]
.rst (1'b0), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_wa), // output[3:0]
.data (cmd_data), // output[31:0]
.we ({we_mode,we_addr}) // output
);
......@@ -399,31 +403,32 @@ module histogram_saxi#(
.LOG2WIDTH_RD(5),
.DUMMY(0)
) ram_var_w_var_r_i (
.rclk (aclk), // input
.raddr ({page_rd[1:0],page_ra[7:0]}), // input[9:0]
.ren (buf_re[0]), // input
.regen (buf_re[1]), // input
.data_out (inter_buf_data), // output[31:0]
.wclk (mclk), // input
.rclk (aclk), // input
.raddr ({page_rd[1:0],page_ra[7:0]}), // input[9:0]
.ren (buf_re[0]), // input
.regen (buf_re[1]), // input
.data_out (inter_buf_data), // output[31:0]
.wclk (mclk), // input
.waddr ({page_wr[1:0], page_wa[7:0]}), // input[9:0]
.we (dav_r), // input
.web (8'hff), // input[7:0]
.data_in (din_r) // input[31:0]
.we (dav_r), // input
.web (8'hff), // input[7:0]
.data_in (din_r) // input[31:0]
);
// Small extra FIFO to tolerate ram_var_w_var_r latency
fifo_same_clock #(
.DATA_WIDTH(32),
.DATA_DEPTH(4)
) fifo_same_clock_i (
.rst (rst), // input
.clk (aclk), // input
.sync_rst (!en_aclk), // input
.we (buf_re[2]), // input
.re (fifo_re), // input
.rst (1'b0), // input
.clk (aclk), // input
.sync_rst (arst), // input
.sync_rst (!en_aclk), // input
.we (buf_re[2]), // input
.re (fifo_re), // input
.data_in (inter_buf_data), // input[31:0]
.data_out (saxi_wdata), // output[31:0]
.nempty (fifo_nempty), // output
.half_full (fifo_half_full) // output reg
.data_out (saxi_wdata), // output[31:0]
.nempty (fifo_nempty), // output
.half_full (fifo_half_full) // output reg
);
endmodule
axi/membridge.v
View file @ b721ae66
......@@ -37,9 +37,12 @@ module membridge#(
// ,parameter MCNTRL_SCANLINE_FRAME_PAGE_RESET= 1'b0 // reset internal page number to zero at the frame start (false - only when hard/soft reset)
)(
input rst,
input mclk, // for command/status
input hclk, // global clock to run axi_hp @ 150MHz
// input rst,
input mrst, // @posedge mclk - sync reset
input hrst, // @posedge hclk - sync reset
input mclk, // for command/status
input hclk, // global clock to run axi_hp @ 150MHz
// programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
......@@ -208,24 +211,24 @@ module membridge#(
width64_minus1_mclk <= width64_mclk-1;
end
always @ (posedge mclk or posedge rst) begin
if (rst) rdwr_en_mclk <= 0;
always @ (posedge mclk) begin
if (mrst) rdwr_en_mclk <= 0;
else if (set_ctrl_w) rdwr_en_mclk <= cmd_data[0];
if (rst) start_mclk <= 0;
else start_mclk <= set_ctrl_w & cmd_data[1];
if (mrst) start_mclk <= 0;
else start_mclk <= set_ctrl_w & cmd_data[1];
if (rst) mode_reg_mclk <= 5'h03;
if (mrst) mode_reg_mclk <= 5'h03;
else if (set_mode_w) mode_reg_mclk <= cmd_data[4:0];
`ifdef MEMBRIDGE_DEBUG_READ
if (rst) debug_aw_mclk <= 0;
if (mrst) debug_aw_mclk <= 0;
else debug_aw_mclk <= set_ctrl_w & cmd_data[2];
if (rst) debug_w_mclk <= 0;
if (mrst) debug_w_mclk <= 0;
else debug_w_mclk <= set_ctrl_w & cmd_data[3];
if (rst) debug_disable_set_mclk <= 0;
if (mrst) debug_disable_set_mclk <= 0;
else debug_disable_set_mclk <= set_ctrl_w & cmd_data[4];
......@@ -286,48 +289,50 @@ module membridge#(
last_addr1k <= size64[28:4] - 1;
end
always @ (posedge hclk or posedge rst) begin
if (rst) rdwr_en <= 0;
else rdwr_en <= rdwr_en_mclk;
always @ (posedge hclk) begin
if (hrst) rdwr_en <= 0;
else rdwr_en <= rdwr_en_mclk;
if (rst) rdwr_start <= 0;
else rdwr_start <= {rdwr_start[1:0],start_hclk};
if (hrst) rdwr_start <= 0;
else rdwr_start <= {rdwr_start[1:0],start_hclk};
if (rst) rd_start <= 0;
else rd_start <= rdwr_start[2] && !wr_mode; // later to enable adders+ to propagate
if (hrst) rd_start <= 0;
else rd_start <= rdwr_start[2] && !wr_mode; // later to enable adders+ to propagate
if (rst) wr_start <= 0;
else wr_start <= rdwr_start[2] && wr_mode;
if (hrst) wr_start <= 0;
else wr_start <= rdwr_start[2] && wr_mode;
page_ready_rd <= page_ready && !wr_mode;
if (rst) rd_id <= 0;
if (hrst) rd_id <= 0;
else if (rd_start) rd_id <= rd_id +1;
if (rst) wr_id <= 0;
if (hrst) wr_id <= 0;
else if (wr_start) wr_id <= wr_id +1;
end
// mclk -> hclk
pulse_cross_clock start_i (.rst(rst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(start_mclk), .out_pulse(start_hclk),.busy());
pulse_cross_clock page_ready_i (.rst(rst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(page_ready_chn), .out_pulse(page_ready),.busy());
pulse_cross_clock frame_done_i (.rst(rst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(frame_done_chn), .out_pulse(frame_done),.busy());
pulse_cross_clock reset_page_wr_i (.rst(rst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(xfer_reset_page_wr), .out_pulse(reset_page_wr),.busy());
pulse_cross_clock start_i (.rst(mrst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(start_mclk), .out_pulse(start_hclk),.busy());
pulse_cross_clock page_ready_i (.rst(mrst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(page_ready_chn), .out_pulse(page_ready),.busy());
pulse_cross_clock frame_done_i (.rst(mrst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(frame_done_chn), .out_pulse(frame_done),.busy());
pulse_cross_clock reset_page_wr_i (.rst(mrst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(xfer_reset_page_wr), .out_pulse(reset_page_wr),.busy());
`ifdef MEMBRIDGE_DEBUG_READ
// mclk -> hclk, debug-only
pulse_cross_clock debug_aw_i (.rst(rst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(debug_aw_mclk), .out_pulse(debug_aw),.busy());
pulse_cross_clock debug_w_i (.rst(rst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(debug_w_mclk), .out_pulse(debug_w), .busy());
pulse_cross_clock debug_disable_set_i(.rst(rst),.src_clk(mclk),.dst_clk(hclk), .in_pulse(debug_disable_set_mclk),.out_pulse(debug_disable_set), .busy());
pulse_cross_clock debug_aw_i (.rst(hrst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(debug_aw_mclk), .out_pulse(debug_aw),.busy());
pulse_cross_clock debug_w_i (.rst(hrst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(debug_w_mclk), .out_pulse(debug_w), .busy());
pulse_cross_clock debug_disable_set_i(.rst(hrst),.src_clk(mclk),.dst_clk(hclk), .in_pulse(debug_disable_set_mclk),.out_pulse(debug_disable_set), .busy());
`endif
// negedge mclk -> hclk (verify clock inversion is absorbed)
pulse_cross_clock reset_page_rd_i (.rst(rst), .src_clk(~mclk),.dst_clk(hclk), .in_pulse(xfer_reset_page_rd), .out_pulse(reset_page_rd),.busy());
reg mrstn = 1;
always @ (negedge mclk) mrstn <= mrst;
pulse_cross_clock reset_page_rd_i (.rst(mrstn), .src_clk(~mclk),.dst_clk(hclk), .in_pulse(xfer_reset_page_rd), .out_pulse(reset_page_rd),.busy());
// hclk -> mclk
pulse_cross_clock next_page_i (.rst(rst), .src_clk(hclk), .dst_clk(mclk), .in_pulse(next_page), .out_pulse(next_page_chn),.busy(busy_next_page));
pulse_cross_clock next_page_i (.rst(hrst), .src_clk(hclk), .dst_clk(mclk), .in_pulse(next_page), .out_pulse(next_page_chn),.busy(busy_next_page));
// Common to both directions
localparam DELAY_ADVANCE_ADDR=3;
......@@ -359,10 +364,9 @@ module membridge#(
assign afi_araddr={axi_addr64,3'b0};
assign left_zero = low4_zero && last_burst;
always @ (posedge hclk or posedge rst) begin
if (rst) advance_rel_addr_d <= 0;
// else if (advance_rel_addr_w) advance_rel_addr_d <= {DELAY_ADVANCE_ADDR{1'b1}};
else advance_rel_addr_d <= {advance_rel_addr_d[DELAY_ADVANCE_ADDR-2:0],advance_rel_addr};
always @ (posedge hclk) begin
if (hrst) advance_rel_addr_d <= 0;
else advance_rel_addr_d <= {advance_rel_addr_d[DELAY_ADVANCE_ADDR-2:0],advance_rel_addr};
end
......@@ -441,31 +445,31 @@ module membridge#(
`endif
assign afi_awvalid=advance_rel_addr && read_started;
always @ (posedge hclk or posedge rst) begin
if (rst) read_busy <= 0;
always @ (posedge hclk) begin
if (hrst) read_busy <= 0;
else if (rd_start) read_busy <= 1;
else if (read_over) read_busy <= 0;
if (rst) read_started <= 0;
if (hrst) read_started <= 0;
else if (!read_busy) read_started <= 0;
else if (wr_mode) read_started <= 0; // just debugging, making sure read is disabled in write mode
else if (page_ready) read_started <= 1; // first page is in the buffer - use it to mask page number comparison
`ifdef MEMBRIDGE_DEBUG_READ
if (rst) debug_aw_allowed <= 0;
if (hrst) debug_aw_allowed <= 0;
else if (!read_busy) debug_aw_allowed <= 0;
else if ( debug_aw && !afi_awvalid) debug_aw_allowed <= debug_aw_allowed + 1;
else if (!debug_aw && afi_awvalid) debug_aw_allowed <= debug_aw_allowed - 1;
if (rst) debug_w_allowed <= 0;
if (hrst) debug_w_allowed <= 0;
else if (!read_busy) debug_w_allowed <= 0;
else if ( debug_w && !(afi_wvalid && afi_wlast)) debug_w_allowed <= debug_w_allowed + 1;
else if (!debug_w && (afi_wvalid && afi_wlast)) debug_w_allowed <= debug_w_allowed - 1;
if (rst) debug_disable <= 0;
if (hrst) debug_disable <= 0;
else if (!read_busy) debug_disable <= 0;
else if (debug_disable_set) debug_disable <= 1;
`endif
......@@ -473,36 +477,34 @@ module membridge#(
afi_bvalid_r <=afi_bvalid;
if (rst) wresp_conf <= 0;
if (hrst) wresp_conf <= 0;
else if (!read_busy) wresp_conf <= 0;
else if (afi_bvalid_r) wresp_conf <= wresp_conf +1;
read_over <= left_zero && (axi_wr_pending == 0) && read_started;
// read_over <= ((left_zero && (axi_wr_pending == 0)) || frame_done) && read_started ; // WRONG, just for debugging
// else if (frame_done) read_busy <= 0;
if (rst) read_page <= 0;
if (hrst) read_page <= 0;
else if (reset_page_rd) read_page <= 0;
else if (next_page_rd_w) read_page <= read_page + 1;
if (rst) read_pages_ready <= 0;
if (hrst) read_pages_ready <= 0;
else if (!read_busy) read_pages_ready <= 0;
else if ( page_ready_rd && !next_page_rd_w) read_pages_ready <= read_pages_ready +1;
else if (!page_ready_rd && next_page_rd_w) read_pages_ready <= read_pages_ready -1;
if (rst) afi_wd_safe_not_full <= 0;
else afi_wd_safe_not_full <= rdwr_en && (!afi_wcount[7] && !(&afi_wcount[6:3]));
if (hrst) afi_wd_safe_not_full <= 0;
else afi_wd_safe_not_full <= rdwr_en && (!afi_wcount[7] && !(&afi_wcount[6:3]));
if (rst) afi_wa_safe_not_full <= 0;
else afi_wa_safe_not_full <= rdwr_en && (!afi_wacount[5] && !(&afi_wacount[4:2]));
if (hrst) afi_wa_safe_not_full <= 0;
else afi_wa_safe_not_full <= rdwr_en && (!afi_wacount[5] && !(&afi_wacount[4:2]));
if (rst) busy <= 0;
else busy <= read_busy || write_busy;
if (hrst) busy <= 0;
else busy <= read_busy || write_busy;
if (rst) pre_done <= 0; // delay done to turn on same time busy is off
if (hrst) pre_done <= 0; // delay done to turn on same time busy is off
else pre_done <= (write_busy && frame_done) || (read_busy && read_over);
if (rst) done <= 0;
if (hrst) done <= 0;
else if (!rdwr_en) done <= 0; // disabling when idle will reset done
else if (pre_done) done <= 1;
else if (rdwr_start) done <= 0;
......@@ -586,43 +588,43 @@ module membridge#(
assign afi_rready = bufwr_we[0];
always @ (posedge hclk or posedge rst) begin
if (rst) write_busy <= 0;
always @ (posedge hclk) begin
if (hrst) write_busy <= 0;
else if (wr_start) write_busy <= 1;
else if (!wr_mode) write_busy <= 0; // Just debugging, making sure write mode is disabled in read mode
else if (frame_done) write_busy <= 0;
if (rst) axi_arw_requested <= 0;
if (hrst) axi_arw_requested <= 0;
else if (!write_busy && !read_started) axi_arw_requested <= 0;
else if (advance_rel_addr) axi_arw_requested <= axi_arw_requested + afi_len_plus1;
if (rst) axi_bursts_requested <= 0;
if (hrst) axi_bursts_requested <= 0;
else if (!write_busy && !read_started) axi_bursts_requested <= 0;
else if (advance_rel_addr) axi_bursts_requested <= axi_bursts_requested + 1;
if (rst) axi_rd_received <= 0;
if (hrst) axi_rd_received <= 0;
else if (!write_busy) axi_rd_received <= 0;
else if (bufwr_we[0]) axi_rd_received <= axi_rd_received + 1;
if (rst) afi_rd_safe_not_empty <= 0;
if (hrst) afi_rd_safe_not_empty <= 0;
// allow 1 cycle latency, no continuous reads when FIFO is low (like in the very end of the transfer)
// Adjust '2' in afi_rcount[6:2] ?
else afi_rd_safe_not_empty <= rdwr_en && ( afi_rcount[7] || (|afi_rcount[6:SAFE_RD_BITS]) || (!(|bufwr_we) && !bufwr_we_w && afi_rvalid));
if (rst) afi_ra_safe_not_full <= 0;
else afi_ra_safe_not_full <= rdwr_en && ( !afi_racount[2] && !(&afi_racount[1:0]));
if (hrst) afi_ra_safe_not_full <= 0;
else afi_ra_safe_not_full <= rdwr_en && ( !afi_racount[2] && !(&afi_racount[1:0]));
if (rst) afi_safe_rd_pending <= 0;
if (hrst) afi_safe_rd_pending <= 0;
else if (!write_busy) afi_safe_rd_pending <= 0;
else afi_safe_rd_pending <= rdwr_en && ( !axi_rd_pending[7] && !(&axi_rd_pending[6:4]));
// handle buffer address, page
if (rst) write_page <= 0;
if (hrst) write_page <= 0;
else if (reset_page_wr) write_page <= 0;
else if (next_page_wr_w) write_page <= write_page + 1;
if (rst) write_pages_ready <= 0;
if (hrst) write_pages_ready <= 0;
else if (!write_busy) write_pages_ready <= 0;
else if ( page_ready_wr && !next_page_wr_w) write_pages_ready <= write_pages_ready -1; //+1;
else if (!page_ready_wr && next_page_wr_w) write_pages_ready <= write_pages_ready +1; //-1;
......@@ -643,13 +645,14 @@ module membridge#(
.ADDR_WIDTH (4),
.DATA_WIDTH (32)
) cmd_deser_32bit_i (
.rst (rst), // input
.clk (mclk), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[3:0]
.data (cmd_data), // output[31:0]
.we (cmd_we) // output
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[3:0]
.data (cmd_data), // output[31:0]
.we (cmd_we) // output
);
status_generate #(
......@@ -660,54 +663,54 @@ module membridge#(
.PAYLOAD_BITS (18) //2)
`endif
) status_generate_i (
.rst (rst), // input
.clk (mclk), // input
.we (set_status_w), // input
.wd (cmd_data[7:0]), // input[7:0]
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (set_status_w), // input
.wd (cmd_data[7:0]), // input[7:0]
`ifdef MEMBRIDGE_DEBUG_READ
.status ({debug_aw_allowed, debug_w_allowed, done, busy}), // input[25:0]
`else
// .status ({done,busy}), // input[25:0]
.status ({axi_arw_requested, wresp_conf, done, busy}), // input[25:0]
.status ({axi_arw_requested, wresp_conf, done, busy}), // input[25:0]
`endif
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
);
// Port 1rd (read DDR to AFI) buffer, linear
mcntrl_buf_rd #(
.LOG2WIDTH_RD(6) // 64 bit external interface
) chn1rd_buf_i (
.ext_clk (hclk), // input
.ext_clk (hclk), // input
.ext_raddr ({read_page,buf_in_line64[6:0]}), // input[8:0]
.ext_rd (bufrd_rd[0]), // input
.ext_regen (bufrd_rd[1]), // input
.ext_data_out (afi_wdata), // output[63:0]
.wclk (!mclk), // input
.wpage_in (2'b0), // input[1:0]
.wpage_set (xfer_reset_page_rd), // input TODO: Generate @ negedge mclk on frame start
.page_next (buf_wpage_nxt), // input
.page (), // output[1:0]
.we (buf_wr), // input
.data_in (buf_wdata) // input[63:0]
.ext_rd (bufrd_rd[0]), // input
.ext_regen (bufrd_rd[1]), // input
.ext_data_out (afi_wdata), // output[63:0]
.wclk (!mclk), // input
.wpage_in (2'b0), // input[1:0]
.wpage_set (xfer_reset_page_rd), // input TODO: Generate @ negedge mclk on frame start
.page_next (buf_wpage_nxt), // input
.page (), // output[1:0]
.we (buf_wr), // input
.data_in (buf_wdata) // input[63:0]
);
// Port 1wr (write DDR from AFI) buffer, linear
mcntrl_buf_wr #(
.LOG2WIDTH_WR(6) // 64 bit external interface
) chn1wr_buf_i (
.ext_clk (hclk), // input
.ext_clk (hclk), // input
.ext_waddr ({write_page_r, buf_in_line64_r[6:0]}), // input[8:0]
.ext_we (bufwr_we[1]), // input
.ext_data_in (rdata_r), //afi_rdata), // input[63:0] buf_wdata - from AXI
.rclk (mclk), // input
.rpage_in (2'b0), // input[1:0]
.rpage_set (xfer_reset_page_wr), // input @ posedge mclk
.page_next (buf_rpage_nxt), // input
.page (), // output[1:0]
.rd (buf_rd), // input
.data_out (buf_rdata) // output[63:0]
.ext_we (bufwr_we[1]), // input
.ext_data_in (rdata_r), //afi_rdata), // input[63:0] buf_wdata - from AXI
.rclk (mclk), // input
.rpage_in (2'b0), // input[1:0]
.rpage_set (xfer_reset_page_wr), // input @ posedge mclk
.page_next (buf_rpage_nxt), // input
.page (), // output[1:0]
.rd (buf_rd), // input
.data_out (buf_rdata) // output[63:0]
);
endmodule
......
axi/mult_saxi_wr.v
View file @ b721ae66
......@@ -39,9 +39,11 @@ module mult_saxi_wr #(
parameter MULT_SAXI_ADV_RD = 3 // number of clock cycles before end of write to genearte adv_wr_done
) (
input rst, // global reset
// input rst, // global reset
input mclk, // system clock
input aclk, // global clock to run s_axi (@150MHz?)
input mrst, // @mclk sync reset
input arst, // @aclk sync reset
// command interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
......@@ -161,8 +163,8 @@ module mult_saxi_wr #(
assign en_chn_mclk = mode_reg[3:0];
assign run_chn_mclk = mode_reg[7:4];
always @ (posedge rst or posedge mclk) begin
if (rst) mode_reg <= 0;
always @ (posedge mclk) begin
if (mrst) mode_reg <= 0;
else if (we_ctrl && !cmd_a[0]) mode_reg <= cmd_data[7:0];
end
......@@ -420,15 +422,15 @@ module mult_saxi_wr #(
.DATA_WIDTH(35),
.DATA_DEPTH(4)
) fifo_same_clock_i (
.rst (rst), // input
.clk (aclk), // input
.sync_rst (!en_aclk), // input
.we (buf_re[2]), // input
.re (fifo_re), // input
.rst (1'b0), // rst), // input
.clk (aclk), // input
.sync_rst (!en_aclk || arst), // input
.we (buf_re[2]), // input
.re (fifo_re), // input
.data_in ({chn_rd_data,is_last_rd[1],inter_buf_data}), // input[31:0]
.data_out ({chn_fifo_out,saxi_wlast, saxi_wdata}), // output[31:0]
.nempty (fifo_nempty), // output
.half_full (fifo_half_full) // output reg
.nempty (fifo_nempty), // output
.half_full (fifo_half_full) // output reg
);
generate
......@@ -481,8 +483,9 @@ module mult_saxi_wr #(
.ADDR2 (0),
.ADDR_MASK2 (0)
) cmd_deser_sens_i2c_i (
.rst (rst), // input
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[3:0]
......@@ -509,7 +512,7 @@ module mult_saxi_wr #(
if (pntr_we_mclk && (pntr_wa == 2'h3)) status_pntr3 <= pntr_wd;
end
pulse_cross_clock status_wr_i (.rst(rst), .src_clk(aclk), .dst_clk(mclk), .in_pulse(pntr_we), .out_pulse(pntr_we_mclk),.busy());
pulse_cross_clock status_wr_i (.rst(arst), .src_clk(aclk), .dst_clk(mclk), .in_pulse(pntr_we), .out_pulse(pntr_we_mclk),.busy());
status_generate #(
.STATUS_REG_ADDR (MULT_SAXI_STATUS_REG+4), // not used
......@@ -518,8 +521,9 @@ module mult_saxi_wr #(
.EXTRA_WORDS (4),
.EXTRA_REG_ADDR (MULT_SAXI_STATUS_REG)
) status_generate_i (
.rst (rst), // input
.clk (mclk), // input
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (we_ctrl && cmd_a[0]), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_data), // input[128:0]
......
cmd_mux.v
View file @ b721ae66
......@@ -61,7 +61,8 @@ module cmd_mux #(
) (
input axi_clk,
input mclk,
input rst,
input mrst, // @posedge mclk - sync reset
input arst, // @posedge axi_clk - sync reset
// direct commands from AXI. No wait but for multi-cycle output and command sequencer (having higher priority)
input [AXI_WR_ADDR_BITS-1:0] pre_waddr, // AXI write address, before actual writes (to generate busy), valid@start_burst
input start_wburst, // burst start - should generate ~ready (should be AND-ed with !busy internally)
......@@ -114,10 +115,10 @@ module cmd_mux #(
assign seq_length_rom_a=par_ad[NUM_CYCLES_LOW_BIT+:5];
assign ss= seq_length[3];
always @ (posedge axi_clk or posedge rst) begin
if (rst) selected <= 1'b0;
always @ (posedge axi_clk) begin
if (arst) selected <= 1'b0;
else if (start_wburst) selected <= selected_w;
if (rst) busy_r <= 1'b0;
if (arst) busy_r <= 1'b0;
else busy_r <= !fifo_half_empty;
end
......@@ -158,8 +159,8 @@ module cmd_mux #(
5'h1e:seq_length <= NUM_CYCLES_30;
5'h1f:seq_length <= NUM_CYCLES_31;
endcase
always @ (posedge rst or posedge mclk) begin
if (rst) seq_busy_r<=0;
always @ (posedge mclk) begin
if (mrst) seq_busy_r<=0;
else begin
if (ad_stb) begin
case (seq_length)
......@@ -177,9 +178,9 @@ module cmd_mux #(
assign can_start_w= ad_stb_r? ss: !seq_busy_r[1];
assign start_axi_w= can_start_w && ~cmdseq_full_r && fifo_nempty;
assign start_w= can_start_w && (cmdseq_full_r || fifo_nempty);
always @ (posedge rst or posedge mclk) begin
if (rst) ad_stb_r <= 0;
else ad_stb_r <= start_w;
always @ (posedge mclk) begin
if (mrst) ad_stb_r <= 0;
else ad_stb_r <= start_w;
end
always @ (posedge mclk) begin
if (start_w) par_ad <={cmdseq_full_r?cseq_wdata_r:wdata_fifo_out,{(16-AXI_WR_ADDR_BITS){1'b0}},cmdseq_full_r?cseq_waddr_r:waddr_fifo_out};
......@@ -188,8 +189,8 @@ module cmd_mux #(
assign cseq_ackn= cseq_wr_en && (!cmdseq_full_r || can_start_w); // cmddseq_full has priority over axi, so (can_start_w && cmdseq_full_r)
always @ (posedge rst or posedge mclk) begin
if (rst) cmdseq_full_r <= 0;
always @ (posedge mclk) begin
if (mrst) cmdseq_full_r <= 0;
else cmdseq_full_r <= cseq_ackn || (cmdseq_full_r && !can_start_w);
end
always @ (posedge mclk) begin
......@@ -204,7 +205,9 @@ module cmd_mux #(
.DATA_WIDTH (AXI_WR_ADDR_BITS+32),
.DATA_DEPTH (4)
) fifo_cross_clocks_i (
.rst (rst), // input
.rst (1'b0), // input
.rrst (mrst), // input
.wrst (arst), // input
.rclk (mclk), // input
.wclk (axi_clk), // input
.we (wr_en && selected), // input
......
cmd_readback.v
View file @ b721ae66
......@@ -30,7 +30,8 @@ module cmd_readback#(
parameter CONTROL_RBACK_ADDR = 'h0000, // AXI write address of control write registers
parameter CONTROL_RBACK_ADDR_MASK = 'h3800 // AXI write address of control registers
)(
input rst,
input mrst, // @posedge mclk - sync reset
input arst, // @posedge axi_clk - sync reset
input mclk,
input axi_clk,
input [AXI_WR_ADDR_BITS-1:0] par_waddr, // parallel address
......@@ -71,11 +72,11 @@ module cmd_readback#(
assign axird_selected = select_r;
always @ (posedge rst or posedge axi_clk) begin
if (rst) axird_regen <= 0;
else axird_regen <= axird_ren;
always @ (posedge axi_clk) begin
if (arst) axird_regen <= 0;
else axird_regen <= axird_ren;
if (rst) select_r <= 0;
if (arst) select_r <= 0;
else if (axird_start_burst) select_r <= select_w;
end
......@@ -85,9 +86,9 @@ module cmd_readback#(
select_d <= select_r;
end
always @ (posedge rst or posedge mclk) begin
if (rst) we <= 0;
else we <= we_w;
always @ (posedge mclk) begin
if (mrst) we <= 0;
else we <= we_w;
end
always @ (posedge mclk) begin
if (we_w) wdata <= par_data;
......
compressor_jp/cmprs_cmd_decode.v
View file @ b721ae66
......@@ -132,16 +132,16 @@ module cmprs_cmd_decode#(
parameter CMPRS_CSAT_CB_BITS = 10, // number of bits in blue scale field in color saturation word
parameter CMPRS_CSAT_CR = 12, // bit # of number of red scale field in color saturation word
parameter CMPRS_CSAT_CR_BITS = 10, // number of bits in red scale field in color saturation word
parameter CMPRS_CORING_BITS = 3, // number of bits in coring mode
parameter CMPRS_CORING_BITS = 3 // number of bits in coring mode
parameter CMPRS_STUFFER_NEG = 1 // stuffer runs @ negedge xclk2x
//parameter CMPRS_STUFFER_NEG = 1 // stuffer runs @ negedge xclk2x
)(
input rst,
// input rst,
input xclk, // global clock input, compressor single clock rate
// input xclk2x, // global clock input, compressor double clock rate, nominally rising edge aligned
input mclk, // global system/memory clock
input mrst, // @posedge mclk, sync reset
input ctrl_we, // input - @mclk control register write enable
input format_we, // input - @mclk write number of tiles and left margin
input color_sat_we, // input - @mclk write color saturation values
......@@ -236,57 +236,57 @@ module cmprs_cmd_decode#(
wire frame_start_xclk;
assign cmprs_en_mclk = cmprs_en_mclk_r;
always @ (posedge rst or posedge mclk) begin
if (rst) ctrl_we_r <= 0;
else ctrl_we_r <= ctrl_we;
always @ (posedge mclk) begin
if (mrst) ctrl_we_r <= 0;
else ctrl_we_r <= ctrl_we;
if (rst) format_we_r <= 0;
else format_we_r <= format_we;
if (mrst) format_we_r <= 0;
else format_we_r <= format_we;
if (rst) color_sat_we_r <= 0;
else color_sat_we_r <= color_sat_we;
if (mrst) color_sat_we_r <= 0;
else color_sat_we_r <= color_sat_we;
if (rst) coring_we_r <= 0;
else coring_we_r <= coring_we;
if (mrst) coring_we_r <= 0;
else coring_we_r <= coring_we;
if (rst) di_r <= 0;
if (mrst) di_r <= 0;
else if (ctrl_we || format_we || color_sat_we || coring_we) di_r <= di[30:0];
if (rst) cmprs_en_mclk_r <= 0;
if (mrst) cmprs_en_mclk_r <= 0;
else if (ctrl_we_r && di_r[CMPRS_CBIT_RUN]) cmprs_en_mclk_r <= (di_r[CMPRS_CBIT_RUN-1 -:CMPRS_CBIT_RUN_BITS] != CMPRS_CBIT_RUN_RST);
if (rst) cmprs_run_mclk <= 0;
if (mrst) cmprs_run_mclk <= 0;
else if (ctrl_we_r && di_r[CMPRS_CBIT_RUN]) cmprs_run_mclk <= (di_r[CMPRS_CBIT_RUN-1 -:CMPRS_CBIT_RUN_BITS] == CMPRS_CBIT_RUN_ENABLE);
if (rst) cmprs_standalone <= 0;
if (mrst) cmprs_standalone <= 0;
else if (ctrl_we_r) cmprs_standalone <= ctrl_we_r && di_r[CMPRS_CBIT_RUN] && (di_r[CMPRS_CBIT_RUN-1 -:CMPRS_CBIT_RUN_BITS] == CMPRS_CBIT_RUN_STANDALONE);
if (rst) sigle_frame_buf <= 0;
if (mrst) sigle_frame_buf <= 0;
else if (ctrl_we_r && di_r[CMPRS_CBIT_FRAMES]) sigle_frame_buf <= (di_r[CMPRS_CBIT_FRAMES-1 -:CMPRS_CBIT_FRAMES_BITS] == CMPRS_CBIT_FRAMES_SINGLE);
if (rst) cmprs_qpage_mclk <= 0;
if (mrst) cmprs_qpage_mclk <= 0;
else if (ctrl_we_r && di_r[CMPRS_CBIT_QBANK]) cmprs_qpage_mclk <= di_r[CMPRS_CBIT_QBANK-1 -:CMPRS_CBIT_QBANK_BITS];
if (rst) cmprs_dcsub_mclk <= 0;
if (mrst) cmprs_dcsub_mclk <= 0;
else if (ctrl_we_r && di_r[CMPRS_CBIT_DCSUB]) cmprs_dcsub_mclk <= di_r[CMPRS_CBIT_DCSUB-1 -:CMPRS_CBIT_DCSUB_BITS];
if (rst) cmprs_mode_mclk <= 0;
if (mrst) cmprs_mode_mclk <= 0;
else if (ctrl_we_r && di_r[CMPRS_CBIT_CMODE]) cmprs_mode_mclk <= di_r[CMPRS_CBIT_CMODE-1 -:CMPRS_CBIT_CMODE_BITS];
if (rst) cmprs_fmode_mclk <= 0;
if (mrst) cmprs_fmode_mclk <= 0;
else if (ctrl_we_r && di_r[CMPRS_CBIT_FOCUS]) cmprs_fmode_mclk <= di_r[CMPRS_CBIT_FOCUS-1 -:CMPRS_CBIT_FOCUS_BITS];
if (rst) bayer_shift_mclk <= 0;
if (mrst) bayer_shift_mclk <= 0;
else if (ctrl_we_r && di_r[CMPRS_CBIT_BAYER]) bayer_shift_mclk <= di_r[CMPRS_CBIT_BAYER-1 -:CMPRS_CBIT_BAYER_BITS];
if (rst) format_mclk <= 0;
if (mrst) format_mclk <= 0;
else if (format_we_r) format_mclk <= di_r[30:0];
if (rst) color_sat_mclk <= 0;
if (mrst) color_sat_mclk <= 0;
else if (color_sat_we_r) color_sat_mclk <= di_r[23:0];
if (rst) coring_mclk <= 0;
if (mrst) coring_mclk <= 0;
else if (coring_we_r) coring_mclk <= di_r[2:0];
end
......@@ -438,11 +438,11 @@ module cmprs_cmd_decode#(
end
//frame_start_xclk
pulse_cross_clock ctrl_we_xclk_i (.rst(rst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(ctrl_we_r), .out_pulse(ctrl_we_xclk),.busy());
pulse_cross_clock format_we_xclk_i (.rst(rst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(format_we_r), .out_pulse(format_we_xclk),.busy());
pulse_cross_clock color_sat_we_xclk_i (.rst(rst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(color_sat_we_r), .out_pulse(color_sat_we_xclk),.busy());
pulse_cross_clock coring__we_xclk_i (.rst(rst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(coring_we_r), .out_pulse(coring_we_xclk),.busy());
pulse_cross_clock ctrl_we_xclk_i (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(ctrl_we_r), .out_pulse(ctrl_we_xclk),.busy());
pulse_cross_clock format_we_xclk_i (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(format_we_r), .out_pulse(format_we_xclk),.busy());
pulse_cross_clock color_sat_we_xclk_i (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(color_sat_we_r), .out_pulse(color_sat_we_xclk),.busy());
pulse_cross_clock coring__we_xclk_i (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(coring_we_r), .out_pulse(coring_we_xclk),.busy());
pulse_cross_clock frame_start_xclk_i (.rst(rst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(frame_start), .out_pulse(frame_start_xclk),.busy());
pulse_cross_clock frame_start_xclk_i (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(frame_start), .out_pulse(frame_start_xclk),.busy());
endmodule
compressor_jp/cmprs_frame_sync.v
View file @ b721ae66
......@@ -27,10 +27,12 @@ module cmprs_frame_sync#(
parameter CMPRS_TIMEOUT= 1000 // mclk cycles
)(
input rst,
// input rst,
input xclk, // global clock input, compressor single clock rate
// input xclk2x, // global clock input, compressor double clock rate, nominally rising edge aligned
input mclk, // global system/memory clock
input mrst, // @posedge mclk, sync reset
input xrst, // @posedge xclk, sync reset
input cmprs_en, // @mclk 0 resets immediately
output cmprs_en_extend, // @mclk keep compressor enabled for graceful shutdown
......@@ -90,9 +92,9 @@ module cmprs_frame_sync#(
assign stuffer_running_mclk = stuffer_running_mclk_r;
assign reading_frame = reading_frame_r;
always @ (posedge rst or posedge mclk) begin
if (rst) cmprs_en_extend_r <= 0;
else if (cmprs_en) cmprs_en_extend_r <= 1;
always @ (posedge mclk) begin
if (mrst) cmprs_en_extend_r <= 0;
else if (cmprs_en) cmprs_en_extend_r <= 1;
else if ((timeout == 0) || !stuffer_running_mclk_r) cmprs_en_extend_r <= 0;
end
......@@ -132,8 +134,8 @@ module cmprs_frame_sync#(
end
pulse_cross_clock vsync_late_mclk_i (.rst(rst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(vsync_late), .out_pulse(vsync_late_mclk),.busy());
pulse_cross_clock frame_started_i (.rst(rst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(frame_started), .out_pulse(frame_started_mclk),.busy());
pulse_cross_clock vsync_late_mclk_i (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(vsync_late), .out_pulse(vsync_late_mclk),.busy());
pulse_cross_clock frame_started_i (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(frame_started), .out_pulse(frame_started_mclk),.busy());
endmodule
compressor_jp/cmprs_macroblock_buf_iface.v
View file @ b721ae66
......@@ -25,10 +25,13 @@
module cmprs_macroblock_buf_iface #(
)(
input rst,
// input rst,
input xclk, // global clock input, compressor single clock rate
input mclk, // global clock for commands (posedge) and write side of the memory buffer (negedge)
input mrst, // @posedge mclk, sync reset
input xrst, // @posedge xclk, sync reset
// buffer interface, DDR3 memory read
input xfer_reset_page_rd, // @ negedge mclk - reset ddr3 memory buffer. Use it to reset the read buffer too
input page_ready_chn, // single mclk (posedge)
......@@ -200,18 +203,19 @@ module cmprs_macroblock_buf_iface #(
end
reg nmrst;
always @(negedge mclk) nmrst <= mrst;
// synchronization between mclk and xclk clock domains
// negedge mclk -> xclk (verify clock inversion is absorbed)
pulse_cross_clock reset_page_rd_i (.rst(rst), .src_clk(~mclk),.dst_clk(xclk), .in_pulse(xfer_reset_page_rd), .out_pulse(reset_page_rd),.busy());
pulse_cross_clock reset_page_rd_i (.rst(nmrst), .src_clk(~mclk),.dst_clk(xclk), .in_pulse(xfer_reset_page_rd), .out_pulse(reset_page_rd),.busy());
// mclk -> xclk
pulse_cross_clock page_ready_i (.rst(rst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(page_ready_chn), .out_pulse(page_ready),.busy());
pulse_cross_clock page_ready_i (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(page_ready_chn), .out_pulse(page_ready),.busy());
multipulse_cross_clock #(
.WIDTH(3),
.EXTRA_DLY(0)
) multipulse_cross_clock_i (
.rst (rst), // input
.rst (xrst), // input
.src_clk (xclk), // input
.dst_clk (mclk), // input
.num_pulses ({1'b0,add_invalid}), // input[0:0]
......
compressor_jp/cmprs_out_fifo.v
View file @ b721ae66
......@@ -21,9 +21,11 @@
`timescale 1ns/1ps
module cmprs_out_fifo(
input rst, // mostly for simulation
// input rst, // mostly for simulation
// wclk domain
input wclk, // source clock (2x pixel clock, inverted)
input wrst, // @posedge wclk, sync reset
input we,
input [15:0] wdata,
input wa_rst, // reset low address bits when stuffer is disabled (to make sure it is multiple of 32 bytes
......@@ -32,13 +34,14 @@ module cmprs_out_fifo(
// rclk domain
input rclk,
input rst_fifo, // reset FIFO (set read address to write, reset count)
input rrst, // @posedge rclk, sync reset
input rst_fifo, // reset FIFO (set read address to write, reset count)
input ren,
output [63:0] rdata,
output eof, // single rclk pulse signalling EOF
input eof_written, // confirm frame written ofer AFI to the system memory (single rclk pulse)
output flush_fifo, // EOF, need to output all what is in FIFO (Stays active until enough data chunks are read)
output [7:0] fifo_count // number of 32-byte chunks in FIFO
output eof, // single rclk pulse signalling EOF
input eof_written, // confirm frame written ofer AFI to the system memory (single rclk pulse)
output flush_fifo, // EOF, need to output all what is in FIFO (Stays active until enough data chunks are read)
output [7:0] fifo_count // number of 32-byte chunks in FIFO
);
reg regen;
......@@ -54,8 +57,8 @@ module cmprs_out_fifo(
assign fifo_count = count32;
assign eof = wlast_rclk;
always @ (posedge rst or posedge wclk) begin
if (rst) waddr <= 0;
always @ (posedge wclk) begin
if (wrst) waddr <= 0;
else if (wa_rst) waddr <= waddr & 11'h7f0; // reset 4 LSBs only
else if (we) waddr <= waddr + 1;
end
......@@ -82,10 +85,10 @@ module cmprs_out_fifo(
end
// wclk -> rclk
pulse_cross_clock written32b_i (.rst(rst), .src_clk(wclk), .dst_clk(rclk), .in_pulse(we && (&waddr[3:0])), .out_pulse(written32b),.busy());
pulse_cross_clock wlast_rclk_i (.rst(rst), .src_clk(wclk), .dst_clk(rclk), .in_pulse(wlast), .out_pulse(wlast_rclk),.busy());
pulse_cross_clock written32b_i (.rst(wrst), .src_clk(wclk), .dst_clk(rclk), .in_pulse(we && (&waddr[3:0])), .out_pulse(written32b),.busy());
pulse_cross_clock wlast_rclk_i (.rst(wrst), .src_clk(wclk), .dst_clk(rclk), .in_pulse(wlast), .out_pulse(wlast_rclk),.busy());
// rclk -> wclk
pulse_cross_clock eof_written_wclk_i (.rst(rst), .src_clk(rclk), .dst_clk(wclk), .in_pulse(eof_written), .out_pulse(eof_written_wclk),.busy());
pulse_cross_clock eof_written_wclk_i (.rst(rrst), .src_clk(rclk), .dst_clk(wclk), .in_pulse(eof_written), .out_pulse(eof_written_wclk),.busy());
ram_var_w_var_r #(
.REGISTERS(1),
.LOG2WIDTH_WR(4),
......
compressor_jp/compressor393.v
View file @ b721ae66
......@@ -113,9 +113,13 @@ module compressor393 # (
parameter AFI_MUX_BUF_LATENCY = 2 // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
)(
input rst, // global reset
// input rst, // global reset
input xclk, // global clock input, compressor single clock rate
input xclk2x, // global clock input, compressor double clock rate, nominally rising edge aligned
input mrst, // @posedge mclk, sync reset
input xrst, // @posedge xclk, sync reset
input hrst, // @posedge hclk, sync reset
// programming interface
input mclk, // global system/memory clock
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
......@@ -244,8 +248,9 @@ module compressor393 # (
/* Instance template for module status_router8 */
status_router8 status_router8_i (
.rst (rst), // input
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.db_in0 (status_ad_mux[ 0 +: 8]), // input[7:0]
.rq_in0 (status_rq_mux[0]), // input
.start_in0 (status_start_mux[0]), // output
......@@ -354,9 +359,12 @@ module compressor393 # (
.CMPRS_TIMEOUT_BITS (CMPRS_TIMEOUT_BITS),
.CMPRS_TIMEOUT (CMPRS_TIMEOUT)
) jp_channel_i (
.rst (rst), // input
// .rst (rst), // input
.xclk (xclk), // input
.xclk2x (xclk2x), // input
.mrst (mrst), // input
.xrst (xrst), // input
.hrst (hrst), // input
.mclk (mclk), // input
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
......@@ -417,9 +425,11 @@ module compressor393 # (
.CMPRS_AFIMUX_CYCBITS (CMPRS_AFIMUX_CYCBITS),
.AFI_MUX_BUF_LATENCY (AFI_MUX_BUF_LATENCY)
) cmprs_afi0_mux_i (
.rst (rst), // input
// .rst (rst), // input
.mclk (mclk), // input
.hclk (hclk), // input
.mrst (mrst), // input
.hrst (hrst), // input
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
.status_ad (status_ad_mux[32 +: 8]), // output[7:0]
......@@ -490,9 +500,11 @@ module compressor393 # (
.CMPRS_AFIMUX_CYCBITS (CMPRS_AFIMUX_CYCBITS),
.AFI_MUX_BUF_LATENCY (AFI_MUX_BUF_LATENCY)
) cmprs_afi1_mux_i (
.rst (rst), // input
// .rst (rst), // input
.mclk (mclk), // input
.hclk (hclk), // input
.mrst (mrst), // input
.hrst (hrst), // input
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
.status_ad (status_ad_mux[40 +: 8]), // output[7:0]
......@@ -561,9 +573,11 @@ module compressor393 # (
.CMPRS_AFIMUX_CYCBITS (CMPRS_AFIMUX_CYCBITS),
.AFI_MUX_BUF_LATENCY (AFI_MUX_BUF_LATENCY)
) cmprs_afi0_mux_i (
.rst (rst), // input
// .rst (rst), // input
.mclk (mclk), // input
.hclk (hclk), // input
.mrst (mrst), // input
.hrst (hrst), // input
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
.status_ad (status_ad_mux[32 +: 8]), // output[7:0]
......
compressor_jp/jp_channel.v
View file @ b721ae66
......@@ -97,9 +97,13 @@ module jp_channel#(
)(
input rst, // global reset
// input rst, // global reset
input xclk, // global clock input, compressor single clock rate
input xclk2x, // global clock input, compressor double clock rate, nominally rising edge aligned
input mrst, // @posedge mclk, sync reset
input xrst, // @posedge xclk, sync reset
input hrst, // @posedge xclk, sync reset
// programming interface
input mclk, // global system/memory clock
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
......@@ -332,8 +336,9 @@ module jp_channel#(
.ADDR_WIDTH (3),
.DATA_WIDTH (32)
) cmd_deser_32bit_i (
.rst (rst), // input
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[3:0]
......@@ -356,14 +361,15 @@ module jp_channel#(
.EXTRA_REG_ADDR (CMPRS_HIFREQ_REG_ADDR)
) status_generate_i (
.rst (rst), // input
.clk (mclk), // input
.we (set_status_w), // input
.wd (cmd_data[7:0]), // input[7:0]
.status ({hifreq,status_data}), // input[2:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (set_status_w), // input
.wd (cmd_data[7:0]), // input[7:0]
.status ({hifreq,status_data}), // input[2:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
);
//hifreq
// Port buffer - TODO: Move to memory controller
......@@ -383,6 +389,7 @@ module jp_channel#(
.we (buf_we), // input
.data_in (buf_din) // input[63:0]
);
cmprs_cmd_decode #(
.CMPRS_CBIT_RUN (CMPRS_CBIT_RUN),
.CMPRS_CBIT_RUN_BITS (CMPRS_CBIT_RUN_BITS),
......@@ -433,9 +440,10 @@ module jp_channel#(
.CMPRS_CSAT_CR_BITS (CMPRS_CSAT_CR_BITS),
.CMPRS_CORING_BITS (CMPRS_CORING_BITS)
) cmprs_cmd_decode_i (
.rst (rst), // input
// .rst (rst), // input
.xclk (xclk), // input - global clock input, compressor single clock rate
.mclk (mclk), // input - global system/memory clock
.mrst (mrst), // input
.ctrl_we (set_ctrl_reg_w), // input - control register write enable
.format_we (set_format_w), // input - write number of tiles and left margin
.color_sat_we (set_color_saturation_w), // input - write color saturation values
......@@ -493,9 +501,11 @@ module jp_channel#(
.CMPRS_TIMEOUT_BITS (CMPRS_TIMEOUT_BITS),
.CMPRS_TIMEOUT (CMPRS_TIMEOUT)
) cmprs_frame_sync_i (
.rst (rst), // input
// .rst (rst), // input
.xclk (xclk), // input - global clock input, compressor single clock rate
.mclk (mclk), // input - global system/memory clock
.mrst (mrst), // input
.xrst (xrst), // input
.cmprs_en (cmprs_en_mclk), // input - @mclk 0 resets immediately
.cmprs_en_extend (cmprs_en_extend), // output
.cmprs_run (cmprs_run_mclk), // input - @mclk enable propagation of vsync_late to frame_start_dst in bonded(sync to src) mode
......@@ -526,27 +536,29 @@ module jp_channel#(
);
cmprs_macroblock_buf_iface cmprs_macroblock_buf_iface_i (
.rst (rst), // input
.xclk (xclk), // input
.mclk (mclk), // input
// .rst (rst), // input
.xclk (xclk), // input
.mclk (mclk), // input
.mrst (mrst), // input
.xrst (xrst), // input
.xfer_reset_page_rd (xfer_reset_page_rd), // input
.page_ready_chn (page_ready_chn), // input
.next_page_chn (next_page_chn), // output
.frame_en (frame_en), // input
.frame_go (frame_go), // input - do not use - assign to frame_en? Running frames can be controlled by other means
.left_marg (left_marg), // input[4:0]
.page_ready_chn (page_ready_chn), // input
.next_page_chn (next_page_chn), // output
.frame_en (frame_en), // input
.frame_go (frame_go), // input - do not use - assign to frame_en? Running frames can be controlled by other means
.left_marg (left_marg), // input[4:0]
.n_blocks_in_row_m1 (n_blocks_in_row_m1), // input[12:0]
.n_block_rows_m1 (n_block_rows_m1), // input[12:0]
.mb_w_m1 (mb_w_m1), // input[5:0] // macroblock width minus 1 // 3 LSB not used - set them to all 1
.mb_hper (mb_hper), // input[4:0] // macroblock horizontal period (8/16) // 3 LSB not used (set them 0)
.tile_width (tile_width), // input[1:0] // memory tile width. Can be 32/64/128: 0 - 16, 1 - 32, 2 - 64, 3 - 128
.mb_pre_end_in (mb_pre_end), // input
.mb_release_buf (mb_release_buf), // input
.mb_pre_start_out (mb_pre_start), // output
.start_page (start_page), // output[1:0]
.macroblock_x (macroblock_x), // output[6:0]
.first_mb (first_mb), // output reg
.last_mb (last_mb) // output
.n_block_rows_m1 (n_block_rows_m1), // input[12:0]
.mb_w_m1 (mb_w_m1), // input[5:0] // macroblock width minus 1 // 3 LSB not used - set them to all 1
.mb_hper (mb_hper), // input[4:0] // macroblock horizontal period (8/16) // 3 LSB not used (set them 0)
.tile_width (tile_width), // input[1:0] // memory tile width. Can be 32/64/128: 0 - 16, 1 - 32, 2 - 64, 3 - 128
.mb_pre_end_in (mb_pre_end), // input
.mb_release_buf (mb_release_buf), // input
.mb_pre_start_out (mb_pre_start), // output
.start_page (start_page), // output[1:0]
.macroblock_x (macroblock_x), // output[6:0]
.first_mb (first_mb), // output reg
.last_mb (last_mb) // output
);
......@@ -562,25 +574,25 @@ module jp_channel#(
.CMPRS_MONO8 (CMPRS_MONO8)
) cmprs_pixel_buf_iface_i (
.xclk (xclk), // input
.frame_en (frame_en), // input
.buf_di (buf_pxd), // input[7:0]
.buf_ra (buf_ra), // output[11:0]
.buf_rd (buf_rd), // output[1:0]
.converter_type (converter_type), // input[2:0]
.mb_w_m1 (mb_w_m1), // input[5:0]
.mb_h_m1 (mb_h_m1), // input[5:0]
.tile_width (tile_width), // input[1:0]
.tile_col_width (tile_col_width), // input
.mb_pre_end (mb_pre_end), // output
.mb_release_buf (mb_release_buf), // output
.mb_pre_start (mb_pre_start), // input
.start_page (start_page), // input[1:0]
.macroblock_x (macroblock_x), // input[6:0]
.data_out (mb_data_out), // output[7:0] // Macroblock data out in scanline order
.xclk (xclk), // input
.frame_en (frame_en), // input
.buf_di (buf_pxd), // input[7:0]
.buf_ra (buf_ra), // output[11:0]
.buf_rd (buf_rd), // output[1:0]
.converter_type (converter_type), // input[2:0]
.mb_w_m1 (mb_w_m1), // input[5:0]
.mb_h_m1 (mb_h_m1), // input[5:0]
.tile_width (tile_width), // input[1:0]
.tile_col_width (tile_col_width), // input
.mb_pre_end (mb_pre_end), // output
.mb_release_buf (mb_release_buf), // output
.mb_pre_start (mb_pre_start), // input
.start_page (start_page), // input[1:0]
.macroblock_x (macroblock_x), // input[6:0]
.data_out (mb_data_out), // output[7:0] // Macroblock data out in scanline order
.pre_first_out (mb_pre_first_out), // output // Macroblock data out strobe - 1 cycle just before data valid == old pre_first_pixel?
// .data_valid (mb_data_valid) // output // Macroblock data out valid
.data_valid () // output // Macroblock data out valid Unused
.data_valid () // output // Macroblock data out valid Unused
);
csconvert #(
......@@ -668,8 +680,8 @@ module jp_channel#(
wire first_block_color=(color_tn[2:0]==3'h0) && color_first; // while color conversion,
reg first_block_color_after; // after color conversion,
reg first_block_dct; // after DCT
wire first_block_quant; // after quantizer
reg first_block_dct; // after DCT
wire first_block_quant; // after quantizer
always @ (posedge xclk) begin
if (dct_start) first_block_color_after <= first_block_color;
if (dct_last_in) first_block_dct <= first_block_color_after;
......@@ -679,15 +691,15 @@ module jp_channel#(
xdct393 xdct393_i (
.clk (xclk), // input
.en (frame_en), // input if zero will reset transpose memory page numbers
.start (dct_start), // input single-cycle start pulse that goes with the first pixel data. Other 63 should follow
.xin (yc_nodc), // input[9:0]
.last_in (dct_last_in), // output reg output high during input of the last of 64 pixels in a 8x8 block //
.pre_first_out (dct_pre_first_out), // outpu 1 cycle ahead of the first output in a 64 block
/// .dv (dct_dv), // output data output valid. Will go high on the 94-th cycle after the start (now - on 95-th?)
.clk (xclk), // input
.en (frame_en), // input if zero will reset transpose memory page numbers
.start (dct_start), // input single-cycle start pulse that goes with the first pixel data. Other 63 should follow
.xin (yc_nodc), // input[9:0]
.last_in (dct_last_in), // output reg output high during input of the last of 64 pixels in a 8x8 block //
.pre_first_out (dct_pre_first_out), // outpu 1 cycle ahead of the first output in a 64 block
/// .dv (dct_dv), // output data output valid. Will go high on the 94-th cycle after the start (now - on 95-th?)
.dv (), // not used: output data output valid. Will go high on the 94-th cycle after the start (now - on 95-th?)
.d_out (dct_out) // output[12:0]
.d_out (dct_out) // output[12:0]
);
wire quant_start;
dly_16 #(.WIDTH(1)) i_quant_start (.clk(xclk),.rst(1'b0), .dly(0), .din(dct_pre_first_out), .dout(quant_start)); // dly=0+1
......@@ -713,7 +725,7 @@ module jp_channel#(
.ADDR_BITS(3)
) table_ad_transmit_i (
.clk (mclk), // input @posedge
.a_not_d_in (cmd_a[0]), // input writing table address /not data (a[0] from cmd_deser)
.a_not_d_in (cmd_a[0]), // input writing table address /not data (a[0] from cmd_deser)
.we (set_tables_w), // input writing to tables (decoded stb from cmd_deser)
.din (cmd_data), // input[31:0] 32-bit data to serialize/write to tables (LSB first) - from cmd_deser
.ser_d (tser_d), // output[7:0] byte-wide serialized tables address/data to submodules
......@@ -791,7 +803,10 @@ module jp_channel#(
wire eof_written_xclk2xn;
// re-sync to posedge xclk2x
pulse_cross_clock finish_dcc_i (.rst(rst), .src_clk(~xclk2x), .dst_clk(xclk2x), .in_pulse(stuffer_done), .out_pulse(finish_dcc),.busy());
reg xrst2xn;
always @ (negedge xclk2x) xrst2xn <= xrst;
pulse_cross_clock finish_dcc_i (.rst(xrst2xn), .src_clk(~xclk2x), .dst_clk(xclk2x), .in_pulse(stuffer_done), .out_pulse(finish_dcc),.busy());
dcc_sync393 dcc_sync393_i (
.sclk (xclk2x), // input
......@@ -850,8 +865,11 @@ module jp_channel#(
stuffer393 stuffer393_i (
.rst (rst), // input
// .rst (rst), // input
.mclk (mclk), // input
.mrst (mrst), // input
.xrst (xrst), // input
.ts_pre_stb (ts_pre_stb), // input 1 cycle before timestamp data, @mclk
.ts_data (ts_data), // input[7:0] 8-byte timestamp data (s0,s1,s2,s3,us0,us1,us2,us3==0)
.color_first (color_first), // input valid @xclk - only for sec/usec
......@@ -878,17 +896,20 @@ module jp_channel#(
`endif
);
pulse_cross_clock stuffer_done_mclk_i (.rst(rst), .src_clk(~xclk2x), .dst_clk(mclk), .in_pulse(stuffer_done), .out_pulse(stuffer_done_mclk),.busy());
pulse_cross_clock stuffer_done_mclk_i (.rst(xrst2xn), .src_clk(~xclk2x), .dst_clk(mclk), .in_pulse(stuffer_done), .out_pulse(stuffer_done_mclk),.busy());
cmprs_out_fifo cmprs_out_fifo_i (
.rst (rst), // input mostly for simulation
// .rst (rst), // input mostly for simulation
// source (stuffer) clock domain
.wclk (~xclk2x), // input source clock (2x pixel clock, inverted) - same as stuffer out
.wrst (xrst2xn), // input mostly for simulation
.we (stuffer_dv), // input write data from stuffer
.wdata (stuffer_do), // input[15:0] data from stuffer module;
.wa_rst (!stuffer_en), // input reset low address bits when stuffer is disabled (to make sure it is multiple of 32 bytes
.wlast (stuffer_done), // input - written last 32 bytes of a frame (flush FIFO) - stuffer_done (has to be later than we)
.eof_written_wclk (eof_written_xclk2xn), // output - AFI had transferred frame data to the system memory
.rclk (hclk), // input - AFI clock
.rrst (hrst), // input - AFI clock
// AFI clock domain
.rst_fifo (fifo_rst), // input - reset FIFO (set read address to write, reset count)
.ren (fifo_ren), // input - fifo read from AFI channel mux
......@@ -898,7 +919,7 @@ module jp_channel#(
.flush_fifo (fifo_flush), // output level signalling that FIFO has data from the current frame (use short AXI burst if needed)
.fifo_count (fifo_count) // output[7:0] - number of 32-byte chunks available in FIFO
);
pulse_cross_clock eof_written_mclk_i (.rst(rst), .src_clk(~xclk2x), .dst_clk(mclk), .in_pulse(eof_written_xclk2xn), .out_pulse(eof_written_mclk),.busy());
pulse_cross_clock eof_written_mclk_i (.rst(xrst2xn), .src_clk(~xclk2x), .dst_clk(mclk), .in_pulse(eof_written_xclk2xn), .out_pulse(eof_written_mclk),.busy());
// TODO: Add status module to combine/FF, re-clock status signals
......
compressor_jp/stuffer393.v
View file @ b721ae66
......@@ -42,8 +42,11 @@
// Or make FIFO outside of the stuffer?
module stuffer393 (
input rst, // global reset
// input rst, // global reset
input mclk,
input mrst, // @posedge mclk, sync reset
input xrst, // @posedge xclk, sync reset
// time stamping - will copy time at the end of color_first (later than the first hact after vact in the current frame, but before the next one
// and before the data is needed for output
input ts_pre_stb, // @mclk - 1 cycle before receiving 8 bytes of timestamp data
......@@ -414,17 +417,23 @@ end
// extract strart of frame run from different clock, re-clock from the source
always @ (posedge fradv_clk) color_first_r <= color_first;
pulse_cross_clock stb_start_i (.rst(rst), .src_clk(fradv_clk), .dst_clk(~clk), .in_pulse(!color_first && color_first_r), .out_pulse(stb_start),.busy());
pulse_cross_clock stb_start_i (.rst(xrst), .src_clk(fradv_clk), .dst_clk(~clk), .in_pulse(!color_first && color_first_r), .out_pulse(stb_start),.busy());
reg rst_nclk;
always @ (negedge clk) rst_nclk <= xrst;
timestamp_fifo timestamp_fifo_i (
.rst (rst), // input
// .rst (rst), // input
.sclk (mclk), // input
.srst (mrst), // input
.pre_stb (ts_pre_stb), // input
.din (ts_data), // input[7:0]
// may use stb_start @ negedge clk
.aclk (~clk), //fradv_clk), // input
.arst (rst_nclk), //fradv_clk), // input
.advance (stb_start), // color_first), // input
.rclk (~clk), // input
.rrst (rst_nclk), //fradv_clk), // input
.rstb (ts_rstb), // input
.dout (ts_dout) // output[7:0] reg
);
......
logger/event_logger.v
View file @ b721ae66
......@@ -51,9 +51,11 @@ module event_logger#(
parameter GPIO_N = 10 // number of GPIO bits to control
)(
input rst,
// input rst,
input mclk, // system clock
input xclk, // half frequency (80 MHz nominal)
input xclk, // was in 353: half frequency (80 MHz nominal)
input mrst, // @ posedge mclk - sync reset
input xrst, // @ posedge xclk - sync reset
// programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
......@@ -296,12 +298,12 @@ module event_logger#(
end
// generate strobes to copy configuration data from mclk to xclk domain
pulse_cross_clock i_we_config_imu_xclk (.rst(1'b0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_imu), .out_pulse(we_config_imu_xclk),.busy());
pulse_cross_clock i_we_config_gps_xclk (.rst(1'b0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_gps), .out_pulse(we_config_gps_xclk),.busy());
pulse_cross_clock i_we_config_msg_xclk (.rst(1'b0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_msg), .out_pulse(we_config_msg_xclk),.busy());
pulse_cross_clock i_we_config_rst_xclk (.rst(1'b0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_rst), .out_pulse(we_config_rst_xclk),.busy());
pulse_cross_clock i_we_config_debug_xclk (.rst(1'b0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_debug), .out_pulse(we_config_debug_xclk),.busy());
pulse_cross_clock i_we_bitHalfPeriod_xclk (.rst(1'b0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_bitHalfPeriod), .out_pulse(we_bitHalfPeriod_xclk),.busy());
pulse_cross_clock i_we_config_imu_xclk (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_imu), .out_pulse(we_config_imu_xclk),.busy());
pulse_cross_clock i_we_config_gps_xclk (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_gps), .out_pulse(we_config_gps_xclk),.busy());
pulse_cross_clock i_we_config_msg_xclk (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_msg), .out_pulse(we_config_msg_xclk),.busy());
pulse_cross_clock i_we_config_rst_xclk (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_rst), .out_pulse(we_config_rst_xclk),.busy());
pulse_cross_clock i_we_config_debug_xclk (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_debug), .out_pulse(we_config_debug_xclk),.busy());
pulse_cross_clock i_we_bitHalfPeriod_xclk (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_bitHalfPeriod), .out_pulse(we_bitHalfPeriod_xclk),.busy());
cmd_deser #(
.ADDR (LOGGER_ADDR),
......@@ -313,8 +315,9 @@ module event_logger#(
.ADDR_MASK1 (LOGGER_STATUS_MASK)
) cmd_deser_32bit_i (
.rst (rst), // input
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[3:0]
......@@ -327,8 +330,9 @@ module event_logger#(
.PAYLOAD_BITS (26),
.REGISTER_STATUS (1)
) status_generate_i (
.rst (rst), // input
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (cmd_status), // input
.wd (cmd_data[7:0]), // input[7:0]
.status ({sample_counter,2'b0}), // input[25:0] // 2 LSBs - may add "real" status
......@@ -378,9 +382,11 @@ fixed-length de-noise circuitry with latency 256*T(xclk) (~3usec)
/* logs frame synchronization data from other camera (same as frame sync) */
// ts_stb (mclk) -> trig)
imu_exttime393 i_imu_exttime(
.rst (rst), // input global reset
// .rst (rst), // input global reset
.mclk (mclk), // system clock, negedge
.xclk (xclk), // half frequency (80 MHz nominal)
.mrst (mrst), // @mclk - sync reset
.xrst (xrst), // @xclk - sync reset
.en_chn_mclk (enable_syn_mclk), // enable module operation, if 0 - reset
.ts_stb_chn0 (ts_stb_chn0), // input
.ts_data_chn0 (ts_data_chn0), // input[7:0]
......
logger/imu_exttime393.v
View file @ b721ae66
......@@ -25,9 +25,11 @@ When sensors are running in free running mode, each sensor may provide individua
*/
module imu_exttime393(
input rst,
// input rst,
input mclk, // system clock, negedge TODO:COnvert to posedge!
input xclk, // half frequency (80 MHz nominal)
input mrst, // @ posedge mclk - sync reset
input xrst, // @ posedge xclk - sync reset
input [3:0] en_chn_mclk, // enable per-channel module operation, if all 0 - reset
// byte-parallel timestamps from 4 sensors channels (in triggered mode all are the same, different only in free running mode)
// each may generate logger event, channel number encoded in bits 25:24 of the external microseconds
......@@ -128,58 +130,70 @@ module imu_exttime393(
timestamp_fifo timestamp_fifo_chn0_i (
.rst (rst), // input
// .rst (rst), // input
.sclk (mclk), // input
.srst (mrst), // input
.pre_stb (ts_stb[0]), // input
.din (ts_data_chn0), // input[7:0]
.aclk (mclk), // input
.arst (mrst), // input
.advance (ts_stb[0]), // enough time
.rclk (mclk), // input
.rrst (mrst), // input
.rstb (pre_copy_started && (sel_chn == 2'h0)),// input
.dout (dout_chn[0 * 8 +: 8]) // output[7:0] reg valid with copy_selected[1]
);
timestamp_fifo timestamp_fifo_chn1_i (
.rst (rst), // input
// .rst (rst), // input
.sclk (mclk), // input
.srst (mrst), // input
.pre_stb (ts_stb[1]), // input
.din (ts_data_chn1), // input[7:0]
.aclk (mclk), // input
.arst (mrst), // input
.advance (ts_stb[1]), // enough time
.rclk (mclk), // input
.rrst (mrst), // input
.rstb (pre_copy_started && (sel_chn == 2'h1)),// input
.dout (dout_chn[1 * 8 +: 8]) // output[7:0] reg valid with copy_selected[1]
);
timestamp_fifo timestamp_fifo_chn2_i (
.rst (rst), // input
// .rst (rst), // input
.sclk (mclk), // input
.srst (mrst), // input
.pre_stb (ts_stb[2]), // input
.din (ts_data_chn2), // input[7:0]
.aclk (mclk), // input
.arst (mrst), // input
.advance (ts_stb[2]), // enough time
.rclk (mclk), // input
.rrst (mrst), // input
.rstb (pre_copy_started && (sel_chn == 2'h2)),// input
.dout (dout_chn[2 * 8 +: 8]) // output[7:0] reg valid with copy_selected[1]
);
timestamp_fifo timestamp_fifo_chn3_i (
.rst (rst), // input
// .rst (rst), // input
.sclk (mclk), // input
.srst (mrst), // input
.pre_stb (ts_stb[3]), // input
.din (ts_data_chn3), // input[7:0]
.aclk (mclk), // input
.arst (mrst), // input
.advance (ts_stb[3]), // enough time
.rclk (mclk), // input
.rrst (mrst), // input
.rstb (pre_copy_started && (sel_chn == 2'h3)),// input
.dout (dout_chn[3 * 8 +: 8]) // output[7:0] reg valid with copy_selected[1]
);
pulse_cross_clock i_rd_start_mclk (.rst(1'b0), .src_clk(xclk), .dst_clk(mclk), .in_pulse(rd_start), .out_pulse(rd_start_mclk),.busy());
pulse_cross_clock i_rd_start_mclk (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(rd_start), .out_pulse(rd_start_mclk),.busy());
// generate timestamp request as soon as one of the sub-channels starts copying. That time stamp will be stored for this (ext) channel
pulse_cross_clock i_ts (.rst(1'b0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(pre_copy_w), .out_pulse(ts),.busy());
pulse_cross_clock i_ts (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(pre_copy_w), .out_pulse(ts),.busy());
endmodule
memctrl/cmd_encod_linear_rd.v
View file @ b721ae66
......@@ -30,7 +30,7 @@ module cmd_encod_linear_rd #(
parameter CMD_DONE_BIT= 10, // VDT BUG: CMD_DONE_BIT is used in a function call parameter!
parameter RSEL= 1'b1
) (
input rst,
input mrst,
input clk,
// programming interface
// input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
......@@ -90,20 +90,18 @@ module cmd_encod_linear_rd #(
assign rom_skip= rom_r[ENC_PAUSE_SHIFT+:2];
assign full_cmd= rom_cmd[1]?(rom_cmd[0]?CMD_ACTIVATE:CMD_PRECHARGE):(rom_cmd[0]?CMD_READ:CMD_NOP);
always @ (posedge rst or posedge clk) begin
if (rst) gen_run <= 0;
always @ (posedge clk) begin
if (mrst) gen_run <= 0;
else if (start) gen_run<= 1;
else if (pre_done) gen_run<= 0;
// if (rst) gen_run_d <= 0;
// else gen_run_d <= gen_run;
if (rst) gen_addr <= 0;
if (mrst) gen_addr <= 0;
else if (!start && !gen_run) gen_addr <= 0;
else if ((gen_addr==(REPEAT_ADDR-1)) && (num128[NUM_XFER_BITS-1:1]==0)) gen_addr <= REPEAT_ADDR+1; // skip loop alltogeter
else if ((gen_addr !=REPEAT_ADDR) || (num128[NUM_XFER_BITS-1:1]==0)) gen_addr <= gen_addr+1; // not in a loop
//counting loops?
if (rst) num128 <= 0;
if (mrst) num128 <= 0;
else if (start) num128 <= num128_in;
else if (!gen_run) num128 <= 0; //
else if ((gen_addr == (REPEAT_ADDR-1)) || (gen_addr == REPEAT_ADDR)) num128 <= num128 -1;
......@@ -121,8 +119,8 @@ module cmd_encod_linear_rd #(
end
// ROM-based (registered output) encoded sequence
always @ (posedge rst or posedge clk) begin
if (rst) rom_r <= 0;
always @ (posedge clk) begin
if (mrst) rom_r <= 0;
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT);
4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PAUSE_SHIFT);
......@@ -136,17 +134,15 @@ module cmd_encod_linear_rd #(
default:rom_r <= 0;
endcase
end
always @ (posedge rst or posedge clk) begin
// if (rst) done <= 0;
// else done <= pre_done;
always @ (posedge clk) begin
if (rst) enc_wr <= 0;
if (mrst) enc_wr <= 0;
else enc_wr <= gen_run; // || gen_run_d;
if (rst) enc_done <= 0;
if (mrst) enc_done <= 0;
else enc_done <= enc_wr && !gen_run; // !gen_run_d;
if (rst) enc_cmd <= 0;
if (mrst) enc_cmd <= 0;
else if (gen_run) begin
if (rom_cmd==0) enc_cmd <= func_encode_skip ( // encode pause
{{CMD_PAUSE_BITS-2{1'b0}},rom_skip[1:0]}, // skip; // number of extra cycles to skip (and keep all the other outputs)
......@@ -184,74 +180,5 @@ module cmd_encod_linear_rd #(
// move to include?
`include "includes/x393_mcontr_encode_cmd.vh"
/*
function [31:0] func_encode_skip;
input [CMD_PAUSE_BITS-1:0] skip; // number of extra cycles to skip (and keep all the other outputs)
input done; // end of sequence
input [2:0] bank; // bank (here OK to be any)
input odt_en; // enable ODT
input cke; // disable CKE
input sel; // first/second half-cycle, other will be nop (cke+odt applicable to both)
input dq_en; // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
input dqs_en; // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
input dqs_toggle; // enable toggle DQS according to the pattern
input dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
input buf_wr; // connect to external buffer (but only if not paused)
input buf_rd; // connect to external buffer (but only if not paused)
input buf_rst; // connect to external buffer (but only if not paused)
begin
func_encode_skip= func_encode_cmd (
{{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]}, // 15-bit row/column address
bank[2:0], // bank (here OK to be any)
3'b0, // RAS/CAS/WE, positive logic
odt_en, // enable ODT
cke, // disable CKE
sel, // first/second half-cycle, other will be nop (cke+odt applicable to both)
dq_en, // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
dqs_en, // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
dqs_toggle, // enable toggle DQS according to the pattern
dci, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
buf_wr, // connect to external buffer (but only if not paused)
buf_rd, // connect to external buffer (but only if not paused)
1'b0, // nop
buf_rst);
end
endfunction
function [31:0] func_encode_cmd;
input [14:0] addr; // 15-bit row/column address
input [2:0] bank; // bank (here OK to be any)
input [2:0] rcw; // RAS/CAS/WE, positive logic
input odt_en; // enable ODT
input cke; // disable CKE
input sel; // first/second half-cycle, other will be nop (cke+odt applicable to both)
input dq_en; // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
input dqs_en; // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
input dqs_toggle; // enable toggle DQS according to the pattern
input dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
input buf_wr; // connect to external buffer (but only if not paused)
input buf_rd; // connect to external buffer (but only if not paused)
input nop; // add NOP after the current command, keep other data
input buf_rst; // connect to external buffer (but only if not paused)
begin
func_encode_cmd={
addr[14:0], // 15-bit row/column address
bank [2:0], // bank
rcw[2:0], // RAS/CAS/WE
odt_en, // enable ODT
cke, // may be optimized (removed from here)?
sel, // first/second half-cycle, other will be nop (cke+odt applicable to both)
dq_en, // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
dqs_en, // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
dqs_toggle, // enable toggle DQS according to the pattern
dci, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
buf_wr, // phy_buf_wr, // connect to external buffer (but only if not paused)
buf_rd, // phy_buf_rd, // connect to external buffer (but only if not paused)
nop, // add NOP after the current command, keep other data
buf_rst // Reserved for future use
};
end
endfunction
*/
endmodule
/endmodule
memctrl/cmd_encod_linear_rw.v
View file @ b721ae66
......@@ -30,7 +30,7 @@ module cmd_encod_linear_rw#(
parameter RSEL= 1'b1, // late/early READ commands (to adjust timing by 1 SDCLK period)
parameter WSEL= 1'b0 // late/early WRITE commands (to adjust timing by 1 SDCLK period)
) (
input rst,
input mrst,
input clk,
// programming interface
// input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
......@@ -63,7 +63,7 @@ module cmd_encod_linear_rw#(
.CMD_DONE_BIT (CMD_DONE_BIT),
.RSEL (RSEL)
) cmd_encod_linear_rd_i (
.rst (rst), // input
.mrst (mrst), // input
.clk (clk), // input
.bank_in (bank_in), // input[2:0]
.row_in (row_in), // input[14:0]
......@@ -84,7 +84,7 @@ module cmd_encod_linear_rw#(
.CMD_DONE_BIT (CMD_DONE_BIT),
.WSEL (WSEL)
) cmd_encod_linear_wr_i (
.rst (rst), // input
.mrst (mrst), // input
.clk (clk), // input
.bank_in (bank_in), // input[2:0]
.row_in (row_in), // input[14:0]
......@@ -97,11 +97,11 @@ module cmd_encod_linear_rw#(
.enc_done (enc_done_wr) // output reg
);
always @(posedge rst or posedge clk) begin
if (rst) start <= 0;
always @(posedge clk) begin
if (mrst) start <= 0;
else start <= start_rd || start_wr;
if (rst) select_wr <= 0;
if (mrst) select_wr <= 0;
else if (start_rd) select_wr <= 0;
else if (start_wr) select_wr <= 1;
end
......
memctrl/cmd_encod_linear_wr.v
View file @ b721ae66
......@@ -29,7 +29,7 @@ module cmd_encod_linear_wr #(
parameter CMD_DONE_BIT= 10, // VDT BUG: CMD_DONE_BIT is used in a function call parameter!
parameter WSEL= 1'b0
) (
input rst,
input mrst,
input clk,
// programming interface
input [2:0] bank_in, // bank address
......@@ -117,58 +117,39 @@ module cmd_encod_linear_wr #(
start_d <= start;
cut_buf_rd <= rom_r[ENC_BUF_RD] && (cut_buf_rd || next_zero_w);
end
always @ (posedge rst or posedge clk) begin
always @ (posedge clk) begin
if (rst) gen_run <= 0;
if (mrst) gen_run <= 0;
else if (start) gen_run<= 1;
else if (pre_done) gen_run<= 0;
// if (rst) gen_run_d <= 0;
// else gen_run_d <= gen_run;
if (rst) gen_addr <= 0;
if (mrst) gen_addr <= 0;
else if (!start && !gen_run) gen_addr <= 0;
else if ((gen_addr==(REPEAT_ADDR-1)) && few_write) gen_addr <= jump_gen_addr;
// else if ((gen_addr !=REPEAT_ADDR) || (num128[NUM_XFER_BITS:1]==0)) gen_addr <= gen_addr+1; // not in a loop
// else if ((gen_addr !=REPEAT_ADDR) || (num128==2)) gen_addr <= gen_addr+1; // not in a loop
else if ((gen_addr !=REPEAT_ADDR) || (num128[NUM_XFER_BITS:2]==0)) gen_addr <= gen_addr+1; // not in a loop
//counting loops
if (rst) num128 <= 0;
if (mrst) num128 <= 0;
else if (start) num128 <= {(num128_in==0)?1'b1:1'b0,num128_in};
else if (!gen_run) num128 <= 0; //
// else if ((gen_addr == (REPEAT_ADDR-1)) || (gen_addr == REPEAT_ADDR)) num128 <= num128 -1; // ????? - FIXME
else if (write_addr_w) num128 <= num128 -1;
if (rst) single_write <= 0;
if (mrst) single_write <= 0;
else if (start_d) single_write <= (num128[NUM_XFER_BITS:1]==0); // could not be 0
if (rst) dual_write <= 0;
if (mrst) dual_write <= 0;
else if (start_d) dual_write <= (num128==2);
// if (rst) triple_write <= 0;
// else if (start_d) triple_write <= (num128==3);
if (rst) few_write <= 0;
if (mrst) few_write <= 0;
else if (start_d) few_write <=(num128[NUM_XFER_BITS:2]==0); // (0,)1,2 or3
//
// if (rst) few_write <= 0;
// else few_write <= single_write | dual_write | triple_write;
if (rst) jump_gen_addr <= 0;
else jump_gen_addr <= single_write ? NO_WRITE_ADDR : (dual_write ? LAST_WRITE_ADDR : PRELAST_WRITE_ADDR);
//triple_write
// reg single_write; // only one burst has to be written
// reg dual_write; // Two bursts have to be written
if (mrst) jump_gen_addr <= 0;
else jump_gen_addr <= single_write ? NO_WRITE_ADDR : (dual_write ? LAST_WRITE_ADDR : PRELAST_WRITE_ADDR);
end
always @ (posedge clk) if (start) begin
row<=row_in;
// col <= start_col;
bank <= bank_in;
skip_next_page <= skip_next_page_in;
end
......@@ -180,8 +161,8 @@ module cmd_encod_linear_wr #(
// ROM-based (registered output) encoded sequence
// TODO: Remove last ENC_BUF_RD
always @ (posedge rst or posedge clk) begin
if (rst) rom_r <= 0;
always @ (posedge clk) begin
if (mrst) rom_r <= 0;
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD);// | (1 << ENC_NOP);
4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD);
......@@ -203,18 +184,16 @@ module cmd_encod_linear_wr #(
default:rom_r <= 0;
endcase
end
always @ (posedge rst or posedge clk) begin
// if (rst) done <= 0;
// else done <= pre_done;
always @ (posedge clk) begin
if (rst) enc_wr <= 0;
if (mrst) enc_wr <= 0;
else enc_wr <= gen_run; // || gen_run_d;
if (rst) enc_done <= 0;
// else enc_done <= enc_wr || !gen_run_d;
else enc_done <= enc_wr && !gen_run; // !gen_run_d;
if (mrst) enc_done <= 0;
// else enc_done <= enc_wr || !gen_run_d;
else enc_done <= enc_wr && !gen_run; // !gen_run_d;
if (rst) enc_cmd <= 0;
if (mrst) enc_cmd <= 0;
else if (gen_run) begin
if (rom_cmd==0) enc_cmd <= func_encode_skip ( // encode pause
{{CMD_PAUSE_BITS-2{1'b0}},rom_skip[1:0]}, // skip; // number of extra cycles to skip (and keep all the other outputs)
......
memctrl/cmd_encod_tiled_rd.v
View file @ b721ae66
......@@ -51,7 +51,7 @@ module cmd_encod_tiled_rd #(
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter RSEL= 1'b1
) (
input rst,
input mrst,
input clk,
// programming interface
input [2:0] start_bank, // bank address
......@@ -157,59 +157,55 @@ module cmd_encod_tiled_rd #(
assign pre_read= rom_r[ENC_CMD_SHIFT]; //1 cycle before READ command
always @ (posedge rst or posedge clk) begin
if (rst) gen_run <= 0;
always @ (posedge clk) begin
if (mrst) gen_run <= 0;
else if (start_d) gen_run<= 1; // delaying
else if (pre_done) gen_run<= 0;
// if (rst) gen_run_d <= 0;
// else gen_run_d <= gen_run;
if (rst) num_rows_m1 <= 0;
else if (start) num_rows_m1 <= num_rows_in_m1; // number of rows
if (rst) num_cols128_m1 <= 0;
else if (start) num_cols128_m1 <= num_cols_in_m1; // number of r16-byte columns
if (mrst) num_rows_m1 <= 0;
else if (start ) num_rows_m1 <= num_rows_in_m1; // number of rows
if (mrst) num_cols128_m1 <= 0;
else if (start) num_cols128_m1 <= num_cols_in_m1; // number of r16-byte columns
if (rst) start_d <=0;
else start_d <= start;
if (mrst) start_d <=0;
else start_d <= start;
if (rst) top_rc <= 0;
if (mrst) top_rc <= 0;
else if (start_d) top_rc <= {row,col}+1;
else if (pre_act && last_row) top_rc <= top_rc+1; // may increment RA
if (rst) row_col_bank <= 0;
else if (start_d) row_col_bank <= {row,col,bank}; // TODO: Use start_col,... and start, not start_d?
else if (pre_act) row_col_bank <= row_col_bank_next_w;
if (mrst) row_col_bank <= 0;
else if (start_d) row_col_bank <= {row,col,bank}; // TODO: Use start_col,... and start, not start_d?
else if (pre_act) row_col_bank <= row_col_bank_next_w;
if (rst) scan_row <= 0;
if (mrst) scan_row <= 0;
else if (start_d) scan_row <= 0;
else if (pre_act) scan_row <= last_row?0:scan_row+1;
if (rst) scan_col <= 0;
if (mrst) scan_col <= 0;
else if (start_d) scan_col <= 0;
else if (pre_act && last_row) scan_col <= scan_col+1; // for ACTIVATE, not for READ
if (rst) first_col <= 0;
if (mrst) first_col <= 0;
else if (start_d) first_col <= 1;
else if (pre_act && last_row) first_col <= 0;
if (rst) last_col <= 0;
if (mrst) last_col <= 0;
else if (start_d) last_col <= num_cols128_m1==0; // if single column - will start with 1'b1;
else if (pre_act) last_col <= (scan_col==num_cols128_m1); // too early for READ ?
if (rst) enable_autopre <= 0;
if (mrst) enable_autopre <= 0;
else if (start_d) enable_autopre <= 0;
else if (pre_act) enable_autopre <= last_col || !keep_open; // delayed by 2 pre_act tacts form last_col, OK with a single column
if (rst) loop_continue<=0;
else loop_continue <= (scan_col==num_cols128_m1) && last_row;
if (mrst) loop_continue<=0;
else loop_continue <= (scan_col==num_cols128_m1) && last_row;
if (rst) gen_addr <= 0;
else if (!start_d && !gen_run) gen_addr <= 0;
if (mrst) gen_addr <= 0;
else if (!start_d && !gen_run) gen_addr <= 0;
else if ((gen_addr==LOOP_LAST) && !loop_continue) gen_addr <= LOOP_FIRST; // skip loop alltogeter
else gen_addr <= gen_addr+1; // not in a loop
else gen_addr <= gen_addr+1; // not in a loop
end
always @ (posedge clk) if (start) begin
......@@ -222,8 +218,8 @@ module cmd_encod_tiled_rd #(
end
// ROM-based (registered output) encoded sequence
always @ (posedge rst or posedge clk) begin
if (rst) rom_r <= 0;
always @ (posedge clk) begin
if (mrst) rom_r <= 0;
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_PAUSE_SHIFT); // here does not matter, just to work with masked ACTIVATE
4'h1: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT);
......@@ -241,18 +237,15 @@ module cmd_encod_tiled_rd #(
default:rom_r <= 0;
endcase
end
always @ (posedge rst or posedge clk) begin
// if (rst) done <= 0;
// else done <= pre_done;
always @ (posedge clk) begin
if (rst) enc_wr <= 0;
if (mrst) enc_wr <= 0;
else enc_wr <= gen_run; // || gen_run_d;
if (rst) enc_done <= 0;
if (mrst) enc_done <= 0;
else enc_done <= enc_wr && !gen_run; // !gen_run_d;
if (rst) enc_cmd <= 0;
// else if ((rom_cmd==0) || (rom_cmd[1] && !enable_act)) enc_cmd <= func_encode_skip ( // encode pause
if (mrst) enc_cmd <= 0;
else if (gen_run) begin
if (rom_cmd[0] || (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
rom_cmd[1]? // activate
......@@ -295,13 +288,13 @@ module cmd_encod_tiled_rd #(
fifo_2regs #(
.WIDTH(COLADDR_NUMBER)
) fifo_2regs_i (
.rst (rst), // input
.clk (clk), // input
.mrst (mrst), // input
.clk (clk), // input
.din (row_col_bank[COLADDR_NUMBER-1:0]), // input[15:0]
.wr(pre_act), // input
.rd(pre_read), // input
.srst(start_d), // input
.dout(col_bank) // output[15:0]
.wr(pre_act), // input
.rd(pre_read), // input
.srst(start_d), // input
.dout(col_bank) // output[15:0]
);
`include "includes/x393_mcontr_encode_cmd.vh"
......
memctrl/cmd_encod_tiled_rw.v
View file @ b721ae66
......@@ -29,7 +29,7 @@ module cmd_encod_tiled_rw #(
parameter RSEL= 1'b1, // late/early READ commands (to adjust timing by 1 SDCLK period)
parameter WSEL= 1'b0 // late/early WRITE commands (to adjust timing by 1 SDCLK period)
) (
input rst,
input mrst,
input clk,
// programming interface
input [2:0] start_bank, // bank address
......@@ -62,21 +62,21 @@ module cmd_encod_tiled_rw #(
.CMD_DONE_BIT (CMD_DONE_BIT),
.RSEL (RSEL)
) cmd_encod_tiled_rd_i (
.rst (rst), // input
.clk (clk), // input
.start_bank (start_bank), // input[2:0]
.start_row (start_row), // input[14:0]
.start_col (start_col), // input[6:0]
.rowcol_inc_in (rowcol_inc_in), // input[13:0] // [21:0]
.num_rows_in_m1 (num_rows_in_m1), // input[5:0]
.num_cols_in_m1 (num_cols_in_m1), // input[5:0]
.keep_open_in (keep_open_in), // input
.mrst (mrst), // input
.clk (clk), // input
.start_bank (start_bank), // input[2:0]
.start_row (start_row), // input[14:0]
.start_col (start_col), // input[6:0]
.rowcol_inc_in (rowcol_inc_in), // input[13:0] // [21:0]
.num_rows_in_m1 (num_rows_in_m1), // input[5:0]
.num_cols_in_m1 (num_cols_in_m1), // input[5:0]
.keep_open_in (keep_open_in), // input
.skip_next_page_in (skip_next_page_in), // input
.start (start_rd), // input
.enc_cmd (enc_cmd_rd), // output[31:0] reg
.enc_wr (enc_wr_rd), // output reg
.enc_done (enc_done_rd) // output reg
.start (start_rd), // input
.enc_cmd (enc_cmd_rd), // output[31:0] reg
.enc_wr (enc_wr_rd), // output reg
.enc_done (enc_done_rd) // output reg
);
cmd_encod_tiled_wr #(
......@@ -86,7 +86,7 @@ module cmd_encod_tiled_rw #(
.CMD_DONE_BIT (CMD_DONE_BIT),
.WSEL (WSEL)
) cmd_encod_tiled_wr_i (
.rst (rst), // input
.mrst (mrst), // input
.clk (clk), // input
.start_bank (start_bank), // input[2:0]
.start_row (start_row), // input[14:0]
......@@ -94,7 +94,7 @@ module cmd_encod_tiled_rw #(
.rowcol_inc_in (rowcol_inc_in), // input[13:0] // [21:0]
.num_rows_in_m1 (num_rows_in_m1), // input[5:0]
.num_cols_in_m1 (num_cols_in_m1), // input[5:0]
.keep_open_in (keep_open_in), // input
.keep_open_in (keep_open_in), // input
.skip_next_page_in (skip_next_page_in), // input
.start (start_wr), // input
......@@ -103,11 +103,11 @@ module cmd_encod_tiled_rw #(
.enc_done (enc_done_wr) // output reg
);
always @(posedge rst or posedge clk) begin
if (rst) start <= 0;
always @(posedge clk) begin
if (mrst) start <= 0;
else start <= start_rd || start_wr;
if (rst) select_wr <= 0;
if (mrst) select_wr <= 0;
else if (start_rd) select_wr <= 0;
else if (start_wr) select_wr <= 1;
end
......
memctrl/cmd_encod_tiled_wr.v
View file @ b721ae66
......@@ -52,7 +52,7 @@ module cmd_encod_tiled_wr #(
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter WSEL= 1'b0
) (
input rst,
input mrst,
input clk,
// programming interface
input [2:0] start_bank, // bank address
......@@ -164,57 +164,54 @@ module cmd_encod_tiled_wr #(
assign pre_write= rom_r[ENC_CMD_SHIFT]; //1 cycle before READ command
always @ (posedge rst or posedge clk) begin
if (rst) gen_run <= 0;
always @ (posedge clk) begin
if (mrst) gen_run <= 0;
else if (start_d) gen_run<= 1; // delaying
else if (pre_done) gen_run<= 0;
// if (rst) gen_run_d <= 0;
// else gen_run_d <= gen_run;
if (rst) num_rows_m1 <= 0;
if (mrst) num_rows_m1 <= 0;
else if (start) num_rows_m1 <= num_rows_in_m1; // number of rows
if (rst) num_cols128_m1 <= 0;
if (mrst) num_cols128_m1 <= 0;
else if (start) num_cols128_m1 <= num_cols_in_m1; // number of r16-byte columns
if (rst) start_d <=0;
if (mrst) start_d <=0;
else start_d <= start;
if (rst) top_rc <= 0;
if (mrst) top_rc <= 0;
else if (start_d) top_rc <= {row,col}+1;
else if (pre_act && last_row) top_rc <= top_rc+1; // may increment RA
if (rst) row_col_bank <= 0;
if (mrst) row_col_bank <= 0;
else if (start_d) row_col_bank <= {row,col,bank}; // TODO: Use start_col,... and start, not start_d?
else if (pre_act) row_col_bank <= row_col_bank_next_w;
if (rst) scan_row <= 0;
if (mrst) scan_row <= 0;
else if (start_d) scan_row <= 0;
else if (pre_act) scan_row <= last_row?0:scan_row+1;
if (rst) scan_col <= 0;
if (mrst) scan_col <= 0;
else if (start_d) scan_col <= 0;
else if (pre_act && last_row) scan_col <= scan_col+1; // for ACTIVATE, not for READ
if (rst) first_col <= 0;
if (mrst) first_col <= 0;
else if (start_d) first_col <= 1;
else if (pre_act && last_row) first_col <= 0;
if (rst) last_col <= 0;
if (mrst) last_col <= 0;
else if (start_d) last_col <= num_cols128_m1==0; // if single column - will start with 1'b1;
else if (pre_act) last_col <= (scan_col==num_cols128_m1); // too early for READ ?
if (rst) enable_autopre <= 0;
if (mrst) enable_autopre <= 0;
else if (start_d) enable_autopre <= 0;
else if (pre_act) enable_autopre <= last_col || !keep_open; // delayed by 2 pre_act tacts form last_col, OK with a single column
if (rst) loop_continue<=0;
if (mrst) loop_continue<=0;
else loop_continue <= (scan_col==num_cols128_m1) && last_row;
if (rst) gen_addr <= 0;
if (mrst) gen_addr <= 0;
else if (!start_d && !gen_run) gen_addr <= 0;
else if ((gen_addr==LOOP_LAST) && !loop_continue) gen_addr <= LOOP_FIRST; // skip loop alltogeter
else gen_addr <= gen_addr+1; // not in a loop
......@@ -230,14 +227,13 @@ module cmd_encod_tiled_wr #(
end
// ROM-based (registered output) encoded sequence
always @ (posedge rst or posedge clk) begin
if (rst) rom_r <= 0;
always @ (posedge clk) begin
if (mrst) rom_r <= 0;
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) ; // here does not matter, just to work with masked ACTIVATE
4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) ;
4'h2: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL);
4'h3: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT);
// 4'h4: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN);
4'h4: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT);
4'h5: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
// start loop
......@@ -252,16 +248,14 @@ module cmd_encod_tiled_wr #(
default:rom_r <= 0;
endcase
end
always @ (posedge rst or posedge clk) begin
// if (rst) done <= 0;
// else done <= pre_done;
if (rst) enc_wr <= 0;
always @ (posedge clk) begin
if (mrst) enc_wr <= 0;
else enc_wr <= gen_run || gen_run; // gen_run_d; *****
if (rst) enc_done <= 0;
if (mrst) enc_done <= 0;
else enc_done <= enc_wr && !gen_run; // !gen_run_d; *****
if (rst) enc_cmd <= 0;
if (mrst) enc_cmd <= 0;
else if (gen_run) begin
if (rom_cmd[0] || (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
rom_cmd[1]? // activate
......@@ -304,7 +298,7 @@ module cmd_encod_tiled_wr #(
fifo_2regs #(
.WIDTH(COLADDR_NUMBER)
) fifo_2regs_i (
.rst (rst), // input
.mrst (rst), // input
.clk (clk), // input
.din (row_col_bank[COLADDR_NUMBER-1:0]), // input[15:0]
.wr(pre_act), // input
......
memctrl/ddr_refresh.v
View file @ b721ae66
......@@ -21,7 +21,7 @@
`timescale 1ns/1ps
module ddr_refresh(
input rst,
input mrst,
input clk,
input en,
input [7:0] refresh_period, // in 16*clk, 0 - disable refresh, turn off requests
......@@ -39,39 +39,39 @@ module ddr_refresh(
reg en_refresh;
reg en_r;
always @ (posedge rst or posedge clk) begin
if (rst) en_r <= 0;
always @ (posedge clk) begin
if (mrst) en_r <= 0;
else en_r <= en;
if (rst) en_refresh <= 0;
if (mrst) en_refresh <= 0;
else if (set) en_refresh <= (refresh_period != 0);
if (rst) pre_div <= 0;
if (mrst) pre_div <= 0;
else if (set || !en_refresh) pre_div <= 0;
else pre_div <= pre_div +1;
if (rst) cry <= 0;
if (mrst) cry <= 0;
else if (set) cry <= 0;
else cry <= (pre_div == 4'hf);
if (rst) period_cntr <= 0;
if (mrst) period_cntr <= 0;
else if (set) period_cntr <= 0;
else if (over) period_cntr <= refresh_period;
else if (cry) period_cntr <= period_cntr -1;
if (rst) refresh_due <= 0;
if (mrst) refresh_due <= 0;
else refresh_due <= over;
if (rst) pending_rq <= 0;
if (mrst) pending_rq <= 0;
else if (set) pending_rq <= 0;
else if ( refresh_due && !grant) pending_rq <= pending_rq+1;
else if (!refresh_due && grant) pending_rq <= pending_rq-1;
if (rst) want <= 0;
else want<= en_refresh && en_r && (pending_rq != 0);
if (mrst) want <= 0;
else want<= en_refresh && en_r && (pending_rq != 0);
if (rst) need <= 0;
else need <= en_refresh && en_r && (pending_rq[4:3] != 0);
if (mrst) need <= 0;
else need <= en_refresh && en_r && (pending_rq[4:3] != 0);
end
endmodule
memctrl/mcntrl393.v
View file @ b721ae66
......@@ -229,7 +229,10 @@ module mcntrl393 #(
input rst_in,
input clk_in,
output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
input mrst, // @posedge mclk synchronous reset - should not interrupt mclk generation
output locked, // to generate sync reset
output ref_clk, // global clock for idelay_ctrl calibration
output idelay_ctrl_reset,
// programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
......@@ -386,7 +389,7 @@ module mcntrl393 #(
localparam COL_WDTH = COLADDR_NUMBER-3; // number of column address bits in bursts
localparam FRAME_WBP1 = FRAME_WIDTH_BITS + 1;
wire rst=rst_in;
wire rrst=rst_in;
wire axi_rst=rst_in;
// Not yet connected
......@@ -816,8 +819,9 @@ module mcntrl393 #(
end
//axiwr_waddr
status_router16 status_router16_mctrl_top_i (
.rst (rst), // input
.rst (1'b0), // input
.clk (mclk), // input
.srst (mrst), // input
.db_in0 (status_mcontr_ad), // input[7:0]
.rq_in0 (status_mcontr_rq), // input
.start_in0 (status_mcontr_start), // output
......@@ -1045,7 +1049,7 @@ module mcntrl393 #(
.MCNTRL_SCANLINE_PENDING_CNTR_BITS (MCNTRL_SCANLINE_PENDING_CNTR_BITS),
.MCNTRL_SCANLINE_FRAME_PAGE_RESET (MCNTRL_SCANLINE_FRAME_PAGE_RESET)
) mcntrl_linear_wr_sensor_i (
.rst (rst), // input
.mrst (mrst), // input
.mclk (mclk), // input
.cmd_ad (cmd_sens_ad), // input[7:0]
.cmd_stb (cmd_sens_stb), // input
......@@ -1097,7 +1101,7 @@ module mcntrl393 #(
.MCNTRL_TILED_PENDING_CNTR_BITS(MCNTRL_TILED_PENDING_CNTR_BITS),
.MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET)
) mcntrl_tiled_rd_compressor_i (
.rst (rst), // input
.mrst (mrst), // input
.mclk (mclk), // input
.cmd_ad (cmd_cmprs_ad), // input[7:0]
.cmd_stb (cmd_cmprs_stb), // input
......@@ -1158,7 +1162,7 @@ module mcntrl393 #(
.MCNTRL_SCANLINE_PENDING_CNTR_BITS (MCNTRL_SCANLINE_PENDING_CNTR_BITS),
.MCNTRL_SCANLINE_FRAME_PAGE_RESET (MCNTRL_SCANLINE_FRAME_PAGE_RESET)
) mcntrl_linear_rw_chn1_i (
.rst (rst), // input
.mrst (mrst), // input
.mclk (mclk), // input
.cmd_ad (cmd_scanline_chn1_ad), // input[7:0]
.cmd_stb (cmd_scanline_chn1_stb), // input
......@@ -1208,7 +1212,7 @@ module mcntrl393 #(
.MCNTRL_SCANLINE_PENDING_CNTR_BITS (MCNTRL_SCANLINE_PENDING_CNTR_BITS),
.MCNTRL_SCANLINE_FRAME_PAGE_RESET (MCNTRL_SCANLINE_FRAME_PAGE_RESET)
) mcntrl_linear_rw_chn3_i (
.rst (rst), // input
.mrst (mrst), // input
.mclk (mclk), // input
.cmd_ad (cmd_scanline_chn3_ad), // input[7:0]
.cmd_stb (cmd_scanline_chn3_stb), // input
......@@ -1260,34 +1264,34 @@ module mcntrl393 #(
.MCNTRL_TILED_PENDING_CNTR_BITS(MCNTRL_TILED_PENDING_CNTR_BITS),
.MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET)
) mcntrl_tiled_rw_chn2_i (
.rst(rst), // input
.mclk(mclk), // input
.cmd_ad (cmd_tiled_chn2_ad), // input[7:0]
.cmd_stb (cmd_tiled_chn2_stb), // input
.status_ad (status_tiled_chn2_ad), // output[7:0]
.status_rq (status_tiled_chn2_rq), // output
.status_start (status_tiled_chn2_start), // input
.frame_start (frame_start_chn2), // input
.next_page (next_page_chn2), // input
.frame_done (frame_done_chn2), // output
.frame_finished (), // output
.line_unfinished (line_unfinished_chn2), // output[15:0]
.suspend (suspend_chn2), // input
.mrst (mrst), // input
.mclk (mclk), // input
.cmd_ad (cmd_tiled_chn2_ad), // input[7:0]
.cmd_stb (cmd_tiled_chn2_stb), // input
.status_ad (status_tiled_chn2_ad), // output[7:0]
.status_rq (status_tiled_chn2_rq), // output
.status_start (status_tiled_chn2_start), // input
.frame_start (frame_start_chn2), // input
.next_page (next_page_chn2), // input
.frame_done (frame_done_chn2), // output
.frame_finished (), // output
.line_unfinished (line_unfinished_chn2), // output[15:0]
.suspend (suspend_chn2), // input
.frame_number (frame_number_chn2),
.xfer_want (want_rq2), // output
.xfer_need (need_rq2), // output
.xfer_grant (channel_pgm_en2), // input
.xfer_start_rd (tiled_rw_chn2_start_rd16), // output
.xfer_start_wr (tiled_rw_chn2_start_wr16), // output
.xfer_start32_rd (tiled_rw_chn2_start_rd32), // output
.xfer_start32_wr (tiled_rw_chn2_start_wr32), // output
.xfer_bank (tiled_rw_chn2_bank), // output[2:0]
.xfer_row (tiled_rw_chn2_row), // output[14:0]
.xfer_col (tiled_rw_chn2_col), // output[6:0]
.rowcol_inc (tiled_rw_chn2_rowcol_inc), // output[13:0]
.num_rows_m1 (tiled_rw_chn2_num_rows_m1), // output[5:0]
.num_cols_m1 (tiled_rw_chn2_num_cols_m1), // output[5:0]
.keep_open (tiled_rw_chn2_keep_open), // output
.xfer_want (want_rq2), // output
.xfer_need (need_rq2), // output
.xfer_grant (channel_pgm_en2), // input
.xfer_start_rd (tiled_rw_chn2_start_rd16), // output
.xfer_start_wr (tiled_rw_chn2_start_wr16), // output
.xfer_start32_rd (tiled_rw_chn2_start_rd32), // output
.xfer_start32_wr (tiled_rw_chn2_start_wr32), // output
.xfer_bank (tiled_rw_chn2_bank), // output[2:0]
.xfer_row (tiled_rw_chn2_row), // output[14:0]
.xfer_col (tiled_rw_chn2_col), // output[6:0]
.rowcol_inc (tiled_rw_chn2_rowcol_inc), // output[13:0]
.num_rows_m1 (tiled_rw_chn2_num_rows_m1), // output[5:0]
.num_cols_m1 (tiled_rw_chn2_num_cols_m1), // output[5:0]
.keep_open (tiled_rw_chn2_keep_open), // output
.xfer_partial (tiled_rw_chn2_xfer_partial), // output
.xfer_page_done (seq_done2), // input
.xfer_page_rst_wr (xfer_reset_page2_wr), // output
......@@ -1316,39 +1320,39 @@ module mcntrl393 #(
.MCNTRL_TILED_PENDING_CNTR_BITS(MCNTRL_TILED_PENDING_CNTR_BITS),
.MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET)
) mcntrl_tiled_rw_chn4_i (
.rst(rst), // input
.mclk(mclk), // input
.cmd_ad (cmd_tiled_chn4_ad), // input[7:0]
.cmd_stb (cmd_tiled_chn4_stb), // input
.status_ad (status_tiled_chn4_ad), // output[7:0]
.status_rq (status_tiled_chn4_rq), // output
.status_start (status_tiled_chn4_start), // input
.frame_start (frame_start_chn4), // input
.next_page (next_page_chn4), // input
.frame_done (frame_done_chn4), // output
.frame_finished (), // output
.line_unfinished (line_unfinished_chn4), // output[15:0]
.suspend (suspend_chn4), // input
.frame_number (frame_number_chn4),
.xfer_want (want_rq4), // output
.xfer_need (need_rq4), // output
.xfer_grant (channel_pgm_en4), // input
.xfer_start_rd (tiled_rw_chn4_start_rd16), // output
.xfer_start_wr (tiled_rw_chn4_start_wr16), // output
.xfer_start32_rd (tiled_rw_chn4_start_rd32), // output
.xfer_start32_wr (tiled_rw_chn4_start_wr32), // output
.xfer_bank (tiled_rw_chn4_bank), // output[2:0]
.xfer_row (tiled_rw_chn4_row), // output[14:0]
.xfer_col (tiled_rw_chn4_col), // output[6:0]
.rowcol_inc (tiled_rw_chn4_rowcol_inc), // output[13:0]
.num_rows_m1 (tiled_rw_chn4_num_rows_m1), // output[5:0]
.num_cols_m1 (tiled_rw_chn4_num_cols_m1), // output[5:0]
.keep_open (tiled_rw_chn4_keep_open), // output
.mrst (mrst), // input
.mclk (mclk), // input
.cmd_ad (cmd_tiled_chn4_ad), // input[7:0]
.cmd_stb (cmd_tiled_chn4_stb), // input
.status_ad (status_tiled_chn4_ad), // output[7:0]
.status_rq (status_tiled_chn4_rq), // output
.status_start (status_tiled_chn4_start), // input
.frame_start (frame_start_chn4), // input
.next_page (next_page_chn4), // input
.frame_done (frame_done_chn4), // output
.frame_finished (), // output
.line_unfinished (line_unfinished_chn4), // output[15:0]
.suspend (suspend_chn4), // input
.frame_number (frame_number_chn4), // output [15:0]
.xfer_want (want_rq4), // output
.xfer_need (need_rq4), // output
.xfer_grant (channel_pgm_en4), // input
.xfer_start_rd (tiled_rw_chn4_start_rd16), // output
.xfer_start_wr (tiled_rw_chn4_start_wr16), // output
.xfer_start32_rd (tiled_rw_chn4_start_rd32), // output
.xfer_start32_wr (tiled_rw_chn4_start_wr32), // output
.xfer_bank (tiled_rw_chn4_bank), // output[2:0]
.xfer_row (tiled_rw_chn4_row), // output[14:0]
.xfer_col (tiled_rw_chn4_col), // output[6:0]
.rowcol_inc (tiled_rw_chn4_rowcol_inc), // output[13:0]
.num_rows_m1 (tiled_rw_chn4_num_rows_m1), // output[5:0]
.num_cols_m1 (tiled_rw_chn4_num_cols_m1), // output[5:0]
.keep_open (tiled_rw_chn4_keep_open), // output
.xfer_partial (tiled_rw_chn4_xfer_partial), // output
.xfer_page_done (seq_done4), // input
.xfer_page_rst_wr (xfer_reset_page4_wr), // output
.xfer_page_rst_rd (xfer_reset_page4_rd) // output
);
.xfer_page_done (seq_done4), // input
.xfer_page_rst_wr (xfer_reset_page4_wr), // output
.xfer_page_rst_rd (xfer_reset_page4_rd) // output
);
// PS-controlled launch of the memory controller sequences
......@@ -1360,7 +1364,7 @@ module mcntrl393 #(
.MCNTRL_PS_CMD (MCNTRL_PS_CMD), //'h1),
.MCNTRL_PS_STATUS_CNTRL (MCNTRL_PS_STATUS_CNTRL) //'h2)
) mcntrl_ps_pio_i (
.rst (rst), // input
.mrst (mrst), // input
.mclk (mclk), // input
.cmd_ad (cmd_ps_pio_ad), // input[7:0]
......@@ -1467,7 +1471,7 @@ module mcntrl393 #(
.RSEL (RSEL),
.WSEL (WSEL)
) cmd_encod_linear_rw_i (
.rst (rst), // input
.mrst (mrst), // input
.clk (mclk), // input
.bank_in (lin_rw_bank), // input[2:0]
.row_in (lin_rw_row), // input[14:0]
......@@ -1491,7 +1495,6 @@ module mcntrl393 #(
.MAX_TILE_HEIGHT (MAX_TILE_HEIGHT)
) cmd_encod_tiled_mux_i (
.clk (mclk), // input
.bank2 (tiled_rw_chn2_bank), // input[2:0]
.row2 (tiled_rw_chn2_row), // input[14:0]
.col2 (tiled_rw_chn2_col), // input[6:0]
......@@ -1587,9 +1590,9 @@ module mcntrl393 #(
.RSEL (RSEL),
.WSEL (WSEL)
) cmd_encod_tiled_16_rw_i (
.rst (rst), // input
.clk (mclk), // input
.start_bank (tiled_rw_bank), // input[2:0]
.mrst (mrst), // input
.clk (mclk), // input
.start_bank (tiled_rw_bank), // input[2:0]
.start_row (tiled_rw_row), // input[14:0]
.start_col (tiled_rw_col), // input[6:0]
.rowcol_inc_in (tiled_rw_rowcol_inc), // input[13:0] // [21:0]
......@@ -1739,7 +1742,10 @@ module mcntrl393 #(
.rst_in (rst_in), // input
.clk_in (clk_in), // input
.mclk (mclk), // output
.mrst (mrst), // input
.locked (locked), // output
.ref_clk (ref_clk), // output
.idelay_ctrl_reset (idelay_ctrl_reset), // output
.cmd_ad (cmd_mcontr_ad), // input[7:0]
.cmd_stb (cmd_mcontr_stb), // input
.status_ad (status_mcontr_ad[7:0]), // output[7:0]
......
memctrl/mcntrl393_test01.v
View file @ b721ae66
......@@ -37,7 +37,7 @@ module mcntrl393_test01#(
parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3e, // status/readback register for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3f // status/readback register for channel 4
)(
input rst,
input mrst,
input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
// programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
......@@ -163,65 +163,65 @@ module mcntrl393_test01#(
next_page_chn4_r <= set_chn4_mode && cmd_next_page_w;
end
always @ (posedge rst or posedge mclk) begin
if (rst) page_chn1 <= 0;
always @ (posedge mclk) begin
if (mrst) page_chn1 <= 0;
else if (frame_start_chn1_r) page_chn1 <= 0;
else if (page_ready_chn1) page_chn1 <= page_chn1 + 1;
if (rst) page_chn2 <= 0;
if (mrst) page_chn2 <= 0;
else if (frame_start_chn2_r) page_chn2 <= 0;
else if (page_ready_chn2) page_chn2 <= page_chn2 + 1;
if (rst) page_chn3 <= 0;
if (mrst) page_chn3 <= 0;
else if (frame_start_chn3_r) page_chn3 <= 0;
else if (page_ready_chn3) page_chn3 <= page_chn3 + 1;
if (rst) page_chn4 <= 0;
if (mrst) page_chn4 <= 0;
else if (frame_start_chn4_r) page_chn4 <= 0;
else if (page_ready_chn4) page_chn4 <= page_chn4 + 1;
if (rst) suspend_chn1_r <= 0;
if (mrst) suspend_chn1_r <= 0;
else if (set_chn1_mode) suspend_chn1_r <= cmd_suspend_w;
if (rst) suspend_chn2_r <= 0;
if (mrst) suspend_chn2_r <= 0;
else if (set_chn2_mode) suspend_chn2_r <= cmd_suspend_w;
if (rst) suspend_chn3_r <= 0;
if (mrst) suspend_chn3_r <= 0;
else if (set_chn3_mode) suspend_chn3_r <= cmd_suspend_w;
if (rst) suspend_chn4_r <= 0;
if (mrst) suspend_chn4_r <= 0;
else if (set_chn4_mode) suspend_chn4_r <= cmd_suspend_w;
if (rst) frame_busy_chn1 <= 0;
if (mrst) frame_busy_chn1 <= 0;
else if ( frame_start_chn1_r && !frame_done_chn1) frame_busy_chn1 <= 1;
else if (!frame_start_chn1_r && frame_done_chn1) frame_busy_chn1 <= 0;
if (rst) frame_busy_chn2 <= 0;
if (mrst) frame_busy_chn2 <= 0;
else if ( frame_start_chn2_r && !frame_done_chn2) frame_busy_chn2 <= 1;
else if (!frame_start_chn2_r && frame_done_chn2) frame_busy_chn2 <= 0;
if (rst) frame_busy_chn3 <= 0;
if (mrst) frame_busy_chn3 <= 0;
else if ( frame_start_chn3_r && !frame_done_chn3) frame_busy_chn3 <= 1;
else if (!frame_start_chn3_r && frame_done_chn3) frame_busy_chn3 <= 0;
if (rst) frame_busy_chn4 <= 0;
if (mrst) frame_busy_chn4 <= 0;
else if ( frame_start_chn4_r && !frame_done_chn4) frame_busy_chn4 <= 1;
else if (!frame_start_chn4_r && frame_done_chn4) frame_busy_chn4 <= 0;
if (rst) frame_finished_chn1 <= 0;
if (mrst) frame_finished_chn1 <= 0;
else if ( frame_start_chn1_r && !frame_done_chn1) frame_finished_chn1 <= 0;
else if (!frame_start_chn1_r && frame_done_chn1) frame_finished_chn1 <= 1;
if (rst) frame_finished_chn2 <= 0;
if (mrst) frame_finished_chn2 <= 0;
else if ( frame_start_chn2_r && !frame_done_chn2) frame_finished_chn2 <= 0;
else if (!frame_start_chn2_r && frame_done_chn2) frame_finished_chn2 <= 1;
if (rst) frame_finished_chn3 <= 0;
if (mrst) frame_finished_chn3 <= 0;
else if ( frame_start_chn3_r && !frame_done_chn3) frame_finished_chn3 <= 0;
else if (!frame_start_chn3_r && frame_done_chn3) frame_finished_chn3 <= 1;
if (rst) frame_finished_chn4 <= 0;
if (mrst) frame_finished_chn4 <= 0;
else if ( frame_start_chn4_r && !frame_done_chn4) frame_finished_chn4 <= 0;
else if (!frame_start_chn4_r && frame_done_chn4) frame_finished_chn4 <= 1;
end
......@@ -244,30 +244,32 @@ module mcntrl393_test01#(
.ADDR_WIDTH (4),
.DATA_WIDTH (8)
) cmd_deser_mcontr_test01_8bit_i (
.rst (rst), // input
.clk (mclk), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[15:0]
.data (cmd_data), // output[31:0]
.we (cmd_we) // output
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[15:0]
.data (cmd_data), // output[31:0]
.we (cmd_we) // output
);
status_router4 status_router4_i (
.rst (rst), // input
.clk (mclk), // input
.db_in0 (status_chn1_ad), // input[7:0]
.rq_in0 (status_chn1_rq), // input
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.db_in0 (status_chn1_ad), // input[7:0]
.rq_in0 (status_chn1_rq), // input
.start_in0 (status_chn1_start), // output
.db_in1 (status_chn2_ad), // input[7:0]
.rq_in1 (status_chn2_rq), // input
.db_in1 (status_chn2_ad), // input[7:0]
.rq_in1 (status_chn2_rq), // input
.start_in1 (status_chn2_start), // output
.db_in2 (status_chn3_ad), // input[7:0]
.rq_in2 (status_chn3_rq), // input
.db_in2 (status_chn3_ad), // input[7:0]
.rq_in2 (status_chn3_rq), // input
.start_in2 (status_chn3_start), // output
.db_in3 (status_chn4_ad), // input[7:0]
.rq_in3 (status_chn4_rq), // input
.db_in3 (status_chn4_ad), // input[7:0]
.rq_in3 (status_chn4_rq), // input
.start_in3 (status_chn4_start), // output
.db_out (status_ad), // output[7:0]
......@@ -279,13 +281,14 @@ module mcntrl393_test01#(
.STATUS_REG_ADDR(MCNTRL_TEST01_STATUS_REG_CHN1_ADDR),
.PAYLOAD_BITS(STATUS_PAYLOAD_BITS)
) status_generate_chn1_i (
.rst (rst), // input
.clk (mclk), // input
.we (set_chn1_status), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_chn1), // input[25:0]
.ad (status_chn1_ad), // output[7:0]
.rq (status_chn1_rq), // output
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (set_chn1_status), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_chn1), // input[25:0]
.ad (status_chn1_ad), // output[7:0]
.rq (status_chn1_rq), // output
.start (status_chn1_start) // input
);
......@@ -293,13 +296,14 @@ module mcntrl393_test01#(
.STATUS_REG_ADDR(MCNTRL_TEST01_STATUS_REG_CHN2_ADDR),
.PAYLOAD_BITS(STATUS_PAYLOAD_BITS)
) status_generate_chn2_i (
.rst (rst), // input
.clk (mclk), // input
.we (set_chn2_status), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_chn2), // input[25:0]
.ad (status_chn2_ad), // output[7:0]
.rq (status_chn2_rq), // output
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (set_chn2_status), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_chn2), // input[25:0]
.ad (status_chn2_ad), // output[7:0]
.rq (status_chn2_rq), // output
.start (status_chn2_start) // input
);
......@@ -307,13 +311,14 @@ module mcntrl393_test01#(
.STATUS_REG_ADDR(MCNTRL_TEST01_STATUS_REG_CHN3_ADDR),
.PAYLOAD_BITS(STATUS_PAYLOAD_BITS)
) status_generate_chn3_i (
.rst (rst), // input
.clk (mclk), // input
.we (set_chn3_status), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_chn3), // input[25:0]
.ad (status_chn3_ad), // output[7:0]
.rq (status_chn3_rq), // output
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (set_chn3_status), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_chn3), // input[25:0]
.ad (status_chn3_ad), // output[7:0]
.rq (status_chn3_rq), // output
.start (status_chn3_start) // input
);
......@@ -321,13 +326,14 @@ module mcntrl393_test01#(
.STATUS_REG_ADDR(MCNTRL_TEST01_STATUS_REG_CHN4_ADDR),
.PAYLOAD_BITS(STATUS_PAYLOAD_BITS)
) status_generate_chn4_i (
.rst (rst), // input
.clk (mclk), // input
.we (set_chn4_status), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_chn4), // input[25:0]
.ad (status_chn4_ad), // output[7:0]
.rq (status_chn4_rq), // output
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (set_chn4_status), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_chn4), // input[25:0]
.ad (status_chn4_ad), // output[7:0]
.rq (status_chn4_rq), // output
.start (status_chn4_start) // input
);
......
memctrl/mcntrl_linear_rw.v
View file @ b721ae66
......@@ -50,7 +50,7 @@ module mcntrl_linear_rw #(
parameter MCNTRL_SCANLINE_FRAME_PAGE_RESET =1'b0 // reset internal page number to zero at the frame start (false - only when hard/soft reset)
// parameter MCNTRL_SCANLINE_WRITE_MODE = 1'b0 // module is configured to write tiles to external memory (false - read tiles)
)(
input rst,
input mrst,
input mclk,
// programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
......@@ -215,59 +215,59 @@ module mcntrl_linear_rw #(
assign rst_frame_num_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_MODE) && cmd_data[8];
// Set parameter registers
always @(posedge rst or posedge mclk) begin
if (rst) mode_reg <= 0;
always @(posedge mclk) begin
if (mrst) mode_reg <= 0;
else if (set_mode_w) mode_reg <= cmd_data[10:0]; // 4:0]; // [4:0];
if (rst) single_frame_r <= 0;
else single_frame_r <= single_frame_w;
if (mrst) single_frame_r <= 0;
else single_frame_r <= single_frame_w;
if (rst) rst_frame_num_r <= 0;
else rst_frame_num_r <= {rst_frame_num_r[0],
if (mrst) rst_frame_num_r <= 0;
else rst_frame_num_r <= {rst_frame_num_r[0],
rst_frame_num_w |
set_start_addr_w |
set_last_frame_w |
set_frame_size_w};
if (rst) start_range_addr <= 0;
if (mrst) start_range_addr <= 0;
else if (set_start_addr_w) start_range_addr <= cmd_data[NUM_RC_BURST_BITS-1:0];
if (rst) frame_size <= 0;
if (mrst) frame_size <= 0;
else if (set_start_addr_w) frame_size <= 1; // default number of frames - just one
else if (set_frame_size_w) frame_size <= cmd_data[NUM_RC_BURST_BITS-1:0];
if (rst) last_frame_number <= 0;
if (mrst) last_frame_number <= 0;
else if (set_last_frame_w) last_frame_number <= cmd_data[LAST_FRAME_BITS-1:0];
if (rst) frame_full_width <= 0;
if (mrst) frame_full_width <= 0;
else if (set_frame_width_w) frame_full_width <= {lsw13_zero,cmd_data[FRAME_WIDTH_BITS-1:0]};
if (rst) is_last_frame <= 0;
else is_last_frame <= frame_number_cntr == last_frame_number;
if (mrst) is_last_frame <= 0;
else is_last_frame <= frame_number_cntr == last_frame_number;
if (rst) frame_start_r <= 0;
else frame_start_r <= {frame_start_r[3:0], frame_start & frame_en};
if (mrst) frame_start_r <= 0;
else frame_start_r <= {frame_start_r[3:0], frame_start & frame_en};
if (rst) frame_en <= 0;
if (mrst) frame_en <= 0;
else if (single_frame_r || repeat_frames) frame_en <= 1;
else if (frame_start) frame_en <= 0;
if (rst) frame_number_cntr <= 0;
if (mrst) frame_number_cntr <= 0;
else if (rst_frame_num_r[0]) frame_number_cntr <= 0;
else if (frame_start_r[2]) frame_number_cntr <= is_last_frame?{LAST_FRAME_BITS{1'b0}}:(frame_number_cntr+1);
if (rst) frame_number_current <= 0;
if (mrst) frame_number_current <= 0;
else if (rst_frame_num_r[0]) frame_number_current <= 0;
else if (frame_start_r[2]) frame_number_current <= frame_number_cntr;
if (rst) next_frame_start_addr <= start_range_addr; // just to use rst
if (mrst) next_frame_start_addr <= start_range_addr; // just to use rst
else if (rst_frame_num_r[1]) next_frame_start_addr <= start_range_addr;
else if (frame_start_r[2]) next_frame_start_addr <= is_last_frame? start_range_addr : (start_addr+frame_size);
if (rst) start_addr <= start_range_addr; // just to use rst
if (mrst) start_addr <= start_range_addr; // just to use rst
else if (frame_start_r[0]) start_addr <= next_frame_start_addr;
if (rst) begin
if (mrst) begin
window_width <= 0;
window_height <= 0;
end else if (set_window_wh_w) begin
......@@ -275,7 +275,7 @@ module mcntrl_linear_rw #(
window_height <= {msw_zero,cmd_data[FRAME_HEIGHT_BITS+15:16]};
end
if (rst) begin
if (mrst) begin
window_x0 <= 0;
window_y0 <= 0;
end else if (set_window_x0y0_w) begin
......@@ -283,7 +283,7 @@ module mcntrl_linear_rw #(
window_y0 <=cmd_data[FRAME_HEIGHT_BITS+15:16];
end
if (rst) begin
if (mrst) begin
start_x <= 0;
start_y <= 0;
end else if (set_window_start_w) begin
......@@ -386,88 +386,88 @@ module mcntrl_linear_rw #(
wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
// now have row start address, bank and row_left ;
// calculate number to read (min of row_left, maximal xfer and what is left in the DDR3 page
always @(posedge rst or posedge mclk) begin
if (rst) par_mod_r<=0;
always @(posedge mclk) begin
if (mrst) par_mod_r<=0;
else if (pgm_param_w ||
xfer_start_r[0] ||
chn_rst ||
frame_start_r[0]) par_mod_r<=0;
else par_mod_r <= {par_mod_r[PAR_MOD_LATENCY-2:0], 1'b1};
if (rst) chn_rst_d <= 0;
if (mrst) chn_rst_d <= 0;
else chn_rst_d <= chn_rst;
if (rst) recalc_r<=0;
if (mrst) recalc_r<=0;
else if (chn_rst) recalc_r<=0;
else recalc_r <= {recalc_r[PAR_MOD_LATENCY-2:0],
((xfer_start_r[0] | frame_start_r[0]) & ~chn_rst) | pgm_param_w | (chn_rst_d & ~chn_rst)};
if (rst) busy_r <= 0;
if (mrst) busy_r <= 0;
else if (chn_rst) busy_r <= 0;
else if (frame_start_r[0]) busy_r <= 1;
else if (frame_done_r) busy_r <= 0;
if (rst) xfer_done_d <= 0;
if (mrst) xfer_done_d <= 0;
else xfer_done_d <= xfer_done;
if (rst) continued_xfer <= 1'b0;
if (mrst) continued_xfer <= 1'b0;
else if (chn_rst) continued_xfer <= 1'b0;
else if (frame_start_r[0]) continued_xfer <= 1'b0;
else if (xfer_start_r[0]) continued_xfer <= xfer_limited_by_mem_page_r; // only set after actual start if it was partial, not after parameter change
// single cycle (sent out)
if (rst) frame_done_r <= 0;
if (mrst) frame_done_r <= 0;
else frame_done_r <= busy_r && last_block && xfer_done_d && (pending_xfers==0);
// turns and stays on (used in status)
if (rst) frame_finished_r <= 0;
if (mrst) frame_finished_r <= 0;
else if (chn_rst || frame_start_r[0]) frame_finished_r <= 0;
else if (frame_done_r) frame_finished_r <= 1;
if (rst) xfer_start_r <= 0;
else xfer_start_r <= {xfer_start_r[1:0],xfer_grant && !chn_rst};
if (mrst) xfer_start_r <= 0;
else xfer_start_r <= {xfer_start_r[1:0],xfer_grant && !chn_rst};
if (rst) xfer_start_rd_r <= 0;
else xfer_start_rd_r <= xfer_grant && !chn_rst && !cmd_wrmem;
if (mrst) xfer_start_rd_r <= 0;
else xfer_start_rd_r <= xfer_grant && !chn_rst && !cmd_wrmem;
if (rst) xfer_start_wr_r <= 0;
else xfer_start_wr_r <= xfer_grant && !chn_rst && cmd_wrmem;
if (mrst) xfer_start_wr_r <= 0;
else xfer_start_wr_r <= xfer_grant && !chn_rst && cmd_wrmem;
if (rst) need_r <= 0;
if (mrst) need_r <= 0;
else if (chn_rst || xfer_grant) need_r <= 0;
else if ((pre_want || want_r) && (page_cntr>=3)) need_r <= 1; // may raise need if want was already set
if (rst) want_r <= 0;
if (mrst) want_r <= 0;
else if (chn_rst || xfer_grant) want_r <= 0;
else if (pre_want && (page_cntr>{1'b0,cmd_extra_pages})) want_r <= 1;
if (rst) page_cntr <= 0;
if (mrst) page_cntr <= 0;
else if (frame_start_r[0]) page_cntr <= cmd_wrmem?0:4; // What about last pages (like if only 1 page is needed)? Early frame end?
else if ( start_not_partial && !next_page) page_cntr <= page_cntr - 1;
else if (!start_not_partial && next_page) page_cntr <= page_cntr + 1;
if (rst) xfer_page_rst_r <= 1;
else xfer_page_rst_r <= chn_rst || (MCNTRL_SCANLINE_FRAME_PAGE_RESET ? (frame_start_r[0] & cmd_wrmem):1'b0);
if (mrst) xfer_page_rst_r <= 1;
else xfer_page_rst_r <= chn_rst || (MCNTRL_SCANLINE_FRAME_PAGE_RESET ? (frame_start_r[0] & cmd_wrmem):1'b0);
if (rst) xfer_page_rst_pos <= 1;
else xfer_page_rst_pos <= chn_rst || (MCNTRL_SCANLINE_FRAME_PAGE_RESET ? (frame_start_r[0] & ~cmd_wrmem):1'b0);
if (mrst) xfer_page_rst_pos <= 1;
else xfer_page_rst_pos <= chn_rst || (MCNTRL_SCANLINE_FRAME_PAGE_RESET ? (frame_start_r[0] & ~cmd_wrmem):1'b0);
// increment x,y (two cycles)
if (rst) curr_x <= 0;
if (mrst) curr_x <= 0;
else if (chn_rst || frame_start_r[0]) curr_x <= start_x;
else if (xfer_start_r[0]) curr_x <= last_in_row?0: curr_x + xfer_num128_r;
if (rst) curr_y <= 0;
if (mrst) curr_y <= 0;
else if (chn_rst || frame_start_r[0]) curr_y <= start_y;
else if (xfer_start_r[0] && last_in_row) curr_y <= next_y[FRAME_HEIGHT_BITS-1:0];
if (rst) last_block <= 0;
if (mrst) last_block <= 0;
else if (chn_rst || !busy_r) last_block <= 0;
else if (xfer_start_r[0]) last_block <= last_row_w && last_in_row_w;
if (rst) pending_xfers <= 0;
if (mrst) pending_xfers <= 0;
else if (chn_rst || !busy_r) pending_xfers <= 0;
else if ( xfer_start_r[0] && !xfer_done) pending_xfers <= pending_xfers + 1;
else if (!xfer_start_r[0] && xfer_done) pending_xfers <= pending_xfers - 1;
......@@ -475,11 +475,11 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
//line_unfinished_r cmd_wrmem
if (rst) line_unfinished_r[0] <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
if (mrst) line_unfinished_r[0] <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
else if (chn_rst || frame_start_r[0]) line_unfinished_r[0] <= window_y0+start_y;
else if (xfer_start_r[2]) line_unfinished_r[0] <= window_y0+next_y[FRAME_HEIGHT_BITS-1:0]; // latency 2 from xfer_start
if (rst) line_unfinished_r[1] <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
if (mrst) line_unfinished_r[1] <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
// else if (chn_rst || frame_start_r[0]) line_unfinished_r[1] <= window_y0+start_y;
else if (chn_rst || frame_start_r[2]) line_unfinished_r[1] <= window_y0+start_y; // _r[0] -> _r[2] to make it simultaneous with frame_number
// in read mode advance line number ASAP
......@@ -498,27 +498,29 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
.ADDR_WIDTH (4),
.DATA_WIDTH (32)
) cmd_deser_32bit_i (
.rst (rst), // input
.clk (mclk), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[15:0]
.data (cmd_data), // output[31:0]
.we (cmd_we) // output
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[15:0]
.data (cmd_data), // output[31:0]
.we (cmd_we) // output
);
status_generate #(
.STATUS_REG_ADDR (MCNTRL_SCANLINE_STATUS_REG_ADDR),
.PAYLOAD_BITS (2)
) status_generate_i (
.rst (rst), // input
.clk (mclk), // input
.we (set_status_w), // input
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (set_status_w), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_data), // input[25:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
.status (status_data), // input[25:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
);
endmodule
memctrl/mcntrl_ps_pio.v
View file @ b721ae66
......@@ -30,7 +30,7 @@ module mcntrl_ps_pio#(
parameter MCNTRL_PS_CMD= 'h1,
parameter MCNTRL_PS_STATUS_CNTRL= 'h2
)(
input rst,
input mrst,
input mclk,
// programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
......@@ -136,21 +136,23 @@ reg page_w_set_negedge;
assign set_status_w = cmd_we && (cmd_a== MCNTRL_PS_STATUS_CNTRL);
assign set_en_rst = cmd_we && (cmd_a== MCNTRL_PS_EN_RST);
//PAGE_CNTR_BITS
always @ (posedge rst or posedge mclk) begin
always @ (posedge mclk) begin
if (rst) pending_pages <= 0;
if (mrst) pending_pages <= 0;
else if (chn_rst) pending_pages <= 0;
else if ( cmd_set && !seq_done) pending_pages <= pending_pages + 1;
else if (!cmd_set && seq_done) pending_pages <= pending_pages - 1;
if (rst) nreset_page_fifo <= 0;
else nreset_page_fifo <= cmd_nempty | busy;
if (rst) cmd_wait_r <= 0;
if (mrst) nreset_page_fifo <= 0;
else nreset_page_fifo <= cmd_nempty | busy;
if (mrst) cmd_wait_r <= 0;
else if (channel_pgm_en) cmd_wait_r <= cmd_wait;
if (rst) en_reset <= 0;
if (mrst) en_reset <= 0;
else if (set_en_rst) en_reset <= cmd_data[1:0];
if (rst) begin
if (mrst) begin
want_rq <= 0;
need_rq <= 0;
end else if (chn_rst || channel_pgm_en) begin
......@@ -162,13 +164,12 @@ reg page_w_set_negedge;
end
if (rst) cmd_set <= 0;
if (mrst) cmd_set <= 0;
else if (chn_rst) cmd_set <= 0;
else cmd_set <= channel_pgm_en;
if (rst) cmd_set_d <= 0;
// else cmd_set_d <= {cmd_set_d[0],cmd_set& ~cmd_chn}; // only for channel0 (memory read)
if (mrst) cmd_set_d <= 0;
else cmd_set_d <= {cmd_set_d[0],cmd_set & ~cmd_wr}; // only for channel0 (memory read)
end
......@@ -180,36 +181,38 @@ reg page_w_set_negedge;
.ADDR_WIDTH (5),
.DATA_WIDTH (32)
) cmd_deser_mcontr_32bit_i (
.rst (rst), // input
.clk (mclk), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[15:0]
.data (cmd_data), // output[31:0]
.we (cmd_we) // output
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[15:0]
.data (cmd_data), // output[31:0]
.we (cmd_we) // output
);
status_generate #(
.STATUS_REG_ADDR (MCNTRL_PS_STATUS_REG_ADDR),
.PAYLOAD_BITS (2)
) status_generate_i (
.rst (rst), // input
.clk (mclk), // input
.we (set_status_w), // input
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (set_status_w), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_data), // input[25:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
.status (status_data), // input[25:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
);
fifo_same_clock #(
.DATA_WIDTH(CMD_WIDTH),
.DATA_DEPTH(CMD_FIFO_DEPTH)
) cmd_fifo_i (
.rst (rst),
.rst (1'b0),
.clk (mclk),
.sync_rst(chn_rst), // synchronously reset fifo;
.sync_rst (chn_rst), // synchronously reset fifo;
.we (set_cmd_w),
.re (cmd_set),
.data_in (cmd_data[CMD_WIDTH-1:0]),
......@@ -266,9 +269,9 @@ fifo_same_clock #(
.DATA_WIDTH(3),
.DATA_DEPTH(PAGE_FIFO_DEPTH)
) page_fifo1_i (
.rst (rst),
.rst (1'b0),
.clk (mclk), // posedge
.sync_rst (!nreset_page_fifo), // synchronously reset fifo;
.sync_rst (mrst || !nreset_page_fifo), // synchronously reset fifo;
.we (channel_pgm_en),
.re (buf_run),
.data_in ({cmd_wr,cmd_page}), //page),
......@@ -277,8 +280,8 @@ fifo_same_clock #(
.half_full ()
);
always @ (posedge rst or posedge mclk) begin
if (rst) page_out_r <= 0;
always @ (posedge mclk) begin
if (mrst) page_out_r <= 0;
else if (buf_run) page_out_r <= page_out;
......
memctrl/mcntrl_tiled_rw.v
View file @ b721ae66
......@@ -55,7 +55,7 @@ module mcntrl_tiled_rw#(
parameter MCNTRL_TILED_FRAME_PAGE_RESET =1'b0 // reset internal page number to zero at the frame start (false - only when hard/soft reset)
// parameter MCNTRL_TILED_WRITE_MODE = 1'b0 // module is configured to write tiles to external memory (false - read tiles)
)(
input rst,
input mrst,
input mclk,
// programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
......@@ -247,60 +247,60 @@ module mcntrl_tiled_rw#(
//
// Set parameter registers
always @(posedge rst or posedge mclk) begin
if (rst) mode_reg <= 0;
always @(posedge mclk) begin
if (mrst) mode_reg <= 0;
else if (set_mode_w) mode_reg <= cmd_data[10:0]; // [5:0];
if (rst) single_frame_r <= 0;
else single_frame_r <= single_frame_w;
if (mrst) single_frame_r <= 0;
else single_frame_r <= single_frame_w;
if (rst) rst_frame_num_r <= 0;
else rst_frame_num_r <= {rst_frame_num_r[0],
if (mrst) rst_frame_num_r <= 0;
else rst_frame_num_r <= {rst_frame_num_r[0],
rst_frame_num_w |
set_start_addr_w |
set_last_frame_w |
set_frame_size_w};
if (rst) start_range_addr <= 0;
if (mrst) start_range_addr <= 0;
else if (set_start_addr_w) start_range_addr <= cmd_data[NUM_RC_BURST_BITS-1:0];
if (rst) frame_size <= 0;
if (mrst) frame_size <= 0;
else if (set_start_addr_w) frame_size <= 1; // default number of frames - just one
else if (set_frame_size_w) frame_size <= cmd_data[NUM_RC_BURST_BITS-1:0];
if (rst) last_frame_number <= 0;
if (mrst) last_frame_number <= 0;
else if (set_last_frame_w) last_frame_number <= cmd_data[LAST_FRAME_BITS-1:0];
if (rst) frame_full_width <= 0;
if (mrst) frame_full_width <= 0;
else if (set_frame_width_w) frame_full_width <= {lsw13_zero,cmd_data[FRAME_WIDTH_BITS-1:0]};
if (rst) is_last_frame <= 0;
if (mrst) is_last_frame <= 0;
else is_last_frame <= frame_number_cntr == last_frame_number;
if (rst) frame_start_r <= 0;
if (mrst) frame_start_r <= 0;
else frame_start_r <= {frame_start_r[3:0], frame_start & frame_en};
if (rst) frame_en <= 0;
if (mrst) frame_en <= 0;
else if (single_frame_r || repeat_frames) frame_en <= 1;
else if (frame_start) frame_en <= 0;
if (rst) frame_number_cntr <= 0;
if (mrst) frame_number_cntr <= 0;
else if (rst_frame_num_r[0]) frame_number_cntr <= 0;
else if (frame_start_r[2]) frame_number_cntr <= is_last_frame?{LAST_FRAME_BITS{1'b0}}:(frame_number_cntr+1);
if (rst) frame_number_current <= 0;
if (mrst) frame_number_current <= 0;
else if (rst_frame_num_r[0]) frame_number_current <= 0;
else if (frame_start_r[2]) frame_number_current <= frame_number_cntr;
if (rst) next_frame_start_addr <= start_range_addr; // just to use rst
if (mrst) next_frame_start_addr <= start_range_addr; // just to use rst
else if (rst_frame_num_r[1]) next_frame_start_addr <= start_range_addr;
else if (frame_start_r[2]) next_frame_start_addr <= is_last_frame? start_range_addr : (start_addr+frame_size);
if (rst) start_addr <= start_range_addr; // just to use rst
if (mrst) start_addr <= start_range_addr; // just to use rst
else if (frame_start_r[0]) start_addr <= next_frame_start_addr;
if (rst) begin
if (mrst) begin
window_width <= 0;
window_height <= 0;
end else if (set_window_wh_w) begin
......@@ -308,18 +308,17 @@ module mcntrl_tiled_rw#(
window_height <= {msw_zero,cmd_data[FRAME_HEIGHT_BITS+15:16]};
end
if (rst) begin
if (mrst) begin
tile_cols <= 0;
tile_rows <= 0;
tile_vstep <= 0;
end else if (set_tile_whs_w) begin
tile_cols <= {tile_width_zero, cmd_data[ 0+:MAX_TILE_WIDTH]};
// tile_rows <= {tile_height_zero, cmd_data[ 8+:MAX_TILE_HEIGHT]};
tile_rows <= { cmd_data[ 8+:MAX_TILE_HEIGHT]};
tile_vstep <= {tile_vstep_zero, cmd_data[16+:MAX_TILE_HEIGHT]};
end
if (rst) begin
if (mrst) begin
window_x0 <= 0;
window_y0 <= 0;
end else if (set_window_x0y0_w) begin
......@@ -327,7 +326,7 @@ module mcntrl_tiled_rw#(
window_y0 <=cmd_data[FRAME_HEIGHT_BITS+15:16];
end
if (rst) begin
if (mrst) begin
start_x <= 0;
start_y <= 0;
end else if (set_window_start_w) begin
......@@ -345,12 +344,9 @@ module mcntrl_tiled_rw#(
assign calc_valid= par_mod_r[PAR_MOD_LATENCY-1]; // MSB, longest 0
assign frame_done= frame_done_r;
assign frame_finished= frame_finished_r;
// assign pre_want= chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend && !frame_start_r[0];
assign pre_want= chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend && !(|frame_start_r);
assign last_in_row_w=(row_left=={{(FRAME_WIDTH_BITS-MAX_TILE_WIDTH){1'b0}},num_cols_r}); // what if it crosses page? OK, num_cols_r & row_left know that
// assign last_row_w= next_y>=window_height; // (next_y==window_height) is faster, but will not forgive software errors
// tiles must completely fit window
// assign last_row_w= next_y > window_m_tile_height; // (next_y==window_height) is faster, but will not forgive software errors
// all window should be covered (tiles may extend):
assign last_row_w= next_y>=window_height;
//window_m_tile_height
......@@ -360,7 +356,6 @@ module mcntrl_tiled_rw#(
assign xfer_row= row_col_r[NUM_RC_BURST_BITS-1:COLADDR_NUMBER-3] ; // memory row
assign xfer_col= row_col_r[COLADDR_NUMBER-4:0]; // start memory column in 8-bursts
assign line_unfinished=line_unfinished_r[1];
// assign line_unfinished=line_unfinished_r1;
assign chn_en = &mode_reg[1:0]; // enable requests by channel (continue ones in progress)
assign chn_rst = ~mode_reg[0]; // resets command, including fifo;
assign cmd_wrmem = mode_reg[2];// 0: read from memory, 1:write to memory
......@@ -368,7 +363,6 @@ module mcntrl_tiled_rw#(
assign keep_open= mode_reg[5]; // keep banks open (will be used only if number of rows <= 8
assign byte32= mode_reg[6]; // use 32-byte wide columns in each tile (false - 16-byte)
assign repeat_frames= mode_reg[10];
// reg [10:0] mode_reg;//mode register: {repet,single,rst_frame,na,byte32,keep_open,extra_pages[1:0],write_mode,enable,!reset}
assign status_data= {frame_finished_r, busy_r};
......@@ -380,15 +374,12 @@ module mcntrl_tiled_rw#(
assign num_rows_m1= num_rows_m1_w[MAX_TILE_HEIGHT-1:0]; // remove MSB
assign remainder_tile_width = {EXTRA_BITS,lim_by_tile_width}-mem_page_left;
// assign buf_skip_reset= continued_tile; // buf_skip_reset_r;
// assign xfer_page_rst= xfer_page_rst_r;
assign xfer_page_rst_wr= xfer_page_rst_r;
assign xfer_page_rst_rd= xfer_page_rst_neg;
assign xfer_partial= xfer_limited_by_mem_page_r;
integer i;
// localparam EXTRA_BITS={COLADDR_NUMBER-3-NUM_XFER_BITS{1'b0}};
localparam [COLADDR_NUMBER-3-MAX_TILE_WIDTH-1:0] EXTRA_BITS=0;
wire xfer_limited_by_mem_page;
reg xfer_limited_by_mem_page_r;
......@@ -398,7 +389,6 @@ module mcntrl_tiled_rw#(
if (recalc_r[0]) begin
frame_x <= curr_x + window_x0;
frame_y <= curr_y + window_y0;
// next_y <= curr_y + tile_rows;
next_y <= curr_y + tile_vstep;
row_left <= window_width - curr_x; // 14 bits - 13 bits
end
......@@ -411,7 +401,6 @@ module mcntrl_tiled_rw#(
// TODO: Verify MPY/register timing above
if (recalc_r[5]) begin // cycle 6
row_col_r <= line_start_addr+frame_x;
// line_start_page_left <= {COLADDR_NUMBER-3{1'b0}} - line_start_addr[COLADDR_NUMBER-4:0]; // 7 bits
line_start_page_left <= - line_start_addr[COLADDR_NUMBER-4:0]; // 7 bits
end
bank_reg[0] <= frame_y[2:0]; //TODO: is it needed - a pipeline for the bank? - remove!
......@@ -435,126 +424,109 @@ module mcntrl_tiled_rw#(
if (recalc_r[8]) begin // cycle 9
last_in_row <= last_in_row_w;
end
// window_m_tile_height <= window_height - tile_rows;
end
// now have row start address, bank and row_left ;
// calculate number to read (min of row_left, maximal xfer and what is left in the DDR3 page
wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
always @(posedge rst or posedge mclk) begin
if (rst) par_mod_r<=0;
always @(posedge mclk) begin
if (mrst) par_mod_r<=0;
else if (pgm_param_w ||
xfer_start_r[0] ||
chn_rst ||
frame_start_r[0]) par_mod_r<=0;
else par_mod_r <= {par_mod_r[PAR_MOD_LATENCY-2:0], 1'b1};
if (rst) chn_rst_d <= 0;
if (mrst) chn_rst_d <= 0;
else chn_rst_d <= chn_rst;
if (rst) recalc_r<=0;
if (mrst) recalc_r<=0;
else if (chn_rst) recalc_r<=0;
// else recalc_r <= {recalc_r[PAR_MOD_LATENCY-2:0], (xfer_grant & ~chn_rst) | pgm_param_w | (chn_rst_d & ~chn_rst)};
else recalc_r <= {recalc_r[PAR_MOD_LATENCY-2:0],
((xfer_start_r[0] | frame_start_r[0]) & ~chn_rst) | pgm_param_w | (chn_rst_d & ~chn_rst)};
if (rst) busy_r <= 0;
if (mrst) busy_r <= 0;
else if (chn_rst) busy_r <= 0;
else if (frame_start_r[0]) busy_r <= 1;
else if (frame_done_r) busy_r <= 0;
if (rst) xfer_page_done_d <= 0;
else xfer_page_done_d <= xfer_page_done;
if (mrst) xfer_page_done_d <= 0;
else xfer_page_done_d <= xfer_page_done;
if (rst) xfer_start_r <= 0;
else xfer_start_r <= {xfer_start_r[1:0],xfer_grant && !chn_rst};
if (mrst) xfer_start_r <= 0;
else xfer_start_r <= {xfer_start_r[1:0],xfer_grant && !chn_rst};
if (rst) xfer_start_rd_r <= 0;
else xfer_start_rd_r <= xfer_grant && !chn_rst && !cmd_wrmem && !byte32;
if (mrst) xfer_start_rd_r <= 0;
else xfer_start_rd_r <= xfer_grant && !chn_rst && !cmd_wrmem && !byte32;
if (rst) xfer_start_wr_r <= 0;
else xfer_start_wr_r <= xfer_grant && !chn_rst && cmd_wrmem && !byte32;
if (mrst) xfer_start_wr_r <= 0;
else xfer_start_wr_r <= xfer_grant && !chn_rst && cmd_wrmem && !byte32;
if (rst) xfer_start32_rd_r <= 0;
else xfer_start32_rd_r <= xfer_grant && !chn_rst && !cmd_wrmem && byte32;
if (mrst) xfer_start32_rd_r <= 0;
else xfer_start32_rd_r <= xfer_grant && !chn_rst && !cmd_wrmem && byte32;
if (rst) xfer_start32_wr_r <= 0;
if (mrst) xfer_start32_wr_r <= 0;
else xfer_start32_wr_r <= xfer_grant && !chn_rst && cmd_wrmem && byte32;
if (rst) continued_tile <= 1'b0;
if (mrst) continued_tile <= 1'b0;
else if (chn_rst) continued_tile <= 1'b0;
else if (frame_start_r[0]) continued_tile <= 1'b0;
else if (xfer_start_r[0]) continued_tile <= xfer_limited_by_mem_page_r; // only set after actual start if it was partial, not after parameter change
if (rst) need_r <= 0;
if (mrst) need_r <= 0;
else if (chn_rst || xfer_grant) need_r <= 0;
else if ((pre_want || want_r) && (page_cntr>=3)) need_r <= 1; // may raise need if want was already set
if (rst) want_r <= 0;
if (mrst) want_r <= 0;
else if (chn_rst || xfer_grant) want_r <= 0;
else if (pre_want && (page_cntr>{1'b0,cmd_extra_pages})) want_r <= 1;
if (rst) page_cntr <= 0;
if (mrst) page_cntr <= 0;
else if (frame_start_r[0]) page_cntr <= cmd_wrmem?0:4;
// else if ( xfer_start_r[0] && !next_page) page_cntr <= page_cntr + 1;
// else if (!xfer_start_r[0] && next_page) page_cntr <= page_cntr - 1;
else if ( start_not_partial && !next_page) page_cntr <= page_cntr - 1;
else if (!start_not_partial && next_page) page_cntr <= page_cntr + 1;
if (rst) xfer_page_rst_r <= 1;
if (mrst) xfer_page_rst_r <= 1;
else xfer_page_rst_r <= chn_rst || (MCNTRL_TILED_FRAME_PAGE_RESET ? (frame_start_r[0] & cmd_wrmem):1'b0);
if (rst) xfer_page_rst_pos <= 1;
if (mrst) xfer_page_rst_pos <= 1;
else xfer_page_rst_pos <= chn_rst || (MCNTRL_TILED_FRAME_PAGE_RESET ? (frame_start_r[0] & ~cmd_wrmem):1'b0);
// increment x,y (two cycles)
if (rst) curr_x <= 0;
if (mrst) curr_x <= 0;
else if (chn_rst || frame_start_r[0]) curr_x <= start_x;
else if (xfer_start_r[0]) curr_x <= last_in_row?0: curr_x + num_cols_r;
if (rst) curr_y <= 0;
if (mrst) curr_y <= 0;
else if (chn_rst || frame_start_r[0]) curr_y <= start_y;
else if (xfer_start_r[0] && last_in_row) curr_y <= next_y[FRAME_HEIGHT_BITS-1:0];
if (rst) last_block <= 0;
if (mrst) last_block <= 0;
else if (chn_rst || !busy_r) last_block <= 0;
else if (xfer_start_r[0]) last_block <= last_row_w && last_in_row_w;
// start_not_partial is not generated when partial (first of 2, caused by a tile crossing memory page) transfer is requested
// here we need to cout all requests - partial or not
if (rst) pending_xfers <= 0;
if (mrst) pending_xfers <= 0;
else if (chn_rst || !busy_r) pending_xfers <= 0;
else if ( xfer_start_r[0] && !xfer_page_done) pending_xfers <= pending_xfers + 1;
else if (!xfer_start_r[0] && xfer_page_done) pending_xfers <= pending_xfers - 1; // page done is not generated on partial (first) pages
// single cycle (sent out)
if (rst) frame_done_r <= 0;
if (mrst) frame_done_r <= 0;
else frame_done_r <= busy_r && last_block && xfer_page_done_d && (pending_xfers==0);
// turns and stays on (used in status)
if (rst) frame_finished_r <= 0;
if (mrst) frame_finished_r <= 0;
else if (chn_rst || frame_start_r[0]) frame_finished_r <= 0;
else if (frame_done_r) frame_finished_r <= 1;
/* //line_unfinished_r cmd_wrmem
if (rst) line_unfinished_r0 <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
else if (chn_rst || frame_start_r[0]) line_unfinished_r0 <= window_y0+start_y;
else if (xfer_start_r[2]) line_unfinished_r0 <= window_y0+next_y[FRAME_HEIGHT_BITS-1:0]; // latency 2 from xfer_start
if (rst) line_unfinished_r1 <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
else if (chn_rst || frame_start_r[0]) line_unfinished_r1 <= window_y0+start_y;
// in read mode advance line number ASAP
else if (xfer_start_r[2] && !cmd_wrmem) line_unfinished_r1 <= window_y0+next_y[FRAME_HEIGHT_BITS-1:0]; // latency 2 from xfer_start
// in write mode advance line number only when it is guaranteed it will be the first to actually access memory
else if (xfer_grant && cmd_wrmem) line_unfinished_r1 <= line_unfinished_r0;
*/
//line_unfinished_r cmd_wrmem
if (rst) line_unfinished_r[0] <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
if (mrst) line_unfinished_r[0] <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
else if (chn_rst || frame_start_r[0]) line_unfinished_r[0] <= window_y0+start_y;
else if (xfer_start_r[2]) line_unfinished_r[0] <= window_y0+next_y[FRAME_HEIGHT_BITS-1:0]; // latency 2 from xfer_start
if (rst) line_unfinished_r[1] <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
// else if (chn_rst || frame_start_r[0]) line_unfinished_r[1] <= window_y0+start_y;
if (mrst) line_unfinished_r[1] <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
else if (chn_rst || frame_start_r[2]) line_unfinished_r[1] <= window_y0+start_y; // _r[0] -> _r[2] to make it simultaneous with frame_number
// in read mode advance line number ASAP
......@@ -574,27 +546,29 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
.ADDR_WIDTH (4),
.DATA_WIDTH (32)
) cmd_deser_32bit_i (
.rst (rst), // input
.clk (mclk), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[15:0]
.rst (1'b0), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[15:0]
.data (cmd_data), // output[31:0]
.we (cmd_we) // output
.we (cmd_we) // output
);
status_generate #(
.STATUS_REG_ADDR (MCNTRL_TILED_STATUS_REG_ADDR),
.PAYLOAD_BITS (2)
) status_generate_i (
.rst (rst), // input
.clk (mclk), // input
.we (set_status_w), // input
.rst (1'b0), // input
.clk (mclk), // input
.srst (mrst), // input
.we (set_status_w), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_data), // input[25:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
.status (status_data), // input[25:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
);
endmodule
memctrl/memctrl16.v
View file @ b721ae66
......@@ -141,7 +141,10 @@ module memctrl16 #(
input rst_in,
input clk_in,
output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
input mrst, // @posedge mclk synchronous reset - should not interrupt mclk generation
output locked, // to generate sync reset
output ref_clk, // global clock for idelay_ctrl calibration
output idelay_ctrl_reset,
// programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
......@@ -526,7 +529,7 @@ module memctrl16 #(
// temporary debug data
,output [11:0] tmp_debug // add some signals generated here?
);
wire rst=rst_in; // TODO: decide where toi generate
//wire rst=rst_in; // TODO: decide where to generate
wire ext_buf_rd;
wire ext_buf_rpage_nxt;
......@@ -627,31 +630,33 @@ wire rst=rst_in; // TODO: decide where toi generate
// mux status info from the memory controller and other modules
status_router2 status_router2_top_i (
.rst (rst), // input
.clk (mclk), // input
.db_in0 (status_ad_phy), // input[7:0]
.rq_in0 (status_rq_phy), // input
.start_in0 (status_start_phy), // output
.db_in1 (status_ad_mcontr), // input[7:0]
.rq_in1 (status_rq_mcontr), // input
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.db_in0 (status_ad_phy), // input[7:0]
.rq_in0 (status_rq_phy), // input
.start_in0 (status_start_phy), // output
.db_in1 (status_ad_mcontr), // input[7:0]
.rq_in1 (status_rq_mcontr), // input
.start_in1 (status_start_mcontr), // output
.db_out (status_ad), // output[7:0]
.rq_out (status_rq), // output
.start_out (status_start) // input
.db_out (status_ad), // output[7:0]
.rq_out (status_rq), // output
.start_out (status_start) // input
);
status_generate #(
.STATUS_REG_ADDR (MCONTR_TOP_STATUS_REG_ADDR),
.PAYLOAD_BITS (18)
) status_generate_i (
.rst (rst), // input
.clk (mclk), // input
.we (set_status_w), // input
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (set_status_w), // input
.wd (mcontr_16bit_data[7:0]), // input[7:0]
.status (status_data), // input[25:0]
.ad (status_ad_mcontr), // output[7:0]
.rq (status_rq_mcontr), // output
.start (status_start_mcontr) // input
.status (status_data), // input[25:0]
.ad (status_ad_mcontr), // output[7:0]
.rq (status_rq_mcontr), // output
.start (status_start_mcontr) // input
);
// generate 16-bit data commands (and set defaults to registers)
......@@ -662,13 +667,14 @@ wire rst=rst_in; // TODO: decide where toi generate
.ADDR_WIDTH (4),
.DATA_WIDTH (16)
) cmd_deser_mcontr_16bit_i (
.rst (rst), // input
.clk (mclk), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (priority_addr), // output[15:0]
.data (priority_data), // output[31:0]
.we (priority_en) // output
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (priority_addr), // output[15:0]
.data (priority_data), // output[31:0]
.we (priority_en) // output
);
// generate on/off dependent on lsb and 0-bit commands
......@@ -679,19 +685,20 @@ wire rst=rst_in; // TODO: decide where toi generate
.ADDR_WIDTH (3),
.DATA_WIDTH (0)
) cmd_deser_0bit_i (
.rst (rst), // input
.clk (mclk), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (mcontr_0bit_addr), // output[15:0]
.data (), // output[31:0]
.we (mcontr_0bit_we) // output
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (mcontr_0bit_addr), // output[15:0]
.data (), // output[31:0]
.we (mcontr_0bit_we) // output
);
always @ (posedge rst or posedge mclk) begin
if (rst) mcontr_en <= 0;
always @ (posedge mclk) begin
if (mrst) mcontr_en <= 0;
else if (mcontr_0bit_we && (mcontr_0bit_addr[2:1]==(MCONTR_TOP_0BIT_MCONTR_EN>>1))) mcontr_en <= mcontr_0bit_addr[0];
if (rst) refresh_en <= 0 ; // 1;
if (mrst) refresh_en <= 0 ; // 1;
else if (mcontr_0bit_we && (mcontr_0bit_addr[2:1]==(MCONTR_TOP_0BIT_REFRESH_EN>>1))) refresh_en <= mcontr_0bit_addr[0];
end
......@@ -704,8 +711,9 @@ wire rst=rst_in; // TODO: decide where toi generate
.ADDR_WIDTH (3),
.DATA_WIDTH (16)
) cmd_deser_16bit_i (
.rst (rst), // input
.rst (1'b0), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (mcontr_16bit_addr), // output[15:0]
......@@ -723,27 +731,27 @@ wire rst=rst_in; // TODO: decide where toi generate
assign set_refresh_address_w= mcontr_16bit_we && (mcontr_16bit_addr[2:0]==MCONTR_TOP_16BIT_REFRESH_ADDRESS);
assign set_status_w= mcontr_16bit_we && (mcontr_16bit_addr[2:0]==MCONTR_TOP_16BIT_STATUS_CNTRL);
always @ (posedge rst or posedge mclk) begin
if (rst) set_refresh_period <= 0;
else set_refresh_period <= set_refresh_period_w;
always @ (posedge mclk) begin
if (mrst) set_refresh_period <= 0;
else set_refresh_period <= set_refresh_period_w;
if (rst) mcontr_chn_en <= DFLT_CHN_EN;
if (mrst) mcontr_chn_en <= DFLT_CHN_EN;
else if (set_chn_en_w) mcontr_chn_en <= mcontr_16bit_data[15:0];
if (rst) refresh_addr <= DFLT_REFRESH_ADDR;
if (mrst) refresh_addr <= DFLT_REFRESH_ADDR;
else if (set_refresh_address_w) refresh_addr <= mcontr_16bit_data[9:0];
if (rst) refresh_period <= DFLT_REFRESH_PERIOD;
if (mrst) refresh_period <= DFLT_REFRESH_PERIOD;
else if (set_refresh_period_w) refresh_period <= mcontr_16bit_data[7:0];
if (rst) chn_want_some <= 0;
else chn_want_some <= |want_rq;
if (mrst) chn_want_some <= 0;
else chn_want_some <= |want_rq;
if (rst) chn_need_some <= 0;
else chn_need_some <= |need_rq;
if (mrst) chn_need_some <= 0;
else chn_need_some <= |need_rq;
if (rst) chn_want_r <= 0;
else chn_want_r <= want_rq ; // unmasked channel requests
if (mrst) chn_want_r <= 0;
else chn_want_r <= want_rq ; // unmasked channel requests
end
......@@ -752,7 +760,7 @@ wire rst=rst_in; // TODO: decide where toi generate
scheduler16 #(
.width (16)
) scheduler16_i (
.rst (rst), // input
.mrst (mrst), // input
.clk (mclk), // input
.chn_en (mcontr_chn_en), // input[15:0]
.want_rq (want_rq), // input[15:0]
......@@ -776,42 +784,42 @@ assign pre_run_chn_w= pre_run_seq_w && !sel_refresh_w;
assign en_schedul= mcontr_enabled && !cmd_seq_fill && !cmd_seq_full;
// sequential logic for commands transfer to the sequencer
always @ (posedge rst or posedge mclk) begin
if (rst) grant_r <= 0;
else grant_r <= grant;
always @ (posedge mclk) begin
if (mrst) grant_r <= 0;
else grant_r <= grant;
if (rst) cmd_seq_set <= 0;
if (mrst) cmd_seq_set <= 0;
else if (grant_r) cmd_seq_set <= 0;
else if (seq_wr) cmd_seq_set <= 1;
if (rst) cmd_wr_chn <= 0;
if (mrst) cmd_wr_chn <= 0;
else if (grant) cmd_wr_chn <= grant_chn;
//TODO: Modify,cmd_seq_fill was initially used to see if any sequaence data was written (or PS is used), now it is cmd_seq_set
if (rst) cmd_seq_fill <= 0;
if (mrst) cmd_seq_fill <= 0;
else if (!mcontr_enabled || seq_set || cmd_seq_full ) cmd_seq_fill <= 0;
else if (grant) cmd_seq_fill <= 1;
if (rst) cmd_seq_full <= 0;
if (mrst) cmd_seq_full <= 0;
else if (!mcontr_enabled || pre_run_chn_w ) cmd_seq_full <= 0;
else if (seq_set) cmd_seq_full <= 1; // even with no data
else if (seq_set) cmd_seq_full <= 1; // even with no data
if (rst) cmd_seq_need <= 0;
if (mrst) cmd_seq_need <= 0;
else if (grant) cmd_seq_need <= need;
if (rst) cmd_addr_cur <= 0;
if (mrst) cmd_addr_cur <= 0;
else if (seq_wr) cmd_addr_cur <= cmd_addr_cur+1;
if (rst) cmd_addr_start <= 0;
if (mrst) cmd_addr_start <= 0;
else if (grant_r) cmd_addr_start <= {1'b1,cmd_addr_cur}; // address in PL bank
else if (!cmd_seq_set && seq_set) cmd_addr_start <= {1'b0,seq_data[9:0]}; // address in PS bank
if (rst) cmd_seq_run <= 0;
else cmd_seq_run <= pre_run_seq_w;
if (mrst) cmd_seq_run <= 0;
else cmd_seq_run <= pre_run_seq_w;
// add refresh address here?
end
......@@ -826,18 +834,18 @@ end
ddr_refresh ddr_refresh_i (
.rst (rst), // input
.clk (mclk), // input
.en (refresh_en),
.refresh_period (refresh_period), // input[7:0]
.mrst (mrst), // input
.clk (mclk), // input
.en (refresh_en), // input
.refresh_period (refresh_period), // input[7:0]
.set (set_refresh_period), // input
.want (refresh_want), // output
.need (refresh_need), // output
.grant (refresh_grant) // input
.want (refresh_want), // output
.need (refresh_need), // output
.grant (refresh_grant) // input
);
always @(posedge rst or posedge mclk) begin
if (rst) refresh_grant <= 0;
else refresh_grant <= pre_run_seq_w && sel_refresh_w;
always @(posedge mclk) begin
if (mrst) refresh_grant <= 0;
else refresh_grant <= pre_run_seq_w && sel_refresh_w;
end
......@@ -914,7 +922,10 @@ end
.clk_in (clk_in), // axi_aclk), // input
.rst_in (rst_in), // axi_rst), // input TODO: move buffer outside?
.mclk (mclk), // output
.mrst (mrst), // input
.locked (locked), // output
.ref_clk (ref_clk), // output
.idelay_ctrl_reset (idelay_ctrl_reset),
.cmd0_clk (cmd0_clk), // input
.cmd0_we (cmd0_we), // input
......@@ -958,281 +969,281 @@ end
// Registering existing channel buffers I/Os
`ifdef def_enable_mem_chn0
mcont_common_chnbuf_reg #( .CHN_NUMBER(0)) mcont_common_chnbuf_reg0_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
mcont_common_chnbuf_reg #( .CHN_NUMBER(0)) mcont_common_chnbuf_reg0_i(.rst(mrst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done0),.page_nxt(page_nxt_chn0),.buf_run(buf_run0));
`ifdef def_read_mem_chn0
mcont_to_chnbuf_reg #(.CHN_NUMBER( 0)) mcont_to_chnbuf_reg0_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
mcont_to_chnbuf_reg #(.CHN_NUMBER( 0)) mcont_to_chnbuf_reg0_i(.rst(mrst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn0),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn0),.buf_run(buf_wrun0),.buf_wdata_chn(buf_wdata_chn0));
`endif
`ifdef def_write_mem_chn0
wire [63:0] ext_buf_rdata0;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 0),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg0_i (.rst(rst),.clk(mclk),
mcont_from_chnbuf_reg #(.CHN_NUMBER( 0),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg0_i (.rst(mrst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata0),.buf_rd_chn(buf_rd_chn0),.rpage_nxt(buf_rpage_nxt_chn0),.buf_rdata_chn(buf_rdata_chn0));
`endif
`endif
`ifdef def_enable_mem_chn1
mcont_common_chnbuf_reg #( .CHN_NUMBER(1)) mcont_common_chnbuf_reg1_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
mcont_common_chnbuf_reg #( .CHN_NUMBER(1)) mcont_common_chnbuf_reg1_i(.rst(mrst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done1),.page_nxt(page_nxt_chn1),.buf_run(buf_run1));
`ifdef def_read_mem_chn1
mcont_to_chnbuf_reg #(.CHN_NUMBER( 1)) mcont_to_chnbuf_reg1_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
mcont_to_chnbuf_reg #(.CHN_NUMBER( 1)) mcont_to_chnbuf_reg1_i(.rst(mrst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn1),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn1),.buf_run(buf_wrun1),.buf_wdata_chn(buf_wdata_chn1));
`endif
`ifdef def_write_mem_chn1
wire [63:0] ext_buf_rdata1;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 1),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg1_i (.rst(rst),.clk(mclk),
mcont_from_chnbuf_reg #(.CHN_NUMBER( 1),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg1_i (.rst(mrst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata1),.buf_rd_chn(buf_rd_chn1),.rpage_nxt(buf_rpage_nxt_chn1),.buf_rdata_chn(buf_rdata_chn1));
`endif
`endif
`ifdef def_enable_mem_chn2
mcont_common_chnbuf_reg #( .CHN_NUMBER(2)) mcont_common_chnbuf_reg2_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
mcont_common_chnbuf_reg #( .CHN_NUMBER(2)) mcont_common_chnbuf_reg2_i(.rst(mrst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done2),.page_nxt(page_nxt_chn2),.buf_run(buf_run2));
`ifdef def_read_mem_chn2
mcont_to_chnbuf_reg #(.CHN_NUMBER( 2)) mcont_to_chnbuf_reg2_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
mcont_to_chnbuf_reg #(.CHN_NUMBER( 2)) mcont_to_chnbuf_reg2_i(.rst(mrst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn2),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn2),.buf_run(buf_wrun2),.buf_wdata_chn(buf_wdata_chn2));
`endif
`ifdef def_write_mem_chn2
wire [63:0] ext_buf_rdata2;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 2),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg2_i (.rst(rst),.clk(mclk),
mcont_from_chnbuf_reg #(.CHN_NUMBER( 2),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg2_i (.rst(mrst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata2),.buf_rd_chn(buf_rd_chn2),.rpage_nxt(buf_rpage_nxt_chn2),.buf_rdata_chn(buf_rdata_chn2));
`endif
`endif
`ifdef def_enable_mem_chn3
mcont_common_chnbuf_reg #( .CHN_NUMBER(3)) mcont_common_chnbuf_reg3_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
mcont_common_chnbuf_reg #( .CHN_NUMBER(3)) mcont_common_chnbuf_reg3_i(.rst(mrst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done3),.page_nxt(page_nxt_chn3),.buf_run(buf_run3));
`ifdef def_read_mem_chn3
mcont_to_chnbuf_reg #(.CHN_NUMBER( 3)) mcont_to_chnbuf_reg3_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
mcont_to_chnbuf_reg #(.CHN_NUMBER( 3)) mcont_to_chnbuf_reg3_i(.rst(mrst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn3),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn3),.buf_run(buf_wrun3),.buf_wdata_chn(buf_wdata_chn3));
`endif
`ifdef def_write_mem_chn3
wire [63:0] ext_buf_rdata3;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 3),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg3_i (.rst(rst),.clk(mclk),
mcont_from_chnbuf_reg #(.CHN_NUMBER( 3),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg3_i (.rst(mrst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata3),.buf_rd_chn(buf_rd_chn3),.rpage_nxt(buf_rpage_nxt_chn3),.buf_rdata_chn(buf_rdata_chn3));
`endif
`endif
`ifdef def_enable_mem_chn4
mcont_common_chnbuf_reg #( .CHN_NUMBER(4)) mcont_common_chnbuf_reg4_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
mcont_common_chnbuf_reg #( .CHN_NUMBER(4)) mcont_common_chnbuf_reg4_i(.rst(mrst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done4),.page_nxt(page_nxt_chn4),.buf_run(buf_run4));
`ifdef def_read_mem_chn4
mcont_to_chnbuf_reg #(.CHN_NUMBER( 4)) mcont_to_chnbuf_reg4_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
mcont_to_chnbuf_reg #(.CHN_NUMBER( 4)) mcont_to_chnbuf_reg4_i(.rst(mrst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn4),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn4),.buf_run(buf_wrun4),.buf_wdata_chn(buf_wdata_chn4));
`endif
`ifdef def_write_mem_chn4
wire [63:0] ext_buf_rdata4;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 4),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg4_i (.rst(rst),.clk(mclk),
mcont_from_chnbuf_reg #(.CHN_NUMBER( 4),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg4_i (.rst(mrst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata4),.buf_rd_chn(buf_rd_chn4),.rpage_nxt(buf_rpage_nxt_chn4),.buf_rdata_chn(buf_rdata_chn4));
`endif
`endif
`ifdef def_enable_mem_chn5
mcont_common_chnbuf_reg #( .CHN_NUMBER(5)) mcont_common_chnbuf_reg5_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
mcont_common_chnbuf_reg #( .CHN_NUMBER(5)) mcont_common_chnbuf_reg5_i(.rst(mrst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done5),.page_nxt(page_nxt_chn5),.buf_run(buf_run5));
`ifdef def_read_mem_chn5
mcont_to_chnbuf_reg #(.CHN_NUMBER( 5)) mcont_to_chnbuf_reg5_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
mcont_to_chnbuf_reg #(.CHN_NUMBER( 5)) mcont_to_chnbuf_reg5_i(.rst(mrst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn5),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn5),.buf_run(buf_wrun5),.buf_wdata_chn(buf_wdata_chn5));
`endif
`ifdef def_write_mem_chn5
wire [63:0] ext_buf_rdata5;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 5),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg5_i (.rst(rst),.clk(mclk),
mcont_from_chnbuf_reg #(.CHN_NUMBER( 5),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg5_i (.rst(mrst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata5),.buf_rd_chn(buf_rd_chn5),.rpage_nxt(buf_rpage_nxt_chn5),.buf_rdata_chn(buf_rdata_chn5));
`endif
`endif
`ifdef def_enable_mem_chn6
mcont_common_chnbuf_reg #( .CHN_NUMBER(6)) mcont_common_chnbuf_reg6_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
mcont_common_chnbuf_reg #( .CHN_NUMBER(6)) mcont_common_chnbuf_reg6_i(.rst(mrst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done6),.page_nxt(page_nxt_chn6),.buf_run(buf_run6));
`ifdef def_read_mem_chn6
mcont_to_chnbuf_reg #(.CHN_NUMBER( 6)) mcont_to_chnbuf_reg6_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
mcont_to_chnbuf_reg #(.CHN_NUMBER( 6)) mcont_to_chnbuf_reg6_i(.rst(mrst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn6),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn6),.buf_run(buf_wrun6),.buf_wdata_chn(buf_wdata_chn6));
`endif
`ifdef def_write_mem_chn6
wire [63:0] ext_buf_rdata6;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 6),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg6_i (.rst(rst),.clk(mclk),
mcont_from_chnbuf_reg #(.CHN_NUMBER( 6),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg6_i (.rst(mrst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata6),.buf_rd_chn(buf_rd_chn6),.rpage_nxt(buf_rpage_nxt_chn6),.buf_rdata_chn(buf_rdata_chn6));
`endif
`endif
`ifdef def_enable_mem_chn7
mcont_common_chnbuf_reg #( .CHN_NUMBER(7)) mcont_common_chnbuf_reg7_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
mcont_common_chnbuf_reg #( .CHN_NUMBER(7)) mcont_common_chnbuf_reg7_i(.rst(mrst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done7),.page_nxt(page_nxt_chn7),.buf_run(buf_run7));
`ifdef def_read_mem_chn7
mcont_to_chnbuf_reg #(.CHN_NUMBER( 7)) mcont_to_chnbuf_reg7_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
mcont_to_chnbuf_reg #(.CHN_NUMBER( 7)) mcont_to_chnbuf_reg7_i(.rst(mrst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn7),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn7),.buf_run(buf_wrun7),.buf_wdata_chn(buf_wdata_chn7));
`endif
`ifdef def_write_mem_chn7
wire [63:0] ext_buf_rdata7;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 7),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg7_i (.rst(rst),.clk(mclk),
mcont_from_chnbuf_reg #(.CHN_NUMBER( 7),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg7_i (.rst(mrst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata7),.buf_rd_chn(buf_rd_chn7),.rpage_nxt(buf_rpage_nxt_chn7),.buf_rdata_chn(buf_rdata_chn7));
`endif
`endif
`ifdef def_enable_mem_chn8
mcont_common_chnbuf_reg #( .CHN_NUMBER(8)) mcont_common_chnbuf_reg8_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
mcont_common_chnbuf_reg #( .CHN_NUMBER(8)) mcont_common_chnbuf_reg8_i(.rst(mrst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done8),.page_nxt(page_nxt_chn8),.buf_run(buf_run8));
`ifdef def_read_mem_chn8
mcont_to_chnbuf_reg #(.CHN_NUMBER( 8)) mcont_to_chnbuf_reg8_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
mcont_to_chnbuf_reg #(.CHN_NUMBER( 8)) mcont_to_chnbuf_reg8_i(.rst(mrst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn8),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn8),.buf_run(buf_wrun8),.buf_wdata_chn(buf_wdata_chn8));
`endif
`ifdef def_write_mem_chn8
wire [63:0] ext_buf_rdata8;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 8),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg8_i (.rst(rst),.clk(mclk),
mcont_from_chnbuf_reg #(.CHN_NUMBER( 8),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg8_i (.rst(mrst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata8),.buf_rd_chn(buf_rd_chn8),.rpage_nxt(buf_rpage_nxt_chn8),.buf_rdata_chn(buf_rdata_chn8));
`endif
`endif
`ifdef def_enable_mem_chn9
mcont_common_chnbuf_reg #( .CHN_NUMBER(9)) mcont_common_chnbuf_reg9_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
mcont_common_chnbuf_reg #( .CHN_NUMBER(9)) mcont_common_chnbuf_reg9_i(.rst(mrst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done9),.page_nxt(page_nxt_chn9),.buf_run(buf_run9));
`ifdef def_read_mem_chn9
mcont_to_chnbuf_reg #(.CHN_NUMBER( 9)) mcont_to_chnbuf_reg9_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
mcont_to_chnbuf_reg #(.CHN_NUMBER( 9)) mcont_to_chnbuf_reg9_i(.rst(mrst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn9),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn9),.buf_run(buf_wrun9),.buf_wdata_chn(buf_wdata_chn9));
`endif
`ifdef def_write_mem_chn9
wire [63:0] ext_buf_rdata9;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 9),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg9_i (.rst(rst),.clk(mclk),
mcont_from_chnbuf_reg #(.CHN_NUMBER( 9),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg9_i (.rst(mrst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata9),.buf_rd_chn(buf_rd_chn9),.rpage_nxt(buf_rpage_nxt_chn9),.buf_rdata_chn(buf_rdata_chn9));
`endif
`endif
`ifdef def_enable_mem_chn10
mcont_common_chnbuf_reg #( .CHN_NUMBER(10)) mcont_common_chnbuf_reg10_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
mcont_common_chnbuf_reg #( .CHN_NUMBER(10)) mcont_common_chnbuf_reg10_i(.rst(mrst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done10),.page_nxt(page_nxt_chn10),.buf_run(buf_run10));
`ifdef def_read_mem_chn10
mcont_to_chnbuf_reg #(.CHN_NUMBER( 10)) mcont_to_chnbuf_reg10_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
mcont_to_chnbuf_reg #(.CHN_NUMBER( 10)) mcont_to_chnbuf_reg10_i(.rst(mrst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn10),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn10),.buf_run(buf_wrun10),.buf_wdata_chn(buf_wdata_chn10));
`endif
`ifdef def_write_mem_chn10
wire [63:0] ext_buf_rdata10;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 10),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg10_i (.rst(rst),.clk(mclk),
mcont_from_chnbuf_reg #(.CHN_NUMBER( 10),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg10_i (.rst(mrst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata10),.buf_rd_chn(buf_rd_chn10),.rpage_nxt(buf_rpage_nxt_chn10),.buf_rdata_chn(buf_rdata_chn10));
`endif
`endif
`ifdef def_enable_mem_chn11
mcont_common_chnbuf_reg #( .CHN_NUMBER(11)) mcont_common_chnbuf_reg11_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
mcont_common_chnbuf_reg #( .CHN_NUMBER(11)) mcont_common_chnbuf_reg11_i(.rst(mrst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done11),.page_nxt(page_nxt_chn11),.buf_run(buf_run11));
`ifdef def_read_mem_chn11
mcont_to_chnbuf_reg #(.CHN_NUMBER( 11)) mcont_to_chnbuf_reg11_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
mcont_to_chnbuf_reg #(.CHN_NUMBER( 11)) mcont_to_chnbuf_reg11_i(.rst(mrst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn11),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn11),.buf_run(buf_wrun11),.buf_wdata_chn(buf_wdata_chn11));
`endif
`ifdef def_write_mem_chn11
wire [63:0] ext_buf_rdata11;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 11),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg11_i (.rst(rst),.clk(mclk),
mcont_from_chnbuf_reg #(.CHN_NUMBER( 11),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg11_i (.rst(mrst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata11),.buf_rd_chn(buf_rd_chn11),.rpage_nxt(buf_rpage_nxt_chn11),.buf_rdata_chn(buf_rdata_chn11));
`endif
`endif
`ifdef def_enable_mem_chn12
mcont_common_chnbuf_reg #( .CHN_NUMBER(12)) mcont_common_chnbuf_reg12_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
mcont_common_chnbuf_reg #( .CHN_NUMBER(12)) mcont_common_chnbuf_reg12_i(.rst(mrst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done12),.page_nxt(page_nxt_chn12),.buf_run(buf_run12));
`ifdef def_read_mem_chn12
mcont_to_chnbuf_reg #(.CHN_NUMBER( 12)) mcont_to_chnbuf_reg12_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
mcont_to_chnbuf_reg #(.CHN_NUMBER( 12)) mcont_to_chnbuf_reg12_i(.rst(mrst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn12),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn12),.buf_run(buf_wrun12),.buf_wdata_chn(buf_wdata_chn12));
`endif
`ifdef def_write_mem_chn12
wire [63:0] ext_buf_rdata12;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 12),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg12_i (.rst(rst),.clk(mclk),
mcont_from_chnbuf_reg #(.CHN_NUMBER( 12),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg12_i (.rst(mrst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata12),.buf_rd_chn(buf_rd_chn12),.rpage_nxt(buf_rpage_nxt_chn12),.buf_rdata_chn(buf_rdata_chn12));
`endif
`endif
`ifdef def_enable_mem_chn13
mcont_common_chnbuf_reg #( .CHN_NUMBER(13)) mcont_common_chnbuf_reg13_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
mcont_common_chnbuf_reg #( .CHN_NUMBER(13)) mcont_common_chnbuf_reg13_i(.rst(mrst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done13),.page_nxt(page_nxt_chn13),.buf_run(buf_run13));
`ifdef def_read_mem_chn13
mcont_to_chnbuf_reg #(.CHN_NUMBER( 13)) mcont_to_chnbuf_reg13_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
mcont_to_chnbuf_reg #(.CHN_NUMBER( 13)) mcont_to_chnbuf_reg13_i(.rst(mrst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn13),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn13),.buf_run(buf_wrun13),.buf_wdata_chn(buf_wdata_chn13));
`endif
`ifdef def_write_mem_chn13
wire [63:0] ext_buf_rdata13;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 13),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg13_i (.rst(rst),.clk(mclk),
mcont_from_chnbuf_reg #(.CHN_NUMBER( 13),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg13_i (.rst(mrst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata13),.buf_rd_chn(buf_rd_chn13),.rpage_nxt(buf_rpage_nxt_chn13),.buf_rdata_chn(buf_rdata_chn13));
`endif
`endif
`ifdef def_enable_mem_chn14
mcont_common_chnbuf_reg #( .CHN_NUMBER(14)) mcont_common_chnbuf_reg14_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
mcont_common_chnbuf_reg #( .CHN_NUMBER(14)) mcont_common_chnbuf_reg14_i(.rst(mrst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done14),.page_nxt(page_nxt_chn14),.buf_run(buf_run14));
`ifdef def_read_mem_chn14
mcont_to_chnbuf_reg #(.CHN_NUMBER( 14)) mcont_to_chnbuf_reg14_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
mcont_to_chnbuf_reg #(.CHN_NUMBER( 14)) mcont_to_chnbuf_reg14_i(.rst(mrst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn14),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn14),.buf_run(buf_wrun14),.buf_wdata_chn(buf_wdata_chn14));
`endif
`ifdef def_write_mem_chn14
wire [63:0] ext_buf_rdata14;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 14),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg14_i (.rst(rst),.clk(mclk),
mcont_from_chnbuf_reg #(.CHN_NUMBER( 14),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg14_i (.rst(mrst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata14),.buf_rd_chn(buf_rd_chn14),.rpage_nxt(buf_rpage_nxt_chn14),.buf_rdata_chn(buf_rdata_chn14));
`endif
`endif
`ifdef def_enable_mem_chn15
mcont_common_chnbuf_reg #( .CHN_NUMBER(15)) mcont_common_chnbuf_reg15_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
mcont_common_chnbuf_reg #( .CHN_NUMBER(15)) mcont_common_chnbuf_reg15_i(.rst(mrst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done15),.page_nxt(page_nxt_chn15),.buf_run(buf_run15));
`ifdef def_read_mem_chn15
mcont_to_chnbuf_reg #(.CHN_NUMBER( 15)) mcont_to_chnbuf_reg15_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
mcont_to_chnbuf_reg #(.CHN_NUMBER( 15)) mcont_to_chnbuf_reg15_i(.rst(mrst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn15),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn15),.buf_run(buf_wrun15),.buf_wdata_chn(buf_wdata_chn15));
......@@ -1253,7 +1264,7 @@ localparam [3:0] EXT_READ_LATENCY=CHNBUF_READ_LATENCY+2; // +1;
.WIDTH(5)
) dly_16_i (
.clk(mclk), // input
.rst(rst), // input
.rst(mrst), // input
.dly(EXT_READ_LATENCY), // input[3:0]
.din({~ext_buf_rrefresh & ext_buf_rd,ext_buf_rchn}), // input[0:0]
.dout({ext_buf_rd_late,ext_buf_rchn_late}) // output[0:0]
......
memctrl/phy/mcontr_sequencer.v
View file @ b721ae66
......@@ -115,7 +115,10 @@ module mcontr_sequencer #(
input clk_in,
input rst_in,
output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
input mrst, // @posedge mclk, sync reset (should not interrupt mclk!)
output locked, // to generate sync reset
output ref_clk, // global clock for idelay_ctrl calibration
output idelay_ctrl_reset,
// command port 0 (filled by software - 32w->32r) - used for mode set, refresh, write levelling, ...
input cmd0_clk,
input cmd0_we,
......@@ -205,7 +208,7 @@ module mcontr_sequencer #(
// wire [PHASE_WIDTH-1:0] ps_out;
wire [7:0] ps_out;
wire ps_rdy;
wire locked;
// wire locked;
wire [14:0] status_data;
// temporary, debug
......@@ -234,7 +237,7 @@ module mcontr_sequencer #(
wire buf_rd; // read next 64 bits from the buffer, need one extra pre-read
wire buf_rst; // reset buffer address to
wire buf_rst_d; //buf_rst delayed to match buf_wr
wire rst=rst_in;
// wire rst=rst_in;
// wire [ 9:0] next_cmd_addr;
reg [ 9:0] cmd_addr; // command word address
......@@ -314,13 +317,14 @@ module mcontr_sequencer #(
.ADDR_WIDTH (7),
.DATA_WIDTH (8)
) cmd_deser_dly_i (
.rst (rst), // input
.clk (mclk), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (dly_addr), // output[15:0]
.data (dly_data), // output[31:0]
.we( ld_delay) // output
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (dly_addr), // output[15:0]
.data (dly_data), // output[31:0]
.we( ld_delay) // output
);
// generate on/off dependent on lsb and 0-bit commands
cmd_deser #(
......@@ -330,30 +334,31 @@ module mcontr_sequencer #(
.ADDR_WIDTH (4),
.DATA_WIDTH (0)
) cmd_deser_0bit_i (
.rst (rst), // input
.clk (mclk), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (phy_0bit_addr), // output[15:0]
.data (), // output[31:0]
.we (phy_0bit_we) // output
.data (), // output[31:0]
.we (phy_0bit_we) // output
);
assign set= phy_0bit_we && (phy_0bit_addr==MCONTR_PHY_0BIT_DLY_SET);
always @ (posedge mclk or posedge rst) begin
if (rst) cmda_en <= 0;
always @ (posedge mclk) begin
if (mrst) cmda_en <= 0;
else if (phy_0bit_we && (phy_0bit_addr[3:1]==(MCONTR_PHY_0BIT_CMDA_EN>>1))) cmda_en <= phy_0bit_addr[0];
if (rst) ddr_rst <= 1;
if (mrst) ddr_rst <= 1;
else if (phy_0bit_we && (phy_0bit_addr[3:1]==(MCONTR_PHY_0BIT_SDRST_ACT>>1))) ddr_rst <= phy_0bit_addr[0];
if (rst) dci_rst <= 0;
if (mrst) dci_rst <= 0;
else if (phy_0bit_we && (phy_0bit_addr[3:1]==(MCONTR_PHY_0BIT_DCI_RST>>1))) dci_rst <= phy_0bit_addr[0];
if (rst) dly_rst <= 0;
if (mrst) dly_rst <= 0;
else if (phy_0bit_we && (phy_0bit_addr[3:1]==(MCONTR_PHY_0BIT_DLY_RST>>1))) dly_rst <= phy_0bit_addr[0];
if (rst) ddr_cke <= 0;
if (mrst) ddr_cke <= 0;
else if (phy_0bit_we && (phy_0bit_addr[3:1]==(MCONTR_PHY_0BIT_CKE_EN>>1))) ddr_cke <= phy_0bit_addr[0];
end
......@@ -365,8 +370,9 @@ module mcontr_sequencer #(
.ADDR_WIDTH (3),
.DATA_WIDTH (16)
) cmd_deser_16bit_i (
.rst (rst), // input
.clk (mclk), // input
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (phy_16bit_addr), // output[15:0]
......@@ -388,8 +394,8 @@ module mcontr_sequencer #(
assign control_status_we= phy_16bit_we && (phy_16bit_addr[2:0]==MCONTR_PHY_STATUS_CNTRL);
assign contral_status_data= phy_16bit_data[7:0];
always @ (posedge mclk or posedge rst) begin
if (rst) begin
always @ (posedge mclk) begin
if (mrst) begin
dqm_pattern <=DFLT_DQM_PATTERN;
dqs_pattern <=DFLT_DQS_PATTERN;
end else if (set_patterns) begin
......@@ -397,7 +403,7 @@ module mcontr_sequencer #(
dqs_pattern <= phy_16bit_data[7:0];
end
if (rst) begin
if (mrst) begin
dqs_tri_off_pattern[3:0] <= DFLT_DQS_TRI_OFF_PATTERN;
dqs_tri_on_pattern[3:0] <= DFLT_DQS_TRI_ON_PATTERN;
dq_tri_off_pattern[3:0] <= DFLT_DQ_TRI_OFF_PATTERN;
......@@ -408,10 +414,10 @@ module mcontr_sequencer #(
dq_tri_off_pattern[3:0] <= phy_16bit_data[ 7: 4];
dq_tri_on_pattern[3:0] <= phy_16bit_data[ 3: 0];
end
if (rst) wbuf_delay <= DFLT_WBUF_DELAY;
if (mrst) wbuf_delay <= DFLT_WBUF_DELAY;
else if (set_wbuf_delay) wbuf_delay <= phy_16bit_data[ 3: 0];
if (rst) inv_clk_div <= DFLT_INV_CLK_DIV;
if (mrst) inv_clk_div <= DFLT_INV_CLK_DIV;
else if (set_extra) inv_clk_div <= phy_16bit_data[0];
end
......@@ -423,62 +429,61 @@ module mcontr_sequencer #(
.STATUS_REG_ADDR (MCONTR_PHY_STATUS_REG_ADDR),
.PAYLOAD_BITS (15)
) status_generate_i (
.rst (rst), // input
.clk (mclk), // input
.we (control_status_we), // input
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (control_status_we), // input
.wd (contral_status_data), // input[7:0]
.status (status_data), // input[25:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
.status (status_data), // input[25:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
);
always @ (posedge mclk or posedge rst) begin
if (rst) cmd_busy <= 0;
// else if (sequence_done) cmd_busy <= 0;
always @ (posedge mclk) begin
if (mrst) cmd_busy <= 0;
else if (ddr_rst) cmd_busy <= 0; // *************** reset sequencer with DDR reset
else if (sequence_done && cmd_busy[2]) cmd_busy <= 0;
else cmd_busy <= {cmd_busy[1:0],run_seq | cmd_busy[0]};
// Pause counter
if (rst) pause_cntr <= 0;
if (mrst) pause_cntr <= 0;
else if (!cmd_busy[1]) pause_cntr <= 0; // not needed?
else if (cmd_fetch && phy_cmd_nop) pause_cntr <= pause_len;
else if (pause_cntr!=0) pause_cntr <= pause_cntr-1; //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 10-bit target.
// Fetch - command data valid
if (rst) cmd_fetch <= 0;
else cmd_fetch <= cmd_busy[0] && !pause;
if (mrst) cmd_fetch <= 0;
else cmd_fetch <= cmd_busy[0] && !pause;
if (rst) add_pause <= 0;
else add_pause <= cmd_fetch && phy_cmd_add_pause;
if (mrst) add_pause <= 0;
else add_pause <= cmd_fetch && phy_cmd_add_pause;
// Command read address
if (rst) cmd_addr <= 0;
if (mrst) cmd_addr <= 0;
else if (run_seq) cmd_addr <= run_addr[9:0];
else if (cmd_busy[0] && !pause) cmd_addr <= cmd_addr + 1; //SuppressThisWarning ISExst Result of 11-bit expression is truncated to fit in 10-bit target.
// command bank select (0 - "manual" (software programmed sequences), 1 - "auto" (normal block r/w)
if (rst) cmd_sel <= 0;
if (mrst) cmd_sel <= 0;
else if (run_seq) cmd_sel <= run_addr[10];
// if (rst) buf_raddr <= 7'h0;
// else if (run_seq_d) buf_raddr <= 7'h0;
// else if (buf_wr || buf_rd) buf_raddr <= buf_raddr +1; // Separate read/write address? read address re-registered @ negedge //SuppressThisWarning ISExst Result of 10-bit expression is truncated to fit in 9-bit target.
if (rst) run_chn_d <= 0;
if (mrst) run_chn_d <= 0;
else if (run_seq) run_chn_d <= run_chn;
if (rst) run_refresh_d <= 0;
if (mrst) run_refresh_d <= 0;
else if (run_seq) run_refresh_d <= run_refresh;
if (rst) run_seq_d <= 0;
else run_seq_d <= run_seq;
if (mrst) run_seq_d <= 0;
else run_seq_d <= run_seq;
if (rst) buf_raddr_reset <= 0;
else buf_raddr_reset<= buf_rst & ~mem_read_mode;
if (mrst) buf_raddr_reset <= 0;
else buf_raddr_reset<= buf_rst & ~mem_read_mode;
if (rst) buf_addr_reset <= 0;
else buf_addr_reset<= buf_rst;
if (mrst) buf_addr_reset <= 0;
else buf_addr_reset<= buf_rst;
end
always @ (posedge mclk) begin
......@@ -505,32 +510,32 @@ module mcontr_sequencer #(
ram_1kx32_1kx32 #(
.REGISTERS(1) // (0) // register output
) cmd0_buf_i (
.rclk (mclk), // input
.raddr (cmd_addr), // input[9:0]
.ren (ren0), // input TODO: verify cmd_busy[0] is correct (was cmd_busy )
.regen (ren0), // input
.rclk (mclk), // input
.raddr (cmd_addr), // input[9:0]
.ren (ren0), // input TODO: verify cmd_busy[0] is correct (was cmd_busy ). TODO: make cleaner ren/regen
.regen (ren0), // input
.data_out (phy_cmd0_word), // output[31:0]
.wclk (cmd0_clk), // input
.waddr (cmd0_addr), // input[9:0]
.we (cmd0_we), // input
.web (4'hf), // input[3:0]
.data_in (cmd0_data) // input[31:0]
.wclk (cmd0_clk), // input
.waddr (cmd0_addr), // input[9:0]
.we (cmd0_we), // input
.web (4'hf), // input[3:0]
.data_in (cmd0_data) // input[31:0]
);
// Command sequence memory 0 ("manual"):
ram_1kx32_1kx32 #(
.REGISTERS(1) // (0) // register output
.REGISTERS (1) // (0) // register output
) cmd1_buf_i (
.rclk (mclk), // input
.raddr (cmd_addr), // input[9:0]
.ren ( ren1), // input
.regen ( ren1), // input
.rclk (mclk), // input
.raddr (cmd_addr), // input[9:0]
.ren ( ren1), // input ??? TODO: make cleaner ren/regen
.regen ( ren1), // input ???
.data_out (phy_cmd1_word), // output[31:0]
.wclk (cmd1_clk), // input
.waddr (cmd1_addr), // input[9:0]
.we (cmd1_we), // input
.web (4'hf), // input[3:0]
.data_in (cmd1_data) // input[31:0]
.wclk (cmd1_clk), // input
.waddr (cmd1_addr), // input[9:0]
.we (cmd1_we), // input
.web (4'hf), // input[3:0]
.data_in (cmd1_data) // input[31:0]
);
phy_cmd #(
......@@ -549,7 +554,7 @@ module mcontr_sequencer #(
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE),
.SDCLK_PHASE (SDCLK_PHASE),/// debugging
.SDCLK_PHASE (SDCLK_PHASE), /// debugging
.CLK_PHASE (CLK_PHASE),
.CLK_DIV_PHASE (CLK_DIV_PHASE),
......@@ -560,67 +565,68 @@ module mcontr_sequencer #(
.SS_MOD_PERIOD (SS_MOD_PERIOD),
.CMD_PAUSE_BITS (CMD_PAUSE_BITS), // numer of (address) bits to encode pause
.CMD_DONE_BIT (CMD_DONE_BIT) // bit number (address) to signal sequence done
) phy_cmd_i (
.SDRST (SDRST), // output
.SDCLK (SDCLK), // output
.SDNCLK (SDNCLK), // output
.SDRST (SDRST), // output
.SDCLK (SDCLK), // output
.SDNCLK (SDNCLK), // output
.SDA (SDA[ADDRESS_NUMBER-1:0]), // output[14:0]
.SDBA (SDBA[2:0]), // output[2:0]
.SDWE (SDWE), // output
.SDRAS (SDRAS), // output
.SDCAS (SDCAS), // output
.SDCKE (SDCKE), // output
.SDODT (SDODT), // output
.SDD (SDD[15:0]), // inout[15:0]
.SDDML (SDDML), // inout
.DQSL (DQSL), // inout
.NDQSL (NDQSL), // inout
.SDDMU (SDDMU), // inout
.DQSU (DQSU), // inout
.NDQSU (NDQSU), // inout
.clk_in (clk_in), // input
.rst_in (rst_in), // input
.mclk (mclk), // output
.ref_clk (ref_clk), // output
.dly_data (dly_data[7:0]), // input[7:0]
.dly_addr (dly_addr[6:0]), // input[6:0]
.ld_delay (ld_delay), // input
.set (set), // input
.SDBA (SDBA[2:0]), // output[2:0]
.SDWE (SDWE), // output
.SDRAS (SDRAS), // output
.SDCAS (SDCAS), // output
.SDCKE (SDCKE), // output
.SDODT (SDODT), // output
.SDD (SDD[15:0]), // inout[15:0]
.SDDML (SDDML), // inout
.DQSL (DQSL), // inout
.NDQSL (NDQSL), // inout
.SDDMU (SDDMU), // inout
.DQSU (DQSU), // inout
.NDQSU (NDQSU), // inout
.clk_in (clk_in), // input
.rst_in (rst_in), // input
.mclk (mclk), // output
.mrst (mrst), // input
.ref_clk (ref_clk), // output
.idelay_ctrl_reset (idelay_ctrl_reset), // output
.dly_data (dly_data[7:0]), // input[7:0]
.dly_addr (dly_addr[6:0]), // input[6:0]
.ld_delay (ld_delay), // input
.set (set), // input
// .locked (locked), // output
.locked_mmcm (locked_mmcm), // output
.locked_pll (locked_pll), // output
.dly_ready (dly_ready), // output
.dci_ready (dci_ready), // output
.locked_mmcm (locked_mmcm), // output
.locked_pll (locked_pll), // output
.dly_ready (dly_ready), // output
.dci_ready (dci_ready), // output
.phy_locked_mmcm (phy_locked_mmcm), // output
.phy_locked_pll (phy_locked_pll), // output
.phy_dly_ready (phy_dly_ready), // output
.phy_dci_ready (phy_dci_ready), // output
.phy_locked_mmcm (phy_locked_mmcm), // output
.phy_locked_pll (phy_locked_pll), // output
.phy_dly_ready (phy_dly_ready), // output
.phy_dci_ready (phy_dci_ready), // output
.tmp_debug (tmp_debug_a[7:0]),
.ps_rdy (ps_rdy), // output
.ps_out (ps_out[7:0]), // output[7:0]
.phy_cmd_word (phy_cmd_word[31:0]), // input[31:0]
.phy_cmd_nop (phy_cmd_nop), // output
.phy_cmd_add_pause (phy_cmd_add_pause), // one pause cycle (for 8-bursts)
.add_pause (add_pause),
.pause_len (pause_len), // output [CMD_PAUSE_BITS-1:0]
.sequence_done (sequence_done), // output
.buf_wdata (buf_wdata[63:0]), // output[63:0]
.buf_rdata (buf_rdata[63:0]), // input[63:0]
.buf_wr (buf_wr_ndly), // output
.buf_rd (buf_rd), // output
.buf_rst (buf_rst), // reset external buffer address to page start
.cmda_en (cmda_en), // input
.ddr_rst (ddr_rst), // input
.dci_rst (dci_rst), // input
.dly_rst (dly_rst), // input
.ddr_cke (ddr_cke), // input
.inv_clk_div (inv_clk_div), // input
.dqs_pattern (dqs_pattern), // input[7:0]
.dqm_pattern (dqm_pattern), // input[7:0]
.ps_rdy (ps_rdy), // output
.ps_out (ps_out[7:0]), // output[7:0]
.phy_cmd_word (phy_cmd_word[31:0]), // input[31:0]
.phy_cmd_nop (phy_cmd_nop), // output
.phy_cmd_add_pause (phy_cmd_add_pause), // one pause cycle (for 8-bursts)
.add_pause (add_pause), // input
.pause_len (pause_len), // output [CMD_PAUSE_BITS-1:0]
.sequence_done (sequence_done), // output
.buf_wdata (buf_wdata[63:0]), // output[63:0]
.buf_rdata (buf_rdata[63:0]), // input[63:0]
.buf_wr (buf_wr_ndly), // output
.buf_rd (buf_rd), // output
.buf_rst (buf_rst), // reset external buffer address to page start
.cmda_en (cmda_en), // input
.ddr_rst (ddr_rst), // input
.dci_rst (dci_rst), // input
.dly_rst (dly_rst), // input
.ddr_cke (ddr_cke), // input
.inv_clk_div (inv_clk_div), // input
.dqs_pattern (dqs_pattern), // input[7:0]
.dqm_pattern (dqm_pattern), // input[7:0]
.dq_tri_on_pattern (dq_tri_on_pattern[3:0]), // input[3:0]
.dq_tri_off_pattern (dq_tri_off_pattern[3:0]), // input[3:0]
.dqs_tri_on_pattern (dqs_tri_on_pattern[3:0]), // input[3:0]
......@@ -628,21 +634,21 @@ module mcontr_sequencer #(
);
// delay buf_wr by 1-16 cycles to compensate for DDR and HDL code latency (~7 cycles?)
dly_16 #(2) buf_wr_dly_i (
.clk(mclk), // input
.rst(1'b0), // input
.dly(wbuf_delay[3:0]), // input[3:0]
.din({mem_read_mode & buf_rst,buf_wr_ndly}), // input
.dout({buf_rst_d, buf_wr}) // output reg
.clk (mclk), // input
.rst (mrst), // input
.dly (wbuf_delay[3:0]), // input[3:0]
.din ({mem_read_mode & buf_rst,buf_wr_ndly}), // input
.dout ({buf_rst_d, buf_wr}) // output reg
);
assign wbuf_delay_m1=wbuf_delay-1;
dly_16 #(6) buf_wchn_dly_i (
.clk(mclk), // input
.rst(1'b0), // input
.dly(wbuf_delay_m1), //wbuf_delay[3:0]-1), // input[3:0]
.din({run_seq_d, run_refresh_d, run_chn_d}), // input
.dout({run_w_d,run_refresh_w_d,run_chn_w_d}) // output reg
.clk (mclk), // input
.rst (mrst), // input
.dly (wbuf_delay_m1), //wbuf_delay[3:0]-1), // input[3:0]
.din ({run_seq_d, run_refresh_d, run_chn_d}), // input
.dout ({run_w_d,run_refresh_w_d,run_chn_w_d}) // output reg
);
//run_chn_w_d
endmodule
memctrl/phy/phy_cmd.v
View file @ b721ae66
......@@ -71,13 +71,14 @@ module phy_cmd#(
input clk_in,
input rst_in,
output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
input mrst, // @posedge mclk synchronous reset - should not interrupt mclk generation
output ref_clk, // global clock for idelay_ctrl calibration
output idelay_ctrl_reset,
// inteface to control I/O delays and mmcm
input [7:0] dly_data, // delay value (3 LSB - fine delay)
input [6:0] dly_addr, // select which delay to program
input ld_delay, // load delay data to selected iodelayl (clk_div synchronous)
input set, // clk_div synchronous set all delays from previously loaded values
// output locked,
output locked_mmcm,
output locked_pll,
output dly_ready,
......@@ -93,7 +94,6 @@ module phy_cmd#(
output ps_rdy,
output [PHASE_WIDTH-1:0] ps_out,
// command port
// input [35:0] phy_cmd,
input [31:0] phy_cmd_word,
output phy_cmd_nop,
output phy_cmd_add_pause, // one pause cycle (for 8-bursts)
......@@ -101,14 +101,12 @@ module phy_cmd#(
output [CMD_PAUSE_BITS-1:0] pause_len,
output sequence_done,
// external memory buffer (cs- channel select, high addresses- page addresses are decoded externally)
// output [ 6:0] buf_addr,
output [63:0] buf_wdata, // data to be written to the buffer (from DDR3), valid @ negedge mclk
input [63:0] buf_rdata, // data read from the buffer (to DDR3)
output buf_wr, // write buffer (next cycle!)
output buf_rd, // read buffer (ready next cycle)
output buf_rst, // reset external buffer address to page start
// extras
// input cmda_tri, // tristate command and address lines // not likely to be used
input cmda_en, // tristate command and address lines // not likely to be used
input ddr_rst, // generate reset to DDR3 memory (active high)
input dci_rst, // active high - reset DCI circuitry
......@@ -157,7 +155,6 @@ module phy_cmd#(
wire phy_buf_rd_cur; // connect to external buffer (but only if not paused)
wire phy_buf_rst_cur;
// wire clk;
wire clk_div;
reg [7:0] dly_data_r; // delay value (3 LSB - fine delay)
......@@ -176,10 +173,8 @@ module phy_cmd#(
wire phy_dci_dis_dqs;
reg dqs_tri_prev, dq_tri_prev;
// wire phy_locked;
wire phy_ps_rdy;
wire [PHASE_WIDTH-1:0] phy_ps_out;
// reg locked_r1,locked_r2;
reg ps_rdy_r1,ps_rdy_r2;
reg locked_mmcm_r1,locked_mmcm_r2;
reg locked_pll_r1, locked_pll_r2;
......@@ -195,16 +190,8 @@ module phy_cmd#(
reg [ 2:0] phy_bank_prev;
wire [ADDRESS_NUMBER-1:0] phy_addr_calm;
wire [ 2:0] phy_bank_calm;
// reg [ 8:0] extra_prev;
reg [ 9:0] extra_prev;
// assign phy_locked= phy_locked_mmcm && phy_locked_pll; // no dci and dly here
// output [63:0] buf_wdata, // data to be written to the buffer (from DDR3)
// SuppressWarnings VEditor
// (* keep = "true" *) wire phy_spare;
assign {
phy_addr_in,
phy_bank_in,
......@@ -216,7 +203,6 @@ module phy_cmd#(
phy_dqs_en_in, //phy_dqs_tri_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
phy_dqs_toggle_en, //enable toggle DQS according to the pattern
phy_dci_en_in, //phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
// phy_buf_addr, // connect to external buffer (is it needed? maybe just autoincrement?)
phy_buf_wr, // connect to external buffer (but only if not paused)
phy_buf_rd, // connect to external buffer (but only if not paused)
phy_cmd_add_pause, // add nop to current command
......@@ -260,13 +246,10 @@ module phy_cmd#(
assign phy_addr_calm= (phy_cmd_nop || add_pause) ? phy_addr_prev : phy_addr_in;
assign phy_bank_calm= (phy_cmd_nop || add_pause) ? phy_bank_prev : phy_bank_in;
// assign buf_addr = phy_buf_addr;
assign buf_wr = phy_buf_wr_cur;
assign buf_rd = phy_buf_rd_cur;
assign buf_rst= phy_buf_rst_cur;
// assign phy_addr= {phy_addr_in,phy_addr_in}; // also provides pause length when the command is NOP
// assign phy_bank= {phy_bank_in,phy_bank_in};
assign phy_addr= {phy_addr_calm,phy_addr_calm}; // also provides pause length when the command is NOP
assign phy_bank= {phy_bank_calm,phy_bank_calm};
assign phy_rcw= {phy_sel_cur?phy_rcw_in:3'h7, phy_sel_cur?3'h7:phy_rcw_in}; // {ras,cas,we}
......@@ -282,7 +265,6 @@ module phy_cmd#(
assign phy_dci_dis_dq = phy_dci_in; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
assign phy_dci_dis_dqs = phy_dci_in || phy_odt_cur; // In write leveling mode phy_dci_in = 0, phy_odt_cur=1 - use DCI on DQ only, no DQS
// assign locked = locked_r2;
assign ps_rdy = ps_rdy_r2;
assign ps_out = ps_out_r2;
......@@ -300,8 +282,8 @@ module phy_cmd#(
dq_tri_prev <= phy_dq_tri_in;
end
always @ (posedge mclk or posedge rst_in) begin
if (rst_in) begin
always @ (posedge mclk) begin
if (mrst) begin
phy_addr_prev <= 0;
phy_bank_prev <= 0;
extra_prev <= 0;
......@@ -325,9 +307,12 @@ module phy_cmd#(
end
// cross clock boundary posedge mclk -> posedge clk_div (mclk is later than clk_div)
always @ (posedge clk_div or posedge rst_in) begin
if (rst_in) begin
// cross clock boundary posedge mclk -> posedge clk_div (mclk is later than clk_div)
reg rst_clk_div = 1;
always @ (posedge clk_div) rst_clk_div <= mrst;
always @ (posedge clk_div) begin
if (rst_clk_div) begin
dly_data_r <= 0;
dly_addr_r <= 0;
ld_delay_r <= 0;
......@@ -343,7 +328,6 @@ module phy_cmd#(
// cross clock boundary posedge posedge clk_div->negedge clk_div -> posedge mclk (mclk is later than clk_div)
always @ (negedge clk_div) begin
// locked_r1 <= phy_locked;
ps_rdy_r1 <= phy_ps_rdy;
ps_out_r1 <= phy_ps_out;
......@@ -354,7 +338,6 @@ module phy_cmd#(
end
always @ (posedge mclk) begin
// locked_r2 <= locked_r1;
ps_rdy_r2 <= ps_rdy_r1;
ps_out_r2 <= ps_out_r1;
......@@ -405,63 +388,63 @@ module phy_cmd#(
.SS_MODE (SS_MODE),
.SS_MOD_PERIOD (SS_MOD_PERIOD)
) phy_top_i (
.ddr3_nrst (SDRST), // output
.ddr3_clk (SDCLK), // output
.ddr3_nclk (SDNCLK), // output
.ddr3_a (SDA[ADDRESS_NUMBER-1:0]), // output[14:0]
.ddr3_ba (SDBA[2:0]), // output[2:0]
.ddr3_we (SDWE), // output
.ddr3_ras (SDRAS), // output
.ddr3_cas (SDCAS), // output
.ddr3_cke (SDCKE), // output
.ddr3_odt (SDODT), // output
.dq (SDD[15:0]), // inout[15:0]
.dml (SDDML), // inout
.dqsl (DQSL), // inout
.ndqsl (NDQSL), // inout
.dmu (SDDMU), // inout
.dqsu (DQSU), // inout
.ndqsu (NDQSU), // inout
.clk_in (clk_in), // input
// .clk (clk), // output
.clk (), // output
.clk_div (clk_div), // output
.mclk (mclk), // output
.ref_clk (ref_clk), // output
.ddr3_nrst (SDRST), // output
.ddr3_clk (SDCLK), // output
.ddr3_nclk (SDNCLK), // output
.ddr3_a (SDA[ADDRESS_NUMBER-1:0]), // output[14:0]
.ddr3_ba (SDBA[2:0]), // output[2:0]
.ddr3_we (SDWE), // output
.ddr3_ras (SDRAS), // output
.ddr3_cas (SDCAS), // output
.ddr3_cke (SDCKE), // output
.ddr3_odt (SDODT), // output
.dq (SDD[15:0]), // inout[15:0]
.dml (SDDML), // inout
.dqsl (DQSL), // inout
.ndqsl (NDQSL), // inout
.dmu (SDDMU), // inout
.dqsu (DQSU), // inout
.ndqsu (NDQSU), // inout
.clk_in (clk_in), // input
.clk (), // output
.clk_div (clk_div), // output
.mclk (mclk), // output
.mrst (mrst), // input
.ref_clk (ref_clk), // output
.idelay_ctrl_reset (idelay_ctrl_reset), // output
.rst_in (rst_in), // input
.ddr_rst (ddr_rst), // input
.dci_rst (dci_rst), // input
.dly_rst (dly_rst), // input
.rst_in (rst_in), // input
.ddr_rst (ddr_rst), // input
.dci_rst (dci_rst), // input
.dly_rst (dly_rst), // input
.in_a (phy_addr[2*ADDRESS_NUMBER-1:0]), // input[29:0]
.in_ba (phy_bank[5:0]), // input[5:0]
.in_we ({phy_rcw[3],phy_rcw[0]}), // input[1:0]
.in_ras ({phy_rcw[5],phy_rcw[2]}), // input[1:0]
.in_cas ({phy_rcw[4],phy_rcw[1]}), // input[1:0]
.in_cke (phy_cke), // input[1:0]
.in_odt (phy_odt), // input[1:0]
.in_tri (cmda_tri), // input
.din (buf_rdata[63:0]), // input[63:0]
.din_dm (dqm_pattern[7:0]), // input[7:0]
.tin_dq (phy_dq_tri[7:0]), // input[7:0]
.din_dqs (dqs_data), // input[7:0]
.tin_dqs (phy_dqs_tri[7:0]), // input[7:0]
.dout (phy_rdata[63:0]), // output[63:0] @posedge clk_div
.inv_clk_div (inv_clk_div), // input
.dci_disable_dqs (phy_dci_dis_dqs), // input
.dci_disable_dq (phy_dci_dis_dq), // input
.dly_data (dly_data_r), // input[7:0]
.dly_addr (dly_addr_r), // input[6:0]
.ld_delay (ld_delay_r), // input
.set (set_r), // input
// .locked (phy_locked), // output
.locked_mmcm (phy_locked_mmcm), // output
.locked_pll (phy_locked_pll), // output
.dly_ready (phy_dly_ready), // output
.dci_ready (phy_dci_ready), // output
.tmp_debug (tmp_debug[7:0]),
.ps_rdy (phy_ps_rdy), // output
.ps_out (phy_ps_out) // output[7:0]
.in_ba (phy_bank[5:0]), // input[5:0]
.in_we ({phy_rcw[3],phy_rcw[0]}), // input[1:0]
.in_ras ({phy_rcw[5],phy_rcw[2]}), // input[1:0]
.in_cas ({phy_rcw[4],phy_rcw[1]}), // input[1:0]
.in_cke (phy_cke), // input[1:0]
.in_odt (phy_odt), // input[1:0]
.in_tri (cmda_tri), // input
.din (buf_rdata[63:0]), // input[63:0]
.din_dm (dqm_pattern[7:0]), // input[7:0]
.tin_dq (phy_dq_tri[7:0]), // input[7:0]
.din_dqs (dqs_data), // input[7:0]
.tin_dqs (phy_dqs_tri[7:0]), // input[7:0]
.dout (phy_rdata[63:0]), // output[63:0] @posedge clk_div
.inv_clk_div (inv_clk_div), // input
.dci_disable_dqs (phy_dci_dis_dqs), // input
.dci_disable_dq (phy_dci_dis_dq), // input
.dly_data (dly_data_r), // input[7:0]
.dly_addr (dly_addr_r), // input[6:0]
.ld_delay (ld_delay_r), // input
.set (set_r), // input
.locked_mmcm (phy_locked_mmcm), // output
.locked_pll (phy_locked_pll), // output
.dly_ready (phy_dly_ready), // output
.dci_ready (phy_dci_ready), // output
.tmp_debug (tmp_debug[7:0]), // output[7:0]
.ps_rdy (phy_ps_rdy), // output
.ps_out (phy_ps_out) // output[7:0]
);
endmodule
......
memctrl/phy/phy_top.v
View file @ b721ae66
......@@ -75,8 +75,10 @@ module phy_top #(
output clk, // free-running system clock, same frequency as iclk (shared for R/W), BUFR output
output clk_div, // free-running half clk frequency, front aligned to clk (shared for R/W), BUFR output
output mclk, // same as clk_div, through separate BUFG and static phase adjust
input mrst, // @posedge mclk synchronous reset - should not interrupt mclk generation
output ref_clk, // global clock for idelay_ctrl calibration
input rst_in, // reset delays/serdes
output idelay_ctrl_reset,
input rst_in, // reset delays/serdes - global reset?
input ddr_rst, // active high - generate NRST to memory
input dci_rst, // active high - reset DCI circuitry
input dly_rst, // active high - delay calibration circuitry
......@@ -116,10 +118,16 @@ module phy_top #(
output ps_rdy,
output [PHASE_WIDTH-1:0] ps_out
);
reg rst= 1'b1;
always @(negedge clk_div or posedge rst_in) begin
if (rst_in) rst <= 1'b1;
else rst <= 1'b0;
// always @(negedge clk_div or posedge rst_in) begin // Why is it @ negedge clk_div?
// if (rst_in) rst <= 1'b1;
// else rst <= 1'b0;
// end
always @(negedge clk_div) begin // Why is it @ negedge clk_div?
if (mrst) rst <= 1'b1;
else rst <= 1'b0;
end
wire ld_data_l = (dly_addr[6:5] == 2'h0) && ld_delay ;
......@@ -136,6 +144,7 @@ module phy_top #(
reg dbg1=0;
reg dbg2=0;
/*
always @ (posedge rst_in or posedge mclk) begin
if (rst_in) dbg1 <= 0;
else dbg1 <= ~dbg1;
......@@ -145,7 +154,17 @@ module phy_top #(
if (rst_in) dbg2 <= 0;
else dbg2 <= ~dbg2;
end
*/
always @ (posedge mclk) begin
if (mrst) dbg1 <= 0;
else dbg1 <= ~dbg1;
end
always @ (posedge clk_div) begin
if (mrst) dbg2 <= 0;
else dbg2 <= ~dbg2;
end
assign tmp_debug ={
dbg2, //dly_addr[1],
......@@ -153,7 +172,7 @@ module phy_top #(
clkin_stopped_mmcm,
clkfb_stopped_mmcm,
ddr_rst,
rst_in,
mrst, // rst_in, rst_in - is it global clock?
dci_rst,
dly_rst
};
......@@ -388,11 +407,12 @@ BUFG mclk_i (.O(mclk),.I(mclk_pre) );
.locked(locked_pll) // output
);
// Does it need to be re-calibrated periodically - yes when temperature changes, same as dci_reset
assign idelay_ctrl_reset = rst || dly_rst;
idelay_ctrl# (
.IODELAY_GRP("IODELAY_MEMORY")
) idelay_ctrl_i (
.refclk(ref_clk),
.rst(rst || dly_rst),
.rst(idelay_ctrl_reset), // route it to the top
.rdy(dly_ready)
);
dci_reset dci_reset_i (
......
memctrl/scheduler16.v
View file @ b721ae66
......@@ -24,7 +24,7 @@ module scheduler16 #(
parameter width=16, // counter number of bits
parameter n_chn=16 // number of channels
)(
input rst,
input mrst,
input clk,
input [n_chn-1:0] chn_en, // channel enable mask
input [n_chn-1:0] want_rq, // both want_rq and need_rq should go inactive after being granted
......@@ -60,8 +60,8 @@ module scheduler16 #(
generate
genvar i;
for (i=0;i<n_chn;i=i+1) begin: pri_reg_block
always @ (posedge rst or posedge clk) begin
if (rst) pri_reg[width*i +: width] <= 0;
always @ (posedge clk) begin
if (mrst) pri_reg[width*i +: width] <= 0;
else if (pgm_en && (pgm_addr==i)) pri_reg[width*i +: width] <= pgm_data;
end
end
......@@ -81,8 +81,8 @@ module scheduler16 #(
assign next_want_conf= (want_conf & want_rq & chn_en) | want_set;
assign next_need_conf= (need_conf & need_rq & chn_en) | need_set;
assign need_want_conf_w=need_some? next_need_conf: next_want_conf;
always @(posedge rst or posedge clk) begin
if (rst) begin
always @(posedge clk) begin
if (mrst) begin
want_conf <= 0;
need_conf <= 0;
end else begin
......@@ -126,8 +126,8 @@ module scheduler16 #(
.index (index[3:0]),
.valid (index_valid),
.need_out (need));
always @(posedge rst or posedge clk) begin
if (rst) begin
always @(posedge clk) begin
if (mrst) begin
grant_r <=0;
grant_sent <=0;
grant_chn_r <=0;
......
sensor/pxd_single.v
View file @ b721ae66
......@@ -38,7 +38,8 @@ module pxd_single#(
output pxd_in, // data output (@posedge ipclk?)
input ipclk, // restored clock from the sensor, phase-shifted
input ipclk2x, // restored clock from the sensor, phase-shifted, twice frequency
input rst, // reset
input mrst, // reset @ posxedge mclk
input irst, // reset @ posxedge iclk
input mclk, // clock for setting delay values
input [7:0] dly_data, // delay value (3 LSB - fine delay) - @posedge mclk
input set_idelay, // mclk synchronous load idelay value
......@@ -52,9 +53,9 @@ module pxd_single#(
assign pxd_in=pxd_r;
assign pxd_async = pxd_iobuf;
always @ (posedge rst or posedge mclk) begin
if (rst) pxd_r <= 0;
else pxd_r <= quadrant[1]?(quadrant[0]? dout[3]: dout[2]) : (quadrant[0]? dout[1]: dout[0]);
always @ (posedge mclk) begin
if (mrst) pxd_r <= 0;
else pxd_r <= quadrant[1]?(quadrant[0]? dout[3]: dout[2]) : (quadrant[0]? dout[1]: dout[0]);
end
iobuf #(
......@@ -94,7 +95,7 @@ module pxd_single#(
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE)
) pxd_dly_i(
.clk (mclk),
.rst (rst),
.rst (mrst),
.set (set_idelay),
.ld (ld_idelay),
.delay (dly_data[7:3]),
......@@ -109,7 +110,7 @@ module pxd_single#(
.oclk(ipclk2x), // system clock, phase should allow iclk-to-oclk jitter with setup/hold margin
.oclk_div(ipclk), // oclk divided by 2, front aligned
.inv_clk_div(1'b0), // invert oclk_div (this clock is shared between iserdes and oserdes. Works only in MEMORY_DDR3 mode?
.rst(rst), // reset
.rst(irst), // reset
.d_direct(1'b0), // direct input from IOB, normally not used, controlled by IOBDELAY parameter (set to "NONE")
.ddly(pxd_delayed), // serial input from idelay
.dout(dout[3:0]) // parallel data out
......
sensor/sens_gamma.v
View file @ b721ae66
......@@ -40,7 +40,7 @@ module sens_gamma #(
parameter SENS_GAMMA_MODE_REPET = 4,
parameter SENS_GAMMA_MODE_TRIG = 5
) (
input rst,
// input rst,
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
//input en, // @(posedge pclk) // Enable. Should go active before or with the first hact going active.
// when low will also reset MSB of addresses - buffer page for ping-pong access.
......@@ -52,6 +52,9 @@ module sens_gamma #(
// 3 (optional) - after frame is over (before the first hact of the next one)
// turn "en" off. If needed to restart - go to step 1 to keep buffer pages in sync.
input mrst, // @mclk sync reset
input prst, // @mclk sync reset
input [15:0] pxd_in, // @(posedge pclk)
input hact_in,
input sof_in, // start of frame, single pclk, input
......@@ -183,40 +186,40 @@ module sens_gamma #(
assign sof_masked= sof_in && (pend_trig || repet_mode) && en_input;
assign trig = trig_in || trig_soft;
always @ (posedge rst or posedge mclk) begin
if (rst) tdata <= 0;
always @ (posedge mclk) begin
if (mrst) tdata <= 0;
else if (set_taddr_w) tdata <= cmd_data[17:0];
if (rst) set_tdata_r <= 0;
else set_tdata_r <= set_tdata_w;
if (mrst) set_tdata_r <= 0;
else set_tdata_r <= set_tdata_w;
if (rst) taddr <= 0;
if (mrst) taddr <= 0;
else if (set_taddr_w) taddr <= cmd_data[12:0];
else if (set_tdata_r) taddr <= taddr + 1;
if (rst) mode_mclk <= 0;
if (mrst) mode_mclk <= 0;
else if (set_ctrl_w) mode_mclk <= cmd_data[SENS_GAMMA_MODE_WIDTH-1:0];
if (rst) set_tdata_ram <=0;
else set_tdata_ram <= {4{set_tdata_w}} &
if (mrst) set_tdata_ram <=0;
else set_tdata_ram <= {4{set_tdata_w}} &
{ taddr[12] & taddr[11],
taddr[12] & ~taddr[11],
~taddr[12] & taddr[11],
~taddr[12] & ~taddr[11]};
if (rst) height0_m1 <= 0;
if (mrst) height0_m1 <= 0;
else if (set_height01_w) height0_m1 <= cmd_data[15:0];
if (rst) height1_m1 <= 0;
if (mrst) height1_m1 <= 0;
else if (set_height01_w) height1_m1 <= cmd_data[31:16];
if (rst) height2_m1 <= 0;
if (mrst) height2_m1 <= 0;
else if (set_height2_w) height2_m1 <= cmd_data[15:0];
end
always @ (posedge rst or posedge pclk) begin
if (rst) begin
always @ (posedge pclk) begin
if (prst) begin
mode <= 0;
hact_d[4:0] <= 0;
bayer_nset <= 0;
......@@ -277,8 +280,9 @@ module sens_gamma #(
.ADDR_WIDTH (2),
.DATA_WIDTH (32)
) cmd_deser_sens_io_i (
.rst (rst), // input
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[15:0]
......@@ -290,7 +294,7 @@ module sens_gamma #(
.WIDTH(8)
) dly_16_pxd_i (
.clk (pclk), // input
.rst (rst), // input
.rst (prst), // input
.dly (3), // input[3:0]
.din (pxd_in[7:0]), // input[0:0]
.dout(pxd_in_d3) // output[0:0]
......@@ -300,13 +304,13 @@ module sens_gamma #(
.WIDTH(2)
) dly_16_sof_eof_i (
.clk (pclk), // input
.rst (rst), // input
.rst (prst), // input
.dly (4), // input[3:0]
.din ({eof_in, sof_masked}), // input[0:0]
.dout({eof_out,sof_out}) // output[0:0]
);
pulse_cross_clock trig_soft_i (
.rst (rst),
.rst (mrst),
.src_clk (mclk),
.dst_clk (pclk),
.in_pulse (cmd_data[SENS_GAMMA_MODE_TRIG] && set_ctrl_w),
......
sensor/sens_histogram.v
View file @ b721ae66
......@@ -27,7 +27,9 @@ module sens_histogram #(
parameter HISTOGRAM_LEFT_TOP = 'h0,
parameter HISTOGRAM_WIDTH_HEIGHT = 'h1 // 1.. 2^16, 0 - use HACT
)(
input rst,
// input rst,
input mrst, // @posedge mclk, sync reset
input prst, // @posedge pclk, sync reset
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
input pclk2x,
input sof,
......@@ -263,8 +265,9 @@ module sens_histogram #(
.ADDR2 (0),
.ADDR_MASK2 (0)
) cmd_deser_sens_histogram_i (
.rst (rst), // input
.rst (1'b0), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (pio_addr), // output[15:0]
......@@ -273,7 +276,7 @@ module sens_histogram #(
);
pulse_cross_clock pulse_cross_clock_lt_i (
.rst (rst), // input
.rst (mrst), // input
.src_clk (mclk), // input
.dst_clk (pclk), // input
.in_pulse (set_left_top_w), // input
......@@ -282,7 +285,7 @@ module sens_histogram #(
);
pulse_cross_clock pulse_cross_clock_wh_i (
.rst (rst), // input
.rst (mrst), // input
.src_clk (mclk), // input
.dst_clk (pclk), // input
.in_pulse (set_width_height_w), // input
......@@ -291,7 +294,7 @@ module sens_histogram #(
);
pulse_cross_clock pulse_cross_clock_hist_done_i (
.rst (rst), // input
.rst (prst), // input
.src_clk (pclk), // input
.dst_clk (mclk), // input
.in_pulse (hist_done), // input
......@@ -300,7 +303,7 @@ module sens_histogram #(
);
pulse_cross_clock pulse_cross_clock_hist_xfer_done_i (
.rst (rst), // input
.rst (mrst), // input
.src_clk (mclk), // input
.dst_clk (pclk), // input
.in_pulse (hist_xfer_done_mclk), // input
......
sensor/sens_parallel12.v
View file @ b721ae66
......@@ -75,8 +75,12 @@ module sens_parallel12 #(
parameter SENS_SS_MOD_PERIOD = 10000 // integer 4000-40000 - SS modulation period in ns
)(
input rst,
// input rst,
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
input mclk_rst,
input prst,
output irst,
output ipclk, // re-generated sensor output clock (regional clock to drive external fifo)
output ipclk2x,// twice frequency regenerated sensor clock (possibly to run external fifo)
// input pclk2x, // maybe not needed here
......@@ -117,10 +121,9 @@ module sens_parallel12 #(
input status_start // Acknowledge of the first status packet byte (address)
);
// wire tdi,tdo,done,tms,tck,ten;
reg [2:0] irst_r;
wire ibpf;
wire ipclk_pre, ipclk2x_pre;
// wire ipclk, ipclk2x;
reg [31:0] data_r;
reg [3:0] set_idelay;
......@@ -182,76 +185,84 @@ module sens_parallel12 #(
assign hact_out = hact_r;
assign iaro = trigger_mode? ~trig : iaro_soft;
always @(posedge rst or posedge mclk) begin
if (rst) data_r <= 0;
else if (cmd_we) data_r <= cmd_data;
if (rst) set_idelay <= 0;
else set_idelay <= {4{cmd_we}} & {(cmd_a==(SENSIO_DELAYS+3)),
assign irst=irst_r[2];
always @ (posedge ipclk) begin
irst_r <= {irst_r[1:0], prst};
end
always @(posedge mclk) begin
if (mclk_rst) data_r <= 0;
else if (cmd_we) data_r <= cmd_data;
if (mclk_rst) set_idelay <= 0;
else set_idelay <= {4{cmd_we}} & {(cmd_a==(SENSIO_DELAYS+3)),
(cmd_a==(SENSIO_DELAYS+2)),
(cmd_a==(SENSIO_DELAYS+1)),
(cmd_a==(SENSIO_DELAYS+0))};
if (rst) set_status_r <=0;
else set_status_r <= cmd_we && (cmd_a== SENSIO_STATUS);
if (rst) set_ctrl_r <=0;
else set_ctrl_r <= cmd_we && (cmd_a== SENSIO_CTRL);
if (rst) set_jtag_r <=0;
else set_jtag_r <= cmd_we && (cmd_a== SENSIO_JTAG);
if (mclk_rst) set_status_r <=0;
else set_status_r <= cmd_we && (cmd_a== SENSIO_STATUS);
if (mclk_rst) set_ctrl_r <=0;
else set_ctrl_r <= cmd_we && (cmd_a== SENSIO_CTRL);
if (mclk_rst) set_jtag_r <=0;
else set_jtag_r <= cmd_we && (cmd_a== SENSIO_JTAG);
if (rst) xpgmen <= 0;
if (mclk_rst) xpgmen <= 0;
else if (set_jtag_r && data_r[SENS_JTAG_PGMEN + 1]) xpgmen <= data_r[SENS_JTAG_PGMEN];
if (rst) xfpgaprog <= 0;
if (mclk_rst) xfpgaprog <= 0;
else if (set_jtag_r && data_r[SENS_JTAG_PROG + 1]) xfpgaprog <= data_r[SENS_JTAG_PROG];
if (rst) xfpgatck <= 0;
if (mclk_rst) xfpgatck <= 0;
else if (set_jtag_r && data_r[SENS_JTAG_TCK + 1]) xfpgatck <= data_r[SENS_JTAG_TCK];
if (rst) xfpgatms <= 0;
if (mclk_rst) xfpgatms <= 0;
else if (set_jtag_r && data_r[SENS_JTAG_TMS + 1]) xfpgatms <= data_r[SENS_JTAG_TMS];
if (rst) xfpgatdi <= 0;
if (mclk_rst) xfpgatdi <= 0;
else if (set_jtag_r && data_r[SENS_JTAG_TDI + 1]) xfpgatdi <= data_r[SENS_JTAG_TDI];
if (rst) imrst <= 0;
if (mclk_rst) imrst <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_MRST + 1]) imrst <= data_r[SENS_CTRL_MRST];
if (rst) iarst <= 0;
if (mclk_rst) iarst <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_ARST + 1]) iarst <= data_r[SENS_CTRL_ARST];
if (rst) iaro_soft <= 0;
if (mclk_rst) iaro_soft <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_MRST + 1]) iaro_soft <= data_r[SENS_CTRL_ARO];
if (rst) rst_mmcm <= 0;
if (mclk_rst) rst_mmcm <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_RST_MMCM + 1]) rst_mmcm <= data_r[SENS_CTRL_RST_MMCM];
if (rst) sel_ext_clk <= 0;
if (mclk_rst) sel_ext_clk <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_EXT_CLK + 1]) sel_ext_clk <= data_r[SENS_CTRL_EXT_CLK];
if (rst) quadrants <= 0;
if (mclk_rst) quadrants <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_QUADRANTS + 8]) quadrants <= data_r[SENS_CTRL_QUADRANTS+:6];
if (rst) ld_idelay <= 0;
else ld_idelay <= set_ctrl_r && data_r[SENS_CTRL_LD_DLY];
if (mclk_rst) ld_idelay <= 0;
else ld_idelay <= set_ctrl_r && data_r[SENS_CTRL_LD_DLY];
if (rst) set_width_r <= 0;
else set_width_r <= {set_width_r[0],cmd_we && (cmd_a== SENSIO_WIDTH)};
if (mclk_rst) set_width_r <= 0;
else set_width_r <= {set_width_r[0],cmd_we && (cmd_a== SENSIO_WIDTH)};
if (rst) line_width_m1 <= 0;
if (mclk_rst) line_width_m1 <= 0;
else if (set_width_r[1]) line_width_m1 <= data_r[LINE_WIDTH_BITS-1:0] -1;
if (rst) line_width_internal <= 0;
if (mclk_rst) line_width_internal <= 0;
else if (set_width_r[1]) line_width_internal <= ~ (|data_r[LINE_WIDTH_BITS:0]);
// regenerate/propagate HACT
if (rst) hact_ext_r <= 1'b0;
else hact_ext_r <= hact_ext;
if (mclk_rst) hact_ext_r <= 1'b0;
else hact_ext_r <= hact_ext;
if (rst) hact_r <= 0;
if (mclk_rst) hact_r <= 0;
else if (hact_ext && !hact_ext_r) hact_r <= 1;
else if (line_width_internal?(hact_cntr == 0):( hact_ext ==0)) hact_r <= 0;
if (rst) hact_cntr <= 0;
if (mclk_rst) hact_cntr <= 0;
else if (hact_ext && !hact_ext_r) hact_cntr <= line_width_m1;
else if (hact_r) hact_cntr <= hact_cntr - 1;
......@@ -296,27 +307,29 @@ module sens_parallel12 #(
.ADDR_WIDTH (3),
.DATA_WIDTH (32)
) cmd_deser_sens_io_i (
.rst (rst), // input
.clk (mclk), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[15:0]
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mclk_rst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[15:0]
.data (cmd_data), // output[31:0]
.we (cmd_we) // output
.we (cmd_we) // output
);
status_generate #(
.STATUS_REG_ADDR(SENSIO_STATUS_REG),
.PAYLOAD_BITS(15) // STATUS_PAYLOAD_BITS)
) status_generate_sens_io_i (
.rst (rst), // input
.clk (mclk), // input
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mclk_rst), // input
.we (set_status_r), // input
.wd (data_r[7:0]), // input[7:0]
.status (status), // input[25:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
.wd (data_r[7:0]), // input[7:0]
.status (status), // input[25:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
);
......@@ -334,13 +347,14 @@ module sens_parallel12 #(
.HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE)
) pxd_pxd0_i (
.pxd (pxd[0]), // inout
.pxd_out (xfpgatdi), // input
.pxd_en (xpgmen), // input
.pxd_async (), // output
.pxd_out (xfpgatdi), // input
.pxd_en (xpgmen), // input
.pxd_async (), // output
.pxd_in (pxd_out[0]), // output
.ipclk (ipclk), // input
.ipclk2x (ipclk2x), // input
.rst (rst), // input
.mrst (mclk_rst), // input
.irst (irst), // input
.mclk (mclk), // input
.dly_data (data_r[7:0]), // input[7:0]
.set_idelay (set_pxd_delay[0]),// input
......@@ -365,7 +379,8 @@ module sens_parallel12 #(
.pxd_in (pxd_out[1]), // output
.ipclk (ipclk), // input
.ipclk2x (ipclk2x), // input
.rst (rst), // input
.mrst (mclk_rst), // input
.irst (irst), // input
.mclk (mclk), // input
.dly_data (data_r[15:8]), // input[7:0]
.set_idelay (set_pxd_delay[0]),// input
......@@ -393,7 +408,8 @@ module sens_parallel12 #(
.pxd_in (pxd_out[i]), // output
.ipclk (ipclk), // input
.ipclk2x (ipclk2x), // input
.rst (rst), // input
.mrst (mclk_rst), // input
.irst (irst), // input
.mclk (mclk), // input
// .dly_data (data_r[8*((i+2)&3)+:8]), // input[7:0] alternating bytes of 32-bit word
// .set_idelay (set_pxd_delay[(i+2)>>2]),// input 0 for pxd[3:2], 1 for pxd[7:4], 2 for pxd [11:8]
......@@ -422,9 +438,10 @@ module sens_parallel12 #(
.pxd_in (hact_ext), // output
.ipclk (ipclk), // input
.ipclk2x (ipclk2x), // input
.rst (rst), // input
.mrst (mclk_rst), // input
.irst (irst), // input
.mclk (mclk), // input
.dly_data (data_r[7:0]), // input[7:0]
.dly_data (data_r[7:0]), // input[7:0]
.set_idelay (set_other_delay),// input
.ld_idelay (ld_idelay), // input
.quadrant (quadrants[3:2]) // input[1:0]
......@@ -447,7 +464,8 @@ module sens_parallel12 #(
.pxd_in (vact_out), // output
.ipclk (ipclk), // input
.ipclk2x (ipclk2x), // input
.rst (rst), // input
.mrst (mclk_rst), // input
.irst (irst), // input
.mclk (mclk), // input
.dly_data (data_r[15:8]), // input[7:0]
.set_idelay (set_other_delay),// input
......@@ -469,7 +487,7 @@ module sens_parallel12 #(
.pxclk_out (1'b0), // input
.pxclk_en (1'b0), // input
.pxclk_in (ibpf), // output
.rst (rst), // input
.rst (mclk_rst), // input
.mclk (mclk), // input
.dly_data (data_r[23:16]), // input[7:0]
.set_idelay (set_other_delay), // input
......@@ -485,7 +503,7 @@ module sens_parallel12 #(
) dclk_i (
.clk (pclk), // input
.ce (1'b1), // input
.rst (rst), // input
.rst (prst), // input
.set (1'b0), // input
.din (2'b01), // input[1:0]
.tin (1'b0), // input
......@@ -549,11 +567,11 @@ module sens_parallel12 #(
// pullup for mrst (used as input for "DONE") and senspgm (grounded on sensor boards)
mpullup i_mrst_pullup(mrst);
mpullup i_senspgm_pullup(senspgm);
always @ (posedge mclk or posedge rst) begin
if (rst) force_senspgm <= 0;
always @ (posedge mclk) begin
if (mclk_rst) force_senspgm <= 0;
else if (xpgmen_d[1:0]==2'b10) force_senspgm <= senspgmin;
if (rst) xpgmen_d <= 0;
else xpgmen_d <= {xpgmen_d[0], xpgmen};
if (mclk_rst) xpgmen_d <= 0;
else xpgmen_d <= {xpgmen_d[0], xpgmen};
end
// generate phase-shifterd pixel clock (and 2x version) from either the internal clock (that is output to the sensor) or from the clock
......@@ -627,7 +645,7 @@ module sens_parallel12 #(
generate
if (BUF_IPCLK == "BUFG") BUFG clk1x_i (.O(ipclk), .I(ipclk_pre));
else if (BUF_IPCLK == "BUFH") BUFH clk1x_i (.O(ipclk), .I(ipclk_pre));
else if (BUF_IPCLK == "BUFR") BUFR clk1x_i (.O(ipclk), .I(ipclk_pre), .CE(1'b1), .CLR(rst));
else if (BUF_IPCLK == "BUFR") BUFR clk1x_i (.O(ipclk), .I(ipclk_pre), .CE(1'b1), .CLR(prst));
else if (BUF_IPCLK == "BUFMR") BUFMR clk1x_i (.O(ipclk), .I(ipclk_pre));
else if (BUF_IPCLK == "BUFIO") BUFIO clk1x_i (.O(ipclk), .I(ipclk_pre));
else assign ipclk = ipclk_pre;
......@@ -636,7 +654,7 @@ module sens_parallel12 #(
generate
if (BUF_IPCLK2X == "BUFG") BUFG clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));
else if (BUF_IPCLK2X == "BUFH") BUFH clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));
else if (BUF_IPCLK2X == "BUFR") BUFR clk2x_i (.O(ipclk2x), .I(ipclk2x_pre), .CE(1'b1), .CLR(rst));
else if (BUF_IPCLK2X == "BUFR") BUFR clk2x_i (.O(ipclk2x), .I(ipclk2x_pre), .CE(1'b1), .CLR(prst));
else if (BUF_IPCLK2X == "BUFMR") BUFMR clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));
else if (BUF_IPCLK2X == "BUFIO") BUFIO clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));
else assign ipclk2x = ipclk2x_pre;
......
sensor/sens_sync.v
View file @ b721ae66
......@@ -33,9 +33,11 @@ module sens_sync#(
parameter SENS_SYNC_MINPER = 130 // minimal frame period (in pclk/mclk?)
)(
input rst, // global reset
// input rst, // global reset
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
input mclk, // global system clock, synchronizes commands
input mrst, // @mclk sync reset
input prst, // @mclk sync reset
input en, // @pclk enable channel (0 resets counters)
input sof_in, // @pclk start of frame input, single-cycle
input eof_in, // @pclk end of frame input, single-cycle (to limit sof_late
......@@ -144,8 +146,9 @@ module sens_sync#(
.ADDR2 (0),
.ADDR_MASK2 (0)
) cmd_deser_sens_sync_i (
.rst (rst), // input
.rst (1'b0), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[15:0]
......@@ -155,7 +158,7 @@ module sens_sync#(
// mclk -> pclk
pulse_cross_clock pulse_cross_clock_set_data_pclk_i (
.rst (rst), // input
.rst (mrst), // input
.src_clk (mclk), // input
.dst_clk (pclk), // input
.in_pulse (set_data_mclk), // input
......@@ -164,7 +167,7 @@ module sens_sync#(
);
pulse_cross_clock pulse_cross_clock_trig_in_pclk_i (
.rst (rst), // input
.rst (mrst), // input
.src_clk (mclk), // input
.dst_clk (pclk), // input
.in_pulse (trig_in), // input
......@@ -174,7 +177,7 @@ module sens_sync#(
// pclk -> mclk
pulse_cross_clock pulse_cross_clock_sof_out_i (
.rst (rst), // input
.rst (prst), // input
.src_clk (pclk), // input
.dst_clk (mclk), // input
.in_pulse (pre_sof_out), // input
......@@ -182,17 +185,13 @@ module sens_sync#(
.busy() // output
);
pulse_cross_clock pulse_cross_clock_sof_late_i (
.rst (rst), // input
.rst (prst), // input
.src_clk (pclk), // input
.dst_clk (mclk), // input
.in_pulse (pre_sof_late), // input
.out_pulse (sof_late), // output
.busy() // output
);
endmodule
sensor/sensor_channel.v
View file @ b721ae66
......@@ -158,9 +158,12 @@ module sensor_channel#(
parameter SENS_SS_MOD_PERIOD = 10000 // integer 4000-40000 - SS modulation period in ns
) (
input rst,
// input rst,
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
input pclk2x, // global clock input, double pixel rate (192MHz for MT9P006)
input mrst, // @posedge mclk, sync reset
input prst, // @posedge pclk, sync reset
// I/O pads, pin names match circuit diagram
inout [7:0] sns_dp,
inout [7:0] sns_dn,
......@@ -306,8 +309,8 @@ module sensor_channel#(
cmd_stb <= cmd_stb_in;
end
always @ (posedge rst or posedge mclk) begin
if (rst) mode <= 0;
always @ (posedge mclk) begin
if (mrst) mode <= 0;
else if (sensor_ctrl_we) mode <= sensor_ctrl_data[SENSOR_MODE_WIDTH-1:0];
end
......@@ -327,8 +330,9 @@ module sensor_channel#(
level_cross_clocks level_cross_clocks_en_pclk_i (.clk(pclk), .d_in(en_mclk), .d_out(en_pclk));
status_router2 status_router2_sensor_i (
.rst (rst), // input
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.db_in0 (sens_i2c_status_ad), // input[7:0]
.rq_in0 (sens_i2c_status_rq), // input
.start_in0 (sens_i2c_status_start), // output
......@@ -347,8 +351,9 @@ module sensor_channel#(
.ADDR_WIDTH (1),
.DATA_WIDTH (32)
) cmd_deser_sens_channel_i (
.rst (rst), // input
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (), // output[0:0] - not used
......@@ -370,7 +375,7 @@ module sensor_channel#(
.SENSI2C_IOSTANDARD (SENSI2C_IOSTANDARD),
.SENSI2C_SLEW (SENSI2C_SLEW)
) sensor_i2c_io_i (
.rst (rst), // input
.mrst (mrst), // input
.mclk (mclk), // input
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
......@@ -381,7 +386,7 @@ module sensor_channel#(
.scl (sns_scl), // inout
.sda (sns_sda) // inout
);
wire irst; // @ posedge ipclk
sens_parallel12 #(
.SENSIO_ADDR (SENSIO_ADDR),
.SENSIO_ADDR_MASK (SENSIO_ADDR_MASK),
......@@ -427,8 +432,11 @@ module sensor_channel#(
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD)
) sens_parallel12_i (
.rst (rst), // input
// .rst (rst), // input
.pclk (pclk), // input
.mclk_rst (mrst), // input
.prst (prst), // input
.irst (irst), // output
.ipclk (ipclk), // output
.ipclk2x (), // ipclk2x), // output
.trigger_mode (trigger_mode), // input
......@@ -458,9 +466,11 @@ module sensor_channel#(
.SENSOR_FIFO_2DEPTH (SENSOR_FIFO_2DEPTH),
.SENSOR_FIFO_DELAY (SENSOR_FIFO_DELAY)
) sensor_fifo_i (
.rst (rst), // input
// .rst (rst), // input
.iclk (ipclk), // input
.pclk (pclk), // input
.prst (prst), // input
.irst (irst), // input
.pxd_in (pxd_to_fifo), // input[11:0]
.vact (vact_to_fifo), // input
.hact (hact_to_fifo), // input
......@@ -481,9 +491,10 @@ module sensor_channel#(
.SENS_SYNC_MINBITS (SENS_SYNC_MINBITS),
.SENS_SYNC_MINPER (SENS_SYNC_MINPER)
) sens_sync_i (
.rst (rst), // input
.pclk (pclk), // input
.mclk (mclk), // input
.mrst (mrst), // input
.prst (prst), // input
.en (en_pclk), // input @pclk
.sof_in (sof), // input
.eof_in (eof), // input
......@@ -514,8 +525,10 @@ module sensor_channel#(
.SENS_GAMMA_MODE_REPET (SENS_GAMMA_MODE_REPET),
.SENS_GAMMA_MODE_TRIG (SENS_GAMMA_MODE_TRIG)
) sens_gamma_i (
.rst (rst), // input
// .rst (rst), // input
.pclk (pclk), // input
.mrst (mrst), // input
.prst (prst), // input
.pxd_in (gamma_pxd_in), // input[15:0]
.hact_in (gamma_hact_in), // input
.sof_in (gamma_sof_in), // input
......@@ -540,7 +553,9 @@ module sensor_channel#(
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT)
) sens_histogram_i (
.rst (rst), // input
// .rst (rst), // input
.mrst (mrst), // input
.prst (prst), // input
.pclk (pclk), // input
.pclk2x (pclk2x), // input
.sof (gamma_sof_out), // input
......@@ -572,7 +587,9 @@ module sensor_channel#(
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT)
) sens_histogram_i (
.rst (rst), // input
// .rst (rst), // input
.mrst (mrst), // input
.prst (prst), // input
.pclk (pclk), // input
.pclk2x (pclk2x), // input
.sof (gamma_sof_out), // input
......@@ -604,7 +621,9 @@ module sensor_channel#(
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT)
) sens_histogram_i (
.rst (rst), // input
// .rst (rst), // input
.mrst (mrst), // input
.prst (prst), // input
.pclk (pclk), // input
.pclk2x (pclk2x), // input
.sof (gamma_sof_out), // input
......@@ -636,7 +655,9 @@ module sensor_channel#(
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT)
) sens_histogram_i (
.rst (rst), // input
// .rst (rst), // input
.mrst (mrst), // input
.prst (prst), // input
.pclk (pclk), // input
.pclk2x (pclk2x), // input
.sof (gamma_sof_out), // input
......
sensor/sensor_fifo.v
View file @ b721ae66
......@@ -25,9 +25,12 @@ module sensor_fifo #(
parameter SENSOR_FIFO_2DEPTH = 4, // 4-bit address
parameter SENSOR_FIFO_DELAY = 7 // approxiametly half (1 << SENSOR_FIFO_2DEPTH) - how long to wait after getting HACT on FIFO before stering it on output
)(
input rst,
// input rst,
input iclk, // input -synchronous clock
input pclk, // internal lixel clock
input prst, // @ posedge pclk
input irst, // @ posedge iclk
input [SENSOR_DATA_WIDTH-1:0] pxd_in, // sensor data @posedge iclk
input vact,
input hact,
......@@ -50,34 +53,36 @@ module sensor_fifo #(
wire hact_out_start;
assign we=sof_in || eof_in || hact || hact_r;
always @(posedge rst or posedge iclk) begin
if (rst) {vact_r,hact_r,sof_in,eof_in} <= 0;
else {vact_r,hact_r,sof_in,eof_in} <= {vact,hact, vact && ! vact_r, vact_r && !vact};
always @(posedge iclk) begin
if (irst) {vact_r,hact_r,sof_in,eof_in} <= 0;
else {vact_r,hact_r,sof_in,eof_in} <= {vact,hact, vact && ! vact_r, vact_r && !vact};
end
fifo_cross_clocks #(
.DATA_WIDTH(SENSOR_DATA_WIDTH+3),
.DATA_DEPTH(SENSOR_FIFO_2DEPTH)
) fifo_cross_clocks_i (
.rst (rst), // input
.rclk (pclk), // input
.wclk (iclk), // input
.we (we), // input
.re (re), // input
.rst (1'b0), // rst), // input
.rrst (prst), // input
.wrst (irst), // input
.rclk (pclk), // input
.wclk (iclk), // input
.we (we), // input
.re (re), // input
.data_in ({eof_in, sof_in, hact, pxd_in}), // input[15:0]
.data_out ({eof_w, sof_w, hact_w, pxd_w}), // output[15:0]
.nempty (nempty), // output
.half_empty () // output
.half_empty () // output
);
dly_16 #(
.WIDTH(1)
) hact_dly_16_i (
.clk(pclk), // input
.rst(rst), // input
.dly(SENSOR_FIFO_DELAY), // input[3:0]
.clk(pclk), // input
.rst(prst), // input
.dly(SENSOR_FIFO_DELAY), // input[3:0]
.din(pre_hact[0] && ! pre_hact[1]), // input[0:0]
.dout(hact_out_start) // output[0:0]
.dout(hact_out_start) // output[0:0]
);
// output clock domain
......@@ -89,28 +94,28 @@ module sensor_fifo #(
assign sof = sof_r;
assign eof = eof_r;
always @(posedge rst or posedge iclk) begin
if (rst) re_r <= 0;
else re_r <= pre_re;
always @(posedge iclk) begin
if (irst) re_r <= 0;
else re_r <= pre_re;
if (rst) pre_hact[0] <= 0;
if (irst) pre_hact[0] <= 0;
else if (re) pre_hact[0] <= hact_w;
if (rst) pre_hact[1] <= 0;
if (irst) pre_hact[1] <= 0;
else if (re) pre_hact[1] <= pre_hact[0];
if (rst) pxd_r <= 0;
if (irst) pxd_r <= 0;
else if (re) pxd_r <= pxd_w;
if (rst) hact_out_r <= 0;
if (irst) hact_out_r <= 0;
else if (hact_out_start) hact_out_r <= 1;
else if (!hact_w) hact_out_r <= 0;
if (rst) sof_r <= 0;
else sof_r <= re && sof_w;
if (irst) sof_r <= 0;
else sof_r <= re && sof_w;
if (rst) eof_r <= 0;
else eof_r <= re && eof_w;
if (irst) eof_r <= 0;
else eof_r <= re && eof_w;
end
......
sensor/sensor_i2c.v
View file @ b721ae66
......@@ -30,7 +30,7 @@ module sensor_i2c#(
parameter SENSI2C_STATUS = 'h1,
parameter SENSI2C_STATUS_REG = 'h30
)(
input rst,
input mrst, // @ posedge mclk
input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
......@@ -207,8 +207,9 @@ module sensor_i2c#(
.ADDR2 (SENSI2C_CTRL_ADDR),
.ADDR_MASK2 (SENSI2C_CTRL_MASK)
) cmd_deser_sens_i2c_i (
.rst (rst), // input
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (wa), // output[15:0]
......@@ -220,8 +221,9 @@ module sensor_i2c#(
.STATUS_REG_ADDR(SENSI2C_STATUS_REG),
.PAYLOAD_BITS(7) // STATUS_PAYLOAD_BITS)
) status_generate_sens_i2c_i (
.rst (rst), // input
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (set_status_w), // input
.wd (di[7:0]), // input[7:0]
.status ({busy, frame_num, sda_in, scl_in}), // input[25:0]
......
sensor/sensor_i2c_io.v
View file @ b721ae66
......@@ -34,10 +34,10 @@ module sensor_i2c_io#(
parameter SENSI2C_IOSTANDARD = "DEFAULT",
parameter SENSI2C_SLEW = "SLOW"
)(
input rst,
input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
input mrst, // @mclk
input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
output status_rq, // input request to send status downstream
input status_start,// Acknowledge of the first status packet byte (address)
......@@ -53,29 +53,29 @@ module sensor_i2c_io#(
wire sda_en;
sensor_i2c #(
.SENSI2C_ABS_ADDR(SENSI2C_ABS_ADDR),
.SENSI2C_REL_ADDR(SENSI2C_REL_ADDR),
.SENSI2C_ADDR_MASK(SENSI2C_ADDR_MASK),
.SENSI2C_CTRL_ADDR(SENSI2C_CTRL_ADDR),
.SENSI2C_CTRL_MASK(SENSI2C_CTRL_MASK),
.SENSI2C_CTRL(SENSI2C_CTRL),
.SENSI2C_STATUS(SENSI2C_STATUS),
.SENSI2C_STATUS_REG(SENSI2C_STATUS_REG)
.SENSI2C_ABS_ADDR (SENSI2C_ABS_ADDR),
.SENSI2C_REL_ADDR (SENSI2C_REL_ADDR),
.SENSI2C_ADDR_MASK (SENSI2C_ADDR_MASK),
.SENSI2C_CTRL_ADDR (SENSI2C_CTRL_ADDR),
.SENSI2C_CTRL_MASK (SENSI2C_CTRL_MASK),
.SENSI2C_CTRL (SENSI2C_CTRL),
.SENSI2C_STATUS (SENSI2C_STATUS),
.SENSI2C_STATUS_REG (SENSI2C_STATUS_REG)
) sensor_i2c_i (
.rst(rst), // input
.mclk(mclk), // input
.cmd_ad(cmd_ad), // input[7:0]
.cmd_stb(cmd_stb), // input
.status_ad(status_ad), // output[7:0]
.status_rq(status_rq), // output
.status_start(status_start), // input
.frame_sync(frame_sync), // input
.scl_in(scl_in), // input
.sda_in(sda_in), // input
.scl_out(scl_out), // output
.sda_out(sda_out), // output
.scl_en(scl_en), // output
.sda_en(sda_en) // output
.mrst (mrst), // input
.mclk (mclk), // input
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
.status_ad (status_ad), // output[7:0]
.status_rq (status_rq), // output
.status_start (status_start), // input
.frame_sync (frame_sync), // input
.scl_in (scl_in), // input
.sda_in (sda_in), // input
.scl_out (scl_out), // output
.sda_out (sda_out), // output
.scl_en (scl_en), // output
.sda_en (sda_en) // output
);
iobuf #(
......@@ -84,10 +84,10 @@ module sensor_i2c_io#(
.IOSTANDARD (SENSI2C_IOSTANDARD),
.SLEW (SENSI2C_SLEW)
) iobuf_scl_i (
.O (scl_in), // output
.IO (scl), // inout
.O (scl_in), // output
.IO (scl), // inout
.I (scl_out), // input
.T (!scl_en) // input
.T (!scl_en) // input
);
iobuf #(
......@@ -96,10 +96,10 @@ module sensor_i2c_io#(
.IOSTANDARD (SENSI2C_IOSTANDARD),
.SLEW (SENSI2C_SLEW)
) iobuf_sda_i (
.O (sda_in), // output
.IO (sda), // inout
.O (sda_in), // output
.IO (sda), // inout
.I (sda_out), // input
.T (!sda_en) // input
.T (!sda_en) // input
);
mpullup i_scl_pullup(scl);
mpullup i_sda_pullup(sda);
......
sensor/sensors393.v
View file @ b721ae66
......@@ -175,12 +175,15 @@ module sensors393 #(
parameter SENS_SS_MOD_PERIOD = 10000 // integer 4000-40000 - SS modulation period in ns
) (
input rst,
// input rst,
// will generate it here
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
input pclk2x, // global clock input, double pixel rate (192MHz for MT9P006)
input ref_clk, // IODELAY calibration
input dly_rst,
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
input pclk2x, // global clock input, double pixel rate (192MHz for MT9P006)
input mrst, // @posedge mclk, sync reset
input prst, // @posedge pclk, sync reset
input arst, // @posedge aclk, sync reset
// programming interface
input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
......@@ -381,31 +384,20 @@ module sensors393 #(
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD)
) sensor_channel_i (
.rst (rst), // input
.pclk (pclk), // input
.pclk2x (pclk2x), // input
/*
.sns_dp ((i & 2) ? ((i & 1) ? sns4_dp: sns3_dp): ((i & 1) ? sns2_dp: sns1_dp)), // inout[7:0]
.sns_dn ((i & 2) ? ((i & 1) ? sns4_dn: sns3_dn): ((i & 1) ? sns2_dn: sns1_dn)), // inout[7:0]
.sns_clkp ((i & 2) ? ((i & 1) ? sns4_clkp: sns3_clkp):((i & 1) ? sns2_clkp: sns1_clkp)), // inout
.sns_clkn ((i & 2) ? ((i & 1) ? sns4_clkn: sns3_clkn):((i & 1) ? sns2_clkn: sns1_clkn)), // inout
.sns_scl ((i & 2) ? ((i & 1) ? sns4_scl: sns3_scl): ((i & 1) ? sns2_scl: sns1_scl)), // inout
.sns_sda ((i & 2) ? ((i & 1) ? sns4_sda: sns3_sda): ((i & 1) ? sns2_sda: sns1_sda)), // inout
.sns_ctl ((i & 2) ? ((i & 1) ? sns4_ctl: sns3_ctl): ((i & 1) ? sns2_ctl: sns1_ctl)), // inout
// .sns_pg ((i & 2) ? ((i & 1) ? sns4_pg: sns3_pg): ((i & 1) ? sns2_pg: sns1_pg)), // inout
// .sns_pg ({sns4_pg,sns3_pg,sns2_pg,sns1_pg}[i]), // inout
.sns_pg (sns_pg[i]), // inout
*/
// .rst (rst), // input
.pclk (pclk), // input
.pclk2x (pclk2x), // input
.mrst (mrst), // input
.prst (prst), // input
.sns_dp (sns_dp[i * 8 +: 8]), // inout[7:0]
.sns_dn (sns_dn[i * 8 +: 8]), // inout[7:0]
.sns_clkp (sns_clkp[i]), // inout
.sns_clkn (sns_clkn[i]), // inout
.sns_scl (sns_scl[i]), // inout
.sns_sda (sns_sda[i]), // inout
.sns_ctl (sns_ctl[i]), // inout
.sns_pg (sns_pg[i]), // inout
.sns_dp (sns_dp[i * 8 +: 8]), // inout[7:0]
.sns_dn (sns_dn[i * 8 +: 8]), // inout[7:0]
.sns_clkp (sns_clkp[i]), // inout
.sns_clkn (sns_clkn[i]), // inout
.sns_scl (sns_scl[i]), // inout
.sns_sda (sns_sda[i]), // inout
.sns_ctl (sns_ctl[i]), // inout
.sns_pg (sns_pg[i]), // inout
.mclk (mclk), // input
.cmd_ad_in (cmd_ad), // input[7:0]
......@@ -459,9 +451,11 @@ module sensors393 #(
.HIST_SAXI_MODE_ADDR_MASK (HIST_SAXI_MODE_ADDR_MASK),
.NUM_FRAME_BITS (NUM_FRAME_BITS)
) histogram_saxi_i (
.rst (rst), // input
// .rst (rst), // input
.mclk (mclk), // input
.aclk (aclk), // input
.mrst (mrst), // input
.arst (arst), // input
.frame0 (frame_num0), // input[3:0]
.hist_request0 (hist_request[0]), // input
.hist_grant0 (hist_grant[0]), // output
......@@ -512,8 +506,9 @@ module sensors393 #(
);
status_router4 status_router4_i (
.rst (rst), // input
.rst (1'b0), // input
.clk (mclk), // input
.srst (mrst), // input
.db_in0 (status_ad_chn[0 +: 8]), // input[7:0]
.rq_in0 (status_rq_chn[0]), // input
.start_in0 (status_start_chn[0]), // output
......
status_read.v
View file @ b721ae66
......@@ -34,13 +34,11 @@ module status_read#(
parameter AXI_RD_ADDR_BITS = 14,
parameter integer STATUS_DEPTH= 8 // 256 cells, maybe just 16..64 are enough?
)(
input rst,
input clk,
input mrst, // @posedge mclk - sync reset
input arst, // @posedge axi_clk - sync reset
input clk,
input axi_clk, // common for read and write channels
input [AXI_RD_ADDR_BITS-1:0] axird_pre_araddr, // status read address, 1 cycle ahead of read data
// input pre_stb, // read data request, with axi_pre_addr
// output reg [31:0] axi_status_rdata, // read data, 1 cycle latency from the address/stb
// output reg data_valid, // read data valid, 1 cycle latency from pre_stb, decoded address
input axird_start_burst, // start of read burst, valid pre_araddr, save externally to control ext. dev_ready multiplexer
input [STATUS_DEPTH-1:0] axird_raddr, // .raddr(read_in_progress?read_address[9:0]:10'h3ff), // read address
input axird_ren, // .ren(bram_reg_re_w) , // read port enable
......@@ -55,9 +53,7 @@ module status_read#(
localparam integer DATA_2DEPTH=(1<<STATUS_DEPTH)-1;
reg [31:0] ram [0:DATA_2DEPTH];
reg [STATUS_DEPTH-1:0] waddr;
// wire [STATUS_DEPTH-1:0] raddr;
reg we;
// wire re;
reg [31: 0] wdata;
reg rq_r;
reg [3:0] dstb;
......@@ -71,13 +67,6 @@ module status_read#(
reg [31:0] axi_status_rdata;
reg [31:0] axi_status_rdata_r;
// registering to match BRAM timing (so it is possible to instantioate it instead)
// reg [STATUS_DEPTH-1:0] raddr_r; // .raddr(read_in_progress?read_address[9:0]:10'h3ff), // read address
// reg rd_r; // .ren(bram_reg_re_w) , // read port enable
// reg regen_r; //==axird_ren?? - remove? .regen(bram_reg_re_w), // output register enable
assign select_w = ((axird_pre_araddr ^ STATUS_ADDR) & STATUS_ADDR_MASK)==0;
assign rd = axird_ren && select_r;
assign regen = axird_regen && select_d;
......@@ -90,60 +79,52 @@ module status_read#(
assign start=rq && !rq_r;
assign axird_rdata=axi_status_rdata_r;
assign axird_selected = select_r;
always @ (posedge rst or posedge axi_clk) begin
if (rst) select_r <= 0;
always @ (posedge axi_clk) begin
if (arst) select_r <= 0;
else if (axird_start_burst) select_r <= select_w;
end
always @ (posedge axi_clk) begin
// if (rd_r) axi_status_rdata <= ram[raddr_r];
// if (regen_r) axi_status_rdata_r <= axi_status_rdata;
if (rd) axi_status_rdata <= ram[axird_raddr];
if (regen) axi_status_rdata_r <= axi_status_rdata;
select_d <= select_r;
// raddr_r <= axird_raddr;
// rd_r <= rd;
// regen_r <= regen;
end
always @ (posedge rst or posedge clk) begin
// if (rst) data_valid <= 0;
// else data_valid <= re;
always @ (posedge clk) begin
if (rst) rq_r <= 0;
else rq_r <= rq;
if (mrst) rq_r <= 0;
else rq_r <= rq;
if (rst) dstb <= 0;
if (mrst) dstb <= 0;
else if (!rq) dstb <= 0;
else dstb <= {dstb[2:0],~rq_r};
// byte 0 - address
if (rst) waddr <= 0;
if (mrst) waddr <= 0;
else if (start) waddr <= ad[STATUS_DEPTH-1:0];
// byte 1 - 2 payload bits and sequence number
// 6 bits of the sequence number will go to bits 26.. 31
// 2 bits (24,25) are payload status
if (rst) wdata[31:24] <= 0;
if (mrst) wdata[31:24] <= 0;
else if (start) wdata[31:24] <= 0;
else if (dstb[0]) wdata[31:24] <= ad;
// byte 2 - payload bits 0..7
if (rst) wdata[ 7: 0] <= 0;
if (mrst) wdata[ 7: 0] <= 0;
else if (start) wdata[ 7: 0] <= 0;
else if (dstb[1]) wdata[ 7: 0] <= ad;
// byte 3 - payload bits 8..15
if (rst) wdata[15: 8] <= 0;
if (mrst) wdata[15: 8] <= 0;
else if (start) wdata[15: 8] <= 0;
else if (dstb[2]) wdata[15: 8] <= ad;
// byte 4 - payload bits 16..23
if (rst) wdata[23:16] <= 0;
if (mrst) wdata[23:16] <= 0;
else if (start) wdata[23:16] <= 0;
else if (dstb[3]) wdata[23:16] <= ad;
if (rst) we <= 0;
if (mrst) we <= 0;
else we <= !rq && rq_r;
end
......
timing/camsync393.v
View file @ b721ae66
......@@ -52,8 +52,9 @@ module camsync393 #(
parameter CAMSYNC_POST_MAGIC = 6'b001101
)(
input rst, // global reset
// input rst, // global reset
input mclk, // @posedge (was negedge) AF2015: check external inversion - make it @posedge mclk
input mrst, // @ posedge mclk - sync reset
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
// 0 - mode: [1:0] +2 - reset ts_snd_en, +3 - set ts_snd_en - enable sending timestamp over sync line
......@@ -75,7 +76,7 @@ module camsync393 #(
// 4..7 - input trigger delay (in pclk periods)
input pclk, // pixel clock (global) - switch it to 100MHz (mclk/2)?
input prst, // @ posedge pclk - sync reset
input [9:0] gpio_in, // 12-bit input from GPIO pins -> 10 bit
output [9:0] gpio_out,// 12-bit output to GPIO pins
output reg [9:0] gpio_out_en,// 12-bit output enable to GPIO pins
......@@ -445,8 +446,8 @@ module camsync393 #(
end
always @ (posedge rst or posedge pclk) begin
if (rst) dly_cntr_run <= 0;
always @ (posedge pclk) begin
if (prst) dly_cntr_run <= 0;
else if (!triggered_mode_pclk) dly_cntr_run <= 0;
else if (start_dly) dly_cntr_run <= 4'hf;
else dly_cntr_run <= dly_cntr_run &
......@@ -585,8 +586,9 @@ module camsync393 #(
.ADDR_WIDTH (3),
.DATA_WIDTH (32)
) cmd_deser_32bit_i (
.rst (rst), // input
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[3:0]
......@@ -663,24 +665,24 @@ module camsync393 #(
);
assign {ts_rcv_stb_chn3, ts_rcv_stb_chn2, ts_rcv_stb_chn1, ts_rcv_stb_chn0}= ts_stb;
pulse_cross_clock i_start_to_pclk (.rst(1'b0), .src_clk(mclk), .dst_clk(pclk), .in_pulse(start_d && start_en), .out_pulse(start_to_pclk),.busy());
pulse_cross_clock i_start_to_pclk (.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(start_d && start_en), .out_pulse(start_to_pclk),.busy());
pulse_cross_clock i_ts_snap_mclk0 (.rst(1'b0), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_snap_triggered[0]), .out_pulse(ts_snap_triggered_mclk[0]),.busy());
pulse_cross_clock i_ts_snap_mclk1 (.rst(1'b0), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_snap_triggered[1]), .out_pulse(ts_snap_triggered_mclk[1]),.busy());
pulse_cross_clock i_ts_snap_mclk2 (.rst(1'b0), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_snap_triggered[2]), .out_pulse(ts_snap_triggered_mclk[2]),.busy());
pulse_cross_clock i_ts_snap_mclk3 (.rst(1'b0), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_snap_triggered[3]), .out_pulse(ts_snap_triggered_mclk[3]),.busy());
pulse_cross_clock i_ts_snap_mclk0 (.rst(prst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_snap_triggered[0]), .out_pulse(ts_snap_triggered_mclk[0]),.busy());
pulse_cross_clock i_ts_snap_mclk1 (.rst(prst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_snap_triggered[1]), .out_pulse(ts_snap_triggered_mclk[1]),.busy());
pulse_cross_clock i_ts_snap_mclk2 (.rst(prst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_snap_triggered[2]), .out_pulse(ts_snap_triggered_mclk[2]),.busy());
pulse_cross_clock i_ts_snap_mclk3 (.rst(prst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_snap_triggered[3]), .out_pulse(ts_snap_triggered_mclk[3]),.busy());
pulse_cross_clock i_rcv_done_mclk (.rst(1'b0), .src_clk(pclk), .dst_clk(mclk), .in_pulse(rcv_done), .out_pulse(rcv_done_mclk),.busy());
pulse_cross_clock i_rcv_done_mclk (.rst(prst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(rcv_done), .out_pulse(rcv_done_mclk),.busy());
pulse_cross_clock i_local_got_pclk0(.rst(1'b0), .src_clk(mclk), .dst_clk(pclk), .in_pulse(local_got[0]), .out_pulse(local_got_pclk[0]),.busy());
pulse_cross_clock i_local_got_pclk1(.rst(1'b0), .src_clk(mclk), .dst_clk(pclk), .in_pulse(local_got[1]), .out_pulse(local_got_pclk[1]),.busy());
pulse_cross_clock i_local_got_pclk2(.rst(1'b0), .src_clk(mclk), .dst_clk(pclk), .in_pulse(local_got[2]), .out_pulse(local_got_pclk[2]),.busy());
pulse_cross_clock i_local_got_pclk3(.rst(1'b0), .src_clk(mclk), .dst_clk(pclk), .in_pulse(local_got[3]), .out_pulse(local_got_pclk[3]),.busy());
pulse_cross_clock i_local_got_pclk0(.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(local_got[0]), .out_pulse(local_got_pclk[0]),.busy());
pulse_cross_clock i_local_got_pclk1(.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(local_got[1]), .out_pulse(local_got_pclk[1]),.busy());
pulse_cross_clock i_local_got_pclk2(.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(local_got[2]), .out_pulse(local_got_pclk[2]),.busy());
pulse_cross_clock i_local_got_pclk3(.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(local_got[3]), .out_pulse(local_got_pclk[3]),.busy());
pulse_cross_clock i_trig_r_mclk0 (.rst(1'b0), .src_clk(pclk), .dst_clk(mclk), .in_pulse(trig_r[0]), .out_pulse(trig_r_mclk[0]),.busy());
pulse_cross_clock i_trig_r_mclk1 (.rst(1'b0), .src_clk(pclk), .dst_clk(mclk), .in_pulse(trig_r[1]), .out_pulse(trig_r_mclk[1]),.busy());
pulse_cross_clock i_trig_r_mclk2 (.rst(1'b0), .src_clk(pclk), .dst_clk(mclk), .in_pulse(trig_r[2]), .out_pulse(trig_r_mclk[2]),.busy());
pulse_cross_clock i_trig_r_mclk3 (.rst(1'b0), .src_clk(pclk), .dst_clk(mclk), .in_pulse(trig_r[3]), .out_pulse(trig_r_mclk[3]),.busy());
pulse_cross_clock i_trig_r_mclk0 (.rst(prst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(trig_r[0]), .out_pulse(trig_r_mclk[0]),.busy());
pulse_cross_clock i_trig_r_mclk1 (.rst(prst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(trig_r[1]), .out_pulse(trig_r_mclk[1]),.busy());
pulse_cross_clock i_trig_r_mclk2 (.rst(prst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(trig_r[2]), .out_pulse(trig_r_mclk[2]),.busy());
pulse_cross_clock i_trig_r_mclk3 (.rst(prst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(trig_r[3]), .out_pulse(trig_r_mclk[3]),.busy());
endmodule
timing/rtc393.v
View file @ b721ae66
......@@ -36,8 +36,10 @@ module rtc393 #(
parameter RTC_SET_STATUS = 3 // set status mode, and take a time snapshot (wait response and read time)
) (
input rst,
// input rst,
input mclk,
input mrst, // @ posedge mclk - sync reset
input refclk, // not a global clock, reference frequency < mclk/2
// programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
......@@ -96,8 +98,8 @@ module rtc393 #(
assign live_sec = sec;
assign live_usec = usec;
always @ (posedge rst or posedge mclk) begin
if (rst) pio_alt_snap <= 0;
always @ (posedge mclk) begin
if (mrst) pio_alt_snap <= 0;
else if (set_status_w) pio_alt_snap <= ~pio_alt_snap;
end
......@@ -112,8 +114,8 @@ module rtc393 #(
if (set_corr_w) corr <= cmd_data[15:0];
end
always @ (posedge rst or posedge mclk) begin
if (rst) enable_rtc <= 0;
always @ (posedge mclk) begin
if (mrst) enable_rtc <= 0;
else if (set_sec_w) enable_rtc <= 1;
end
......@@ -161,8 +163,9 @@ module rtc393 #(
.ADDR_WIDTH (3),
.DATA_WIDTH (32)
) cmd_deser_32bit_i (
.rst (rst), // input
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[3:0]
......@@ -177,14 +180,15 @@ module rtc393 #(
.EXTRA_WORDS (2),
.EXTRA_REG_ADDR (RTC_SEC_USEC_ADDR)
) status_generate_i (
.rst (rst), // input
.clk (mclk), // input
.we (set_status_w), // input
.wd (cmd_data[7:0]), // input[7:0]
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (set_status_w), // input
.wd (cmd_data[7:0]), // input[7:0]
.status ({12'b0,pio_usec,pio_sec,pio_alt_snap}), // input[14:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
);
......
timing/timestamp_fifo.v
View file @ b721ae66
......@@ -25,15 +25,20 @@
`timescale 1ns/1ps
module timestamp_fifo(
input rst,
// input rst,
input sclk,
input srst, // @ posedge smclk - sync reset
input pre_stb, // marks pre-first input byte (s0,s1,s2,s3,u0,u1,u2,u3)
input [7:0] din, // data in - valid for 8 cycles after pre_stb
input aclk, // clock to synchronize "advance" commands
input arst, // @ posedge aclk - sync reset
input advance, // @aclk advance registers
input rclk, // output clock
input rrst, // @ posedge rclk - sync reset
input rstb, // @rclk, read start (data available next 8 cycles)
output reg [ 7:0] dout
);
......@@ -43,12 +48,12 @@ module timestamp_fifo(
reg [3:0] rpntr; // fifo read pointer
reg [1:0] advance_r;
reg snd; // receive data
always @ (posedge rst or posedge sclk) begin
if (rst) rcv <= 0;
always @ (posedge sclk) begin
if (srst) rcv <= 0;
else if (pre_stb) rcv <= 1;
else if (&wpntr[2:0]) rcv <= 0;
if (rst) wpntr <= 0;
if (srst) wpntr <= 0;
else if (!rcv) wpntr <= {wpntr[3],3'b0};
else wpntr <= wpntr + 1;
end
......@@ -57,21 +62,21 @@ module timestamp_fifo(
if (rcv) fifo_ram[wpntr] <= din;
end
always @(posedge rst or posedge aclk) begin
if (rst) advance_r <= 0;
else advance_r <= {advance_r[0], advance};
always @(posedge aclk) begin
if (arst) advance_r <= 0;
else advance_r <= {advance_r[0], advance};
end
always @(posedge aclk) begin
if (advance_r[0] && !advance_r[1]) rpntr[3] <= wpntr[3];
end
always @(posedge rst or posedge rclk) begin
if (rst) snd <= 0;
always @(posedge rclk) begin
if (rrst) snd <= 0;
else if (rstb) snd <= 1;
else if (&rpntr[2:1]) snd <= 0; // at count 6
if (rst) rpntr[2:0] <= 0;
if (rrst) rpntr[2:0] <= 0;
else if (!snd && !rstb) rpntr[2:0] <= 0;
else rpntr[2:0] <= rpntr[2:0] + 1;
end
......
timing/timestamp_snapshot.v
View file @ b721ae66
......@@ -21,12 +21,13 @@
`timescale 1ns/1ps
module timestamp_snapshot(
input rst,
// input rst,
input tclk, // clock that drives time counters
input [31:0] sec, // @tclk: current time seconds
input [19:0] usec, // @tclk: current time microseconds
// snapshot destination clock domain
input sclk,
input srst, // @ posedge sclk - sync reset
input snap,
output pre_stb, // one clock pulse before sending TS data
output reg [7:0] ts_data // timestamp data (s0,s1,s2,s3,u0,u1,u2,u3==0)
......@@ -44,8 +45,8 @@ module timestamp_snapshot(
if (snap_tclk) sec_usec_snap <= {usec,sec};
end
always @(posedge rst or posedge sclk) begin
if (rst) snd <= 0;
always @(posedge sclk) begin
if (srst) snd <= 0;
else if (!pulse_busy && pulse_busy_r) snd <= 1;
else if ((&cntr) || snap) snd <= 0;
end
......@@ -72,7 +73,7 @@ module timestamp_snapshot(
pulse_cross_clock #(
.EXTRA_DLY (1)
) snap_tclk_i (
.rst (rst), // input
.rst (srst), // input
.src_clk (sclk), // input
.dst_clk (tclk), // input
.in_pulse (snap), // input
......
timing/timing393.v
View file @ b721ae66
......@@ -50,9 +50,11 @@ module timing393 #(
parameter RTC_SET_CORR= 2, // write correction 16-bit signed
parameter RTC_SET_STATUS= 3 // generate an output pulse to take a snapshot
)(
input rst, // global reset
// input rst, // global reset
input mclk, // system clock
input pclk, // was pixel clock in x353 clock (global) - switch it to 100MHz (mclk/2)?
input mrst, // @ posedge mclk - sync reset
input prst, // @ posedge pclk - sync reset
input refclk, // not a global clock, reference frequency < mclk/2
......@@ -99,6 +101,7 @@ module timing393 #(
// timestamp for the event logger
input lclk, // clock used by the event logger
input lrst, // @ posedge lclk - sync reset
input ts_logger_snap, // request from the logger to take a snapshot
output ts_logger_stb, // one clock pulse before sending TS data
output [7:0] ts_logger_data // timestamp data (s0,s1,s2,s3,u0,u1,u2,u3==0)
......@@ -135,8 +138,9 @@ module timing393 #(
.RTC_SET_CORR (RTC_SET_CORR),
.RTC_SET_STATUS (RTC_SET_STATUS)
) rtc393_i (
.rst (rst), // input
// .rst (rst), // input
.mclk (mclk), // input
.mrst (mrst), // input
.refclk (refclk), // input
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
......@@ -149,55 +153,60 @@ module timing393 #(
timestamp_snapshot timestamp_snapshot_logger_i (
.rst (rst), // input
// .rst (rst), // input
.tclk (mclk), // input
.sec (live_sec), // input[31:0]
.usec (live_usec), // input[19:0]
.sclk (lclk), // input
.srst (lrst), // input
.snap (ts_logger_snap), // input
.pre_stb (ts_logger_stb), // output
.ts_data (ts_logger_data) // output[7:0] reg
);
timestamp_snapshot timestamp_snapshot_chn0_i (
.rst (rst), // input
// .rst (rst), // input
.tclk (mclk), // input
.sec (live_sec), // input[31:0]
.usec (live_usec), // input[19:0]
.sclk (mclk), // input
.srst (mrst), // input
.snap (ts_local_snap[0]), // input
.pre_stb (ts_local_stb[0]), // output
.ts_data (ts_local_data[0 * 8 +: 8]) // output[7:0] reg
);
timestamp_snapshot timestamp_snapshot_chn1_i (
.rst (rst), // input
// .rst (rst), // input
.tclk (mclk), // input
.sec (live_sec), // input[31:0]
.usec (live_usec), // input[19:0]
.sclk (mclk), // input
.srst (mrst), // input
.snap (ts_local_snap[1]), // input
.pre_stb (ts_local_stb[1]), // output
.ts_data (ts_local_data[1 * 8 +: 8]) // output[7:0] reg
);
timestamp_snapshot timestamp_snapshot_chn2_i (
.rst (rst), // input
// .rst (rst), // input
.tclk (mclk), // input
.sec (live_sec), // input[31:0]
.usec (live_usec), // input[19:0]
.sclk (mclk), // input
.srst (mrst), // input
.snap (ts_local_snap[2]), // input
.pre_stb (ts_local_stb[2]), // output
.ts_data (ts_local_data[2 * 8 +: 8]) // output[7:0] reg
);
timestamp_snapshot timestamp_snapshot_chn3_i (
.rst (rst), // input
// .rst (rst), // input
.tclk (mclk), // input
.sec (live_sec), // input[31:0]
.usec (live_usec), // input[19:0]
.sclk (mclk), // input
.srst (mrst), // input
.snap (ts_local_snap[3]), // input
.pre_stb (ts_local_stb[3]), // output
.ts_data (ts_local_data[3 * 8 +: 8]) // output[7:0] reg
......@@ -222,11 +231,14 @@ module timing393 #(
.CAMSYNC_PRE_MAGIC (CAMSYNC_PRE_MAGIC),
.CAMSYNC_POST_MAGIC (CAMSYNC_POST_MAGIC)
) camsync393_i (
.rst (rst), // input
// .rst (rst), // input
.mclk (mclk), // input
.mrst (mrst), // input
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
.pclk (pclk), // input
.prst (prst), // input
.gpio_in (gpio_in), // input[9:0]
.gpio_out (gpio_out), // output[9:0]
.gpio_out_en (gpio_out_en), // output[9:0] reg
......
util_modules/clocks393.v
View file @ b721ae66
......@@ -80,8 +80,9 @@ module clocks393#(
parameter FFCLK1_IOSTANDARD = "DEFAULT"
)(
input rst,
// input rst,
input mclk, // global clock, comes from the memory controller (uses aclk generated here)
input mrst,
// command/status interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
......@@ -121,11 +122,11 @@ module clocks393#(
wire memclk_rst = reset_clk[4];
wire ffclk0_rst = reset_clk[5];
wire ffclk1_rst = reset_clk[6];
always @ (posedge mclk or posedge rst) begin
if (rst) reset_clk <= 0;
always @ (posedge mclk) begin
if (mrst) reset_clk <= 0;
else if (set_ctrl_w) reset_clk <= {cmd_data[10:8], cmd_data[3:0]};
if (rst) pwrdwn_clk <= 0;
if (mrst) pwrdwn_clk <= 0;
else if (set_ctrl_w) pwrdwn_clk <= cmd_data[7:4];
end
assign status_data = {test_clk, locked, extra_status};
......@@ -140,8 +141,9 @@ module clocks393#(
.ADDR_WIDTH (1),
.DATA_WIDTH (11)
) cmd_deser_32bit_i (
.rst (rst), // input
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[3:0]
......@@ -154,14 +156,15 @@ module clocks393#(
.PAYLOAD_BITS (9),
.REGISTER_STATUS (0)
) status_generate_i (
.rst (rst), // input
.clk (mclk), // input
.we (set_status_w), // input
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (set_status_w), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_data), // input[14:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
.status (status_data), // input[14:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
);
BUFG bufg_axi_aclk_i (.O(aclk), .I(fclk[0]));
......
util_modules/cmd_deser.v
View file @ b721ae66
......@@ -34,6 +34,7 @@ module cmd_deser#(
)(
input rst,
input clk,
input srst, // sync reset
input [7:0] ad,
input stb,
output [ADDR_WIDTH-1:0] addr,
......@@ -57,6 +58,7 @@ module cmd_deser#(
) i_cmd_deser_single (
.rst(rst),
.clk(clk),
.srst(srst),
.ad(ad),
.stb(stb),
.addr(addr),
......@@ -78,6 +80,7 @@ module cmd_deser#(
) i_cmd_deser_dual (
.rst(rst),
.clk(clk),
.srst(srst),
.ad(ad),
.stb(stb),
.addr(addr),
......@@ -100,6 +103,7 @@ module cmd_deser#(
) i_cmd_deser_multi (
.rst(rst),
.clk(clk),
.srst(srst),
.ad(ad),
.stb(stb),
.addr(addr),
......@@ -126,6 +130,7 @@ module cmd_deser_single#(
)(
input rst,
input clk,
input srst, // sync reset
input [7:0] ad,
input stb,
output [ADDR_WIDTH-1:0] addr,
......@@ -148,9 +153,11 @@ module cmd_deser_single#(
((ad ^ ADDR_LOW1) & (8'hff & ADDR_MASK_LOW1)) == 0,
((ad ^ ADDR_LOW ) & (8'hff & ADDR_MASK_LOW )) == 0};
always @ (posedge rst or posedge clk) begin
if (rst) we_r <= 0;
else we_r <= match_low & {3{stb}};
if (rst) deser_r <= 0;
if (rst) we_r <= 0;
else if (srst) we_r <= 0;
else we_r <= match_low & {3{stb}};
if (rst) deser_r <= 0;
else if (srst) deser_r <= 0;
else if ((|match_low) && stb) deser_r <= ad;
end
assign data={DATA_WIDTH{1'b0}};
......@@ -172,6 +179,7 @@ module cmd_deser_dual#(
)(
input rst,
input clk,
input srst, // sync reset
input [7:0] ad,
input stb,
output [ADDR_WIDTH-1:0] addr,
......@@ -215,14 +223,16 @@ module cmd_deser_dual#(
((ad ^ ADDR_HIGH ) & (8'hff & ADDR_MASK_HIGH )) == 0};
always @ (posedge rst or posedge clk) begin
if (rst) stb_d <= 3'b0;
// else stb_d <= match_low && stb;
else stb_d <= stb?match_low:3'b0;
if (rst) stb_d <= 3'b0;
else if (srst) stb_d <= 3'b0;
else stb_d <= stb?match_low:3'b0;
if (rst) we_r <= 3'b0;
else we_r <= match_high & stb_d;
if (rst) we_r <= 3'b0;
else if (srst) we_r <= 3'b0;
else we_r <= match_high & stb_d;
if (rst) deser_r[15:0] <= 0;
else if (srst) deser_r[15:0] <= 0;
else if ((match_low && stb) || (match_high && stb_d)) deser_r[15:0] <= {ad,deser_r[15:8]};
end
assign data=0; // {DATA_WIDTH{1'b0}};
......@@ -245,6 +255,7 @@ module cmd_deser_multi#(
)(
input rst,
input clk,
input srst, // sync reset
input [7:0] ad,
input stb,
output [ADDR_WIDTH-1:0] addr,
......@@ -287,22 +298,27 @@ module cmd_deser_multi#(
((ad ^ ADDR_HIGH1) & (8'hff & ADDR_MASK_HIGH1)) == 0,
((ad ^ ADDR_HIGH ) & (8'hff & ADDR_MASK_HIGH )) == 0};
always @ (posedge rst or posedge clk) begin
if (rst) stb_d <= 0;
else stb_d <= stb?match_low:3'b0;
if (rst) stb_d <= 0;
else if (srst) stb_d <= 0;
else stb_d <= stb?match_low:3'b0;
if (rst) sr <= 0;
else if (srst) sr <= 0;
else if (match_high[0] && stb_d[0]) sr <= 1 << (NUM_CYCLES-2);
else sr <= {1'b0,sr[NUM_CYCLES-2:1]};
if (rst) sr1<= 0;
if (rst) sr1 <= 0;
else if (srst) sr1 <= 0;
else if (match_high[1] && stb_d[1]) sr1 <= 1 << (NUM_CYCLES-2);
else sr1 <= {1'b0,sr1[NUM_CYCLES-2:1]};
if (rst) sr2 <= 0;
else if (srst) sr2 <= 0;
else if (match_high[2] && stb_d[2]) sr2 <= 1 << (NUM_CYCLES-2);
else sr2 <= {1'b0,sr2[NUM_CYCLES-2:1]};
if (rst) deser_r[8*NUM_CYCLES-1:0] <= 0;
else if (srst) deser_r[8*NUM_CYCLES-1:0] <= 0;
else if ((match_low && (|stb)) ||
(match_high && (|stb_d)) ||
(|sr) || (|sr1) || (|sr2)) deser_r[8*NUM_CYCLES-1:0] <= {ad,deser_r[8*NUM_CYCLES-1:8]};
......
util_modules/cmd_frame_sequencer.v
View file @ b721ae66
......@@ -59,7 +59,7 @@ module cmd_frame_sequencer#(
parameter CMDFRAMESEQ_RUN_BIT = 13
)(
input rst,
input mrst,
input mclk, // for command/status
// programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
......@@ -145,22 +145,22 @@ module cmd_frame_sequencer#(
assign commands_pending = rpointer != fifo_wr_pointers_outr_r; // only look at the current page different pages will trigger page increment first
assign pre_cmd_seq_w = commands_pending & ~(|page_r_inc) & seq_enrun;
assign valid = valid_r;
always @ (posedge rst or posedge mclk) begin
if (rst) por <= 0;
else por <= {por[1:0], 1'b1};
always @ (posedge mclk) begin
if (mrst) por <= 0;
else por <= {por[1:0], 1'b1};
if (rst) seq_enrun <= 0;
if (mrst) seq_enrun <= 0;
else if (reset_cmd) seq_enrun <= 0;
else if (run_cmd) seq_enrun <= cmd_data[CMDFRAMESEQ_RUN_BIT-1];
if (rst) initialized <= 0;
if (mrst) initialized <= 0;
else if (reset_seq_done) initialized <= 1;
if (rst) d_na <= 0;
if (mrst) d_na <= 0;
else if (cmd_we_ctl_w) d_na <= 0;
else if (cmd_we) d_na <= ~ d_na;
if (rst) valid_r <= 0;
if (mrst) valid_r <= 0;
else if (ren[1]) valid_r <= 1;
else if (ackn) valid_r <= 0;
......@@ -242,8 +242,9 @@ module cmd_frame_sequencer#(
.DATA_WIDTH (32),
.WE_EARLY (3) // generate cmd_we and cmd_a three cycles before cmd_data is valid
) cmd_deser_32bit_i (
.rst (rst), // input
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[3:0]
......
util_modules/cmd_seq_mux.v
View file @ b721ae66
......@@ -27,7 +27,7 @@ module cmd_seq_mux#(
parameter CMDSEQMUX_STATUS = 'h38,
parameter AXI_WR_ADDR_BITS=14
)(
input rst, // global system reset
input mrst, // global system reset
input mclk, // global system clock
// programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
......@@ -90,12 +90,12 @@ module cmd_seq_mux#(
assign {ackn3, ackn2, ackn1, ackn0} = ackn_r;
assign ackn_w = rq_any && (!full_r || ackn_out);
always @(posedge rst or posedge mclk) begin
if (rst) full_r <= 0;
always @(posedge mclk) begin
if (mrst) full_r <= 0;
else if (rq_any) full_r <= 1;
else if (ackn_out) full_r <= 0;
if (rst) ackn_r <=0;
if (mrst) ackn_r <=0;
else ackn_r <= {4{ackn_w}} & { pri_enc_w[1] & pri_enc_w[0],
pri_enc_w[1] & ~pri_enc_w[0],
~pri_enc_w[1] & pri_enc_w[0],
......@@ -139,13 +139,14 @@ module cmd_seq_mux#(
.DATA_WIDTH (8) //,32)
) cmd_deser_32bit_i (
.rst (rst), // input
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (), // output[0:0]
.addr (), // output[0:0]
.data (cmd_data), // output[31:0]
.we (cmd_status) // output
.we (cmd_status) // output
);
status_generate #(
......@@ -153,14 +154,15 @@ module cmd_seq_mux#(
.PAYLOAD_BITS (18),
.REGISTER_STATUS (1)
) status_generate_cmd_seq_mux_i (
.rst (rst), // input
.clk (mclk), // input
.we (cmd_status), // input
.wd (cmd_data[7:0]), // input[7:0]
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (cmd_status), // input
.wd (cmd_data[7:0]), // input[7:0]
.status ({frame_num3, frame_num2, frame_num1, frame_num0, 2'b0}), // input[18:0] // 2 LSBs - may add "real" status
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
);
......
util_modules/fifo_1cycle.v
View file @ b721ae66
......@@ -30,6 +30,7 @@ module fifo_1cycle
(
input rst, // reset, active high
input clk, // clock - positive edge
input srst, // sync reset
input we, // write enable
input re, // read enable
input [DATA_WIDTH-1:0] data_in, // input data
......@@ -59,23 +60,32 @@ module fifo_1cycle
assign next_fill = fill[DATA_DEPTH-1:0]+((we && ~re)?1:((~we && re)?-1:0));
always @ (posedge clk or posedge rst) begin
if (rst) fill <= 0;
else fill <= next_fill;
if (rst) wa <= 0;
else if (we) wa <= wa+1;
if (rst) ra <= 0;
else if (re) ra <= ra+1;
if (rst) fill <= 0;
else if (srst) fill <= 0;
else fill <= next_fill;
if (rst) wa <= 0;
else if (srst) wa <= 0;
else if (we) wa <= wa+1;
if (rst) ra <= 0;
else if (srst) ra <= 0;
else if (re) ra <= ra+1;
else if (fill==0) ra <= wa; // Just recover from bit errors
if (rst) nempty <= 0;
else nempty <= (next_fill!=0);
if (rst) nempty <= 0;
else if (srst) nempty <= 0;
else nempty <= (next_fill!=0);
`ifdef DEBUG_FIFO
if (rst) wcount <= 0;
else if (we) wcount <= wcount + 1;
if (rst) wcount <= 0;
else if (srst) wcount <= 0;
else if (we) wcount <= wcount + 1;
if (rst) rcount <= 0;
else if (re) rcount <= rcount + 1;
if (rst) rcount <= 0;
else if (srst) rcount <= 0;
else if (re) rcount <= rcount + 1;
`endif
end
......
util_modules/fifo_2regs.v
View file @ b721ae66
......@@ -24,7 +24,7 @@
module fifo_2regs #(
parameter WIDTH =16)
(
input rst,
input mrst,
input clk,
input [WIDTH-1:0] din,
input wr,
......@@ -38,12 +38,12 @@ module fifo_2regs #(
reg [WIDTH-1:0] reg_in;
assign dout=reg_out;
always @ (posedge rst or posedge clk) begin
if (rst) full_out <=0;
always @ (posedge clk) begin
if (mrst) full_out <=0;
else if (srst) full_out <=0;
else if (wr || rd) full_out <= !(!wr && rd && !full_in);
if (rst) full_in <=0;
if (mrst) full_in <=0;
else if (srst) full_in <=0;
else if (wr ^rd) full_in <= wr && (full_out || full_in);
end
......
util_modules/fifo_cross_clocks.v
View file @ b721ae66
......@@ -25,7 +25,9 @@ module fifo_cross_clocks
parameter integer DATA_WIDTH=16,
parameter integer DATA_DEPTH=4 // >=3
) (
input rst, // reset, active high
input rst, // async reset, active high (global)
input rrst, // @ posedge rclk - sync reset
input wrst, // @ posedge wclk - sync reset
input rclk, // read clock - positive edge
input wclk, // write clock - positive edge
input we, // write enable
......@@ -69,29 +71,32 @@ module fifo_cross_clocks
assign nempty= (waddr_gray_rclk[3:0] ^ raddr_gray[3:0]) != 4'b0;
assign data_out=ram[raddr];
always @ (posedge wclk or posedge rst) begin
if (rst) waddr <= 0;
else if (we) waddr <= waddr_plus1;
if (rst) waddr_gray <= 0;
// else if (we) waddr_gray <= waddr_plus1_gray;
else if (we) waddr_gray [3:0] <= waddr_plus1_gray[3:0];
if (rst) waddr <= 0;
else if (wrst) waddr <= 0;
else if (we) waddr <= waddr_plus1;
if (rst) waddr_gray <= 0;
else if (wrst) waddr_gray <= 0;
else if (we) waddr_gray [3:0] <= waddr_plus1_gray[3:0];
end
always @ (posedge rclk or posedge rst) begin
if (rst) raddr <= 0;
else if (re) raddr <= raddr_plus1;
if (rst) raddr_gray_top3 <= 0;
else if (re) raddr_gray_top3 <= raddr_plus1_gray_top3;
if (rst) raddr <= 0;
else if (rrst) raddr <= 0;
else if (re) raddr <= raddr_plus1;
if (rst) raddr_gray_top3 <= 0;
else if (rrst) raddr_gray_top3 <= 0;
else if (re) raddr_gray_top3 <= raddr_plus1_gray_top3;
end
always @ (posedge rclk) begin
// waddr_gray_rclk <= waddr_gray;
waddr_gray_rclk[3:0] <= waddr_gray[3:0];
end
always @ (posedge wclk) begin
// raddr_gray_top3_wclk <= raddr_gray_top3;
raddr_gray_top3_wclk[2:0] <= raddr_gray_top3[2:0];
if (we) ram[waddr] <= data_in;
end
......
util_modules/gpio393.v
View file @ b721ae66
......@@ -65,9 +65,9 @@ module gpio393 #(
parameter GPIO_PORTEN = 24 // bit number to control port enables (up from this)
) (
input rst, // global reset
// input rst, // global reset
input mclk, // system clock
input mrst, // @posedge mclk, sync reset
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
......@@ -124,17 +124,17 @@ module gpio393 #(
// 1 0 2 1 1
// 1 1 3 0 0
always @ (posedge rst or posedge mclk) begin
if (rst) ch_en[0] <= 0;
always @ (posedge mclk) begin
if (mrst) ch_en[0] <= 0;
else if (set_mode_w && cmd_data[GPIO_PORTEN + 1]) ch_en[0] <= cmd_data[GPIO_PORTEN + 0];
if (rst) ch_en[1] <= 0;
if (mrst) ch_en[1] <= 0;
else if (set_mode_w && cmd_data[GPIO_PORTEN + 3]) ch_en[1] <= cmd_data[GPIO_PORTEN + 2];
if (rst) ch_en[2] <= 0;
if (mrst) ch_en[2] <= 0;
else if (set_mode_w && cmd_data[GPIO_PORTEN + 5]) ch_en[2] <= cmd_data[GPIO_PORTEN + 4];
if (rst) ch_en[3] <= 0;
if (mrst) ch_en[3] <= 0;
else if (set_mode_w && cmd_data[GPIO_PORTEN + 7]) ch_en[3] <= cmd_data[GPIO_PORTEN + 6];
end
......@@ -143,8 +143,9 @@ module gpio393 #(
genvar i;
for (i=0; i < GPIO_N; i=i+1) begin: gpio_block
gpio_bit gpio_bit_i (
.rst (rst), // input
// .rst (rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (set_mode_w), // input
.d_in (cmd_data[2*i +: 2]), // input[1:0]
.d_out (ds[i]), // output
......@@ -158,8 +159,8 @@ module gpio393 #(
) iobuf_gpio_i (
.O (io_pins[i]), // output
.IO (ext_pins[i]), // inout
.I (io_do[i]), // input
.T (io_t[i]) // input
.I (io_do[i]), // input
.T (io_t[i]) // input
);
end
......@@ -173,8 +174,9 @@ module gpio393 #(
.ADDR_WIDTH (1),
.DATA_WIDTH (32)
) cmd_deser_32bit_i (
.rst (rst), // input
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[0:0]
......@@ -187,22 +189,24 @@ module gpio393 #(
.PAYLOAD_BITS (12),
.REGISTER_STATUS (1)
) status_generate_i (
.rst (rst), // input
.clk (mclk), // input
.we (set_status_w), // input
.wd (cmd_data[7:0]), // input[7:0]
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (set_status_w), // input
.wd (cmd_data[7:0]), // input[7:0]
.status ({io_pins,2'b0}), // input[11:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
);
endmodule
module gpio_bit (
input rst, // global reset
// input rst, // global reset
input clk, // system clock
input srst, // @posedge clk - sync reset
input we,
input [1:0] d_in, // input bits
output d_out, // output data
......@@ -213,11 +217,11 @@ module gpio_bit (
assign d_out = d_r;
assign en_out = en_r;
always @ (posedge rst or posedge clk) begin
if (rst) d_r <= 0;
always @ (posedge clk) begin
if (srst) d_r <= 0;
else if (we && (|d_in)) d_r <= !d_in[0];
if (rst) en_r <= 0;
if (srst) en_r <= 0;
else if (we && (|d_in)) en_r <= !(&d_in);
end
......
util_modules/level_cross_clocks.v
View file @ b721ae66
/*******************************************************************************
* Module: level_cross_clocks
* Date:2015-07-19
* Author: andrey
* Author: Aandrey Filippov
* Description: re-sample signal to a different clock to reduce metastability
*
* Copyright (c) 2015 Elphel, Inc .
......
util_modules/mcont_common_chnbuf_reg.v
View file @ b721ae66
......@@ -35,7 +35,7 @@ module mcont_common_chnbuf_reg #(
output reg buf_run
);
reg buf_chn_sel;
always @ (posedge rst or posedge clk) begin
always @ (posedge clk) begin
if (rst) buf_chn_sel <= 0;
else buf_chn_sel <= (ext_buf_rchn==CHN_NUMBER) && !ext_buf_rrefresh;
......
util_modules/mcont_to_chnbuf_reg.v
View file @ b721ae66
......@@ -37,14 +37,16 @@ parameter CHN_NUMBER=0
output reg [63:0] buf_wdata_chn // @ negedge mclk
);
reg buf_chn_sel;
always @ (posedge rst or negedge clk) begin
if (rst) buf_chn_sel <= 0;
reg rst_nclk = 1;
always @ (negedge clk) rst_nclk <= rst;
always @ (negedge clk) begin
if (rst_nclk) buf_chn_sel <= 0;
else buf_chn_sel <= (ext_buf_wchn==CHN_NUMBER) && !ext_buf_wrefresh;
if (rst) buf_wr_chn <= 0;
if (rst_nclk) buf_wr_chn <= 0;
else buf_wr_chn <= buf_chn_sel && ext_buf_wr;
if (rst) buf_run <= 0;
if (rst_nclk) buf_run <= 0;
else buf_run <= (ext_buf_wchn==CHN_NUMBER) && !ext_buf_wrefresh && ext_buf_wrun;
end
......
util_modules/pulse_cross_clock.v
View file @ b721ae66
......@@ -44,9 +44,9 @@ module pulse_cross_clock#(
if (rst) busy_r <= 0;
else busy_r <= in_pulse || in_reg || (busy_r && (|out_reg[EXTRA_DLY_SAFE:0]));
end
always @(posedge dst_clk or posedge rst) begin
if (rst) out_reg <= 0;
else out_reg <= {out_reg[0] & ~out_reg[1],out_reg[0],in_reg};
// always @(posedge dst_clk or posedge rst) begin
always @(posedge dst_clk) begin
out_reg <= {out_reg[0] & ~out_reg[1],out_reg[0],in_reg};
end
endmodule
util_modules/status_generate.v
View file @ b721ae66
......@@ -37,9 +37,9 @@ module status_generate #(
)(
input rst,
input clk,
input srst, // @ posedge clk - sync reset
input we, // command strobe
input [7:0] wd, // command data - 6 bits of sequence and 2 mode bits
// input [PAYLOAD_BITS-1:0] status, // parallel status data to be sent out, may come from different clock domain
input [ALL_BITS-1:0] status, // parallel status data to be sent out, may come from different clock domain
output [7:0] ad, // byte-wide address/data
output rq, // request to send downstream (last byte with rq==0)
......@@ -58,6 +58,7 @@ module status_generate #(
) status_generate_extra_i (
.rst (rst), // input
.clk (clk), // input
.srst (srst), // input
.we (we), // input
.wd (wd), // input[7:0]
.status (status), // input[46:0]
......@@ -74,6 +75,7 @@ module status_generate #(
) status_generate_only_i (
.rst (rst), // input
.clk (clk), // input
.srst (srst), // input
.we (we), // input
.wd (wd), // input[7:0]
.status (status[PAYLOAD_BITS-1:0]), // input[14:0]
......@@ -95,6 +97,7 @@ module status_generate_only #(
)(
input rst,
input clk,
input srst, // @ posedge clk - sync reset
input we, // command strobe
input [7:0] wd, // command data - 6 bits of sequence and 2 mode bits
input [PAYLOAD_BITS-1:0] status, // parallel status data to be sent out, may come from different clock domain
......@@ -138,35 +141,42 @@ module status_generate_only #(
always @ (posedge rst or posedge clk) begin
if (rst) status_changed_r <= 0;
// else status_changed_r <= (status_changed_r && !start) || (status_r != status);
else if (srst) status_changed_r <= 0;
else if (start) status_changed_r <= 0;
else status_changed_r <= status_changed_r || (status_r != status_r0);
if (rst) mode <= 0;
else if (we) mode <= mode_w; // wd[7:6];
if (rst) mode <= 0;
else if (srst) mode <= 0;
else if (we) mode <= mode_w; // wd[7:6];
if (rst) seq <= 0;
if (rst) seq <= 0;
else if (srst) seq <= 0;
else if (we) seq <= wd[5:0];
else if ((mode==3) && start) seq <= seq+1;
if (rst) cmd_pend <= 0;
else if (srst) cmd_pend <= 0;
else if (we && (mode_w!=0)) cmd_pend <= 1;
else if (start) cmd_pend <= 0;
if (rst) status_r0r <= 0;
else if (srst) status_r0r <= 0;
else status_r0r <= status;
if (rst) status_r<=0;
else if (srst) status_r<=0;
else if (start) status_r<=status_r0;
if (rst) data <= STATUS_REG_ADDR;
if (rst) data <= STATUS_REG_ADDR;
else if (srst) data <= STATUS_REG_ADDR;
else if (start) data <= (NUM_BYTES>2)?
{aligned_status[ALIGNED_STATUS_WIDTH-1:ALIGNED_STATUS_BIT_2],seq,status_r0[1:0]}:
{seq,status_r0[1:0]};
else if ((NUM_BYTES>2) && snd_rest) data <= data >> 8; // never happens with 2-byte packet
else data <= STATUS_REG_ADDR;
if (rst) rq_r <= 0;
if (rst) rq_r <= 0;
else if (srst) rq_r <= 0;
else if (need_to_send && !rq_r[0]) rq_r <= {NUM_BYTES-1{1'b1}};
else if (start || ((NUM_BYTES>2) && !rq_r[NUM_BYTES-2])) rq_r <= rq_r >> 1;
end
......@@ -186,6 +196,7 @@ module status_generate_extra #(
)(
input rst,
input clk,
input srst, // @ posedge clk - sync reset
input we, // command strobe
input [7:0] wd, // command data - 6 bits of sequence and 2 mode bits
// input [PAYLOAD_BITS-1:0] status, // parallel status data to be sent out, may come from different clock domain
......@@ -271,45 +282,56 @@ module status_generate_extra #(
always @ (posedge rst or posedge clk) begin
if (rst) status_changed_r <= 0;
else if (srst) status_changed_r <= 0;
else if (start_last) status_changed_r <= 0;
else status_changed_r <= status_changed_r || (status_r != status_r0);
if (rst) mode <= 0;
else if (we) mode <= mode_w; // wd[7:6];
if (rst) mode <= 0;
else if (srst) mode <= 0;
else if (we) mode <= mode_w; // wd[7:6];
if (rst) seq <= 0;
if (rst) seq <= 0;
else if (srst) seq <= 0;
else if (we) seq <= wd[5:0];
else if ((mode==3) && start_status) seq <= seq+1; // no need to increment sequence number if no status is sent
if (rst) cmd_pend <= 0;
else if (srst) cmd_pend <= 0;
else if (we && (mode_w!=0)) cmd_pend <= 1;
else if (start_last) cmd_pend <= 0;
if (rst) status_r0r <= 0;
else status_r0r <= status[STATUS_BITS-1:0];
if (rst) status_r0r <= 0;
else if (srst) status_r0r <= 0;
else status_r0r <= status[STATUS_BITS-1:0];
if (rst) status_r <= 0;
else if (srst) status_r <= 0;
else if (start_last) status_r <= status_r0;
if (!rst) next_addr <= first_addr;
if (rst) next_addr <= first_addr;
else if (srst) next_addr <= first_addr;
else if (!need_to_send || start_last) next_addr <= first_addr;
else if (start && (msg1hot[EXTRA_WORDS -1:0])) next_addr <= STATUS_REG_ADDR;
else if (start) next_addr <= next_addr + 1;
if (!rst) next_mask <= first_mask;
if (rst) next_mask <= first_mask;
else if (srst) next_mask <= first_mask;
else if (!need_to_send || start_last) next_mask <= first_mask;
else if (start && (msg1hot[EXTRA_WORDS -1 :0])) next_mask <= STATUS_MASK;
if (rst) rq_r <= 0;
else if (srst) rq_r <= 0;
else if (need_to_send && !rq_r[0]) rq_r <= 1;
else if (start) rq_r <= next_mask;
else if (|rq_r) rq_r <= rq_r >> 1;
if (rst) msg_num <= 0;
if (rst) msg_num <= 0;
else if (srst) msg_num <= 0;
else if (!need_to_send) msg_num <= 0;
else if (start) msg_num <= msg_num + 1;
if (rst) msg1hot <= 0;
if (rst) msg1hot <= 0;
else if (srst) msg1hot <= 0;
else if (!need_to_send) msg1hot <= 0;
else if (start) msg1hot <= msg1hot >> 1;
......
util_modules/status_router16.v
View file @ b721ae66
......@@ -23,6 +23,7 @@
module status_router16(
input rst,
input clk,
input srst, // @ posedge clk
// 4 input channels
input [7:0] db_in0,
input rq_in0,
......@@ -86,6 +87,7 @@ module status_router16(
status_router2 status_router2_top_i (
.rst (rst), // input
.clk (clk), // input
.srst (srst), // input
.db_in0 (db_int[0]), // input[7:0]
.rq_in0 (rq_int[0]), // input
.start_in0 (start_int[0]), // output
......@@ -100,6 +102,7 @@ module status_router16(
status_router8 status_router8_01234567_i (
.rst (rst), // input
.clk (clk), // input
.srst (srst), // input
.db_in0 (db_in0), // input[7:0]
.rq_in0 (rq_in0), // input
.start_in0 (start_in0), // output
......@@ -132,6 +135,7 @@ module status_router16(
status_router8 status_router8_89abcdef_i (
.rst (rst), // input
.clk (clk), // input
.srst (srst), // input
.db_in0 (db_in8), // input[7:0]
.rq_in0 (rq_in8), // input
.start_in0 (start_in8), // output
......
util_modules/status_router2.v
View file @ b721ae66
......@@ -25,6 +25,7 @@
module status_router2 (
input rst,
input clk,
input srst, // sync reset
// 2 input channels
input [7:0] db_in0,
input rq_in0,
......@@ -77,20 +78,24 @@ module status_router2 (
assign fifo_nempty=fifo_nempty_pre & ~fifo_last_byte;
always @ (posedge rst or posedge clk) begin
if (rst) rcv_rest_r<= 0;
else rcv_rest_r <= (rcv_rest_r & rq_in) | start_rcv;
if (rst) rcv_rest_r<= 0;
else if (srst) rcv_rest_r<= 0;
else rcv_rest_r <= (rcv_rest_r & rq_in) | start_rcv;
if (rst) next_chn<= 0;
if (rst) next_chn<= 0;
else if (srst) next_chn<= 0;
else if (|fifo_re) next_chn <= fifo_re[0]; // just to be fair
if (rst) current_chn_r <= 0;
else if (srst) current_chn_r <= 0;
else if (set_other_only_w) current_chn_r <= ~current_chn_r;
else if (snd_pre_start) current_chn_r <= chn_sel_w;
/// else if (|fifo_nempty && !snd_rest_r) current_chn_r <= chn_sel_w;
//|fifo_nempty && (!snd_rest_r
if (rst) snd_rest_r<= 0;
else snd_rest_r <= (snd_rest_r & ~snd_last_byte) | start_out;
if (rst) snd_rest_r<= 0;
else if (srst) snd_rest_r<= 0;
else snd_rest_r <= (snd_rest_r & ~snd_last_byte) | start_out;
end
/* fifo_same_clock has currently latency of 2 cycles, use smth. faster here? - fifo_1cycle (but it has unregistered data output) */
......@@ -98,8 +103,9 @@ module status_router2 (
.DATA_WIDTH(9),
.DATA_DEPTH(4) // 16
) fifo_in0_i (
.rst (rst), // input
.rst (1'b0), // rst), // input
.clk (clk), // input
.srst (srst), // input
.we (start_rcv[0] || rcv_rest_r[0]), // input
.re (fifo_re[0]), // input
.data_in ({rcv_rest_r[0] & ~rq_in[0], db_in0}), // input[8:0] MSB marks last byte
......@@ -119,8 +125,9 @@ module status_router2 (
.DATA_WIDTH(9),
.DATA_DEPTH(4) // 16
) fifo_in1_i (
.rst (rst), // input
.rst (1'b0), // rst), // input
.clk (clk), // input
.srst (srst), // input
.we (start_rcv[1] || rcv_rest_r[1]), // input
.re (fifo_re[1]), // input
.data_in ({rcv_rest_r[1] & ~rq_in[1], db_in1}), // input[8:0] MSB marks last byte
......
util_modules/status_router4.v
View file @ b721ae66
......@@ -23,6 +23,7 @@
module status_router4(
input rst,
input clk,
input srst, // @ posedge clk
// 4 input channels
input [7:0] db_in0,
input rq_in0,
......@@ -49,6 +50,7 @@ module status_router4(
status_router2 status_router2_top_i (
.rst (rst), // input
.clk (clk), // input
.srst (srst), // input
.db_in0 (db_int[0]), // input[7:0]
.rq_in0 (rq_int[0]), // input
.start_in0 (start_int[0]), // output
......@@ -63,6 +65,7 @@ module status_router4(
status_router2 status_router2_01_i (
.rst (rst), // input
.clk (clk), // input
.srst (srst), // input
.db_in0 (db_in0), // input[7:0]
.rq_in0 (rq_in0), // input
.start_in0 (start_in0), // output
......@@ -77,6 +80,7 @@ module status_router4(
status_router2 status_router2_23_i (
.rst (rst), // input
.clk (clk), // input
.srst (srst), // input
.db_in0 (db_in2), // input[7:0]
.rq_in0 (rq_in2), // input
.start_in0 (start_in2), // output
......
util_modules/status_router8.v
View file @ b721ae66
......@@ -23,6 +23,7 @@
module status_router8(
input rst,
input clk,
input srst, // @ posedge clk
// 4 input channels
input [7:0] db_in0,
input rq_in0,
......@@ -61,6 +62,7 @@ module status_router8(
status_router2 status_router2_top_i (
.rst (rst), // input
.clk (clk), // input
.srst (srst), // input
.db_in0 (db_int[0]), // input[7:0]
.rq_in0 (rq_int[0]), // input
.start_in0 (start_int[0]), // output
......@@ -75,6 +77,7 @@ module status_router8(
status_router4 status_router4_0123_i (
.rst (rst), // input
.clk (clk), // input
.srst (srst), // input
.db_in0 (db_in0), // input[7:0]
.rq_in0 (rq_in0), // input
.start_in0 (start_in0), // output
......@@ -95,6 +98,7 @@ module status_router8(
status_router4 status_router4_4567_i (
.rst (rst), // input
.clk (clk), // input
.srst (srst), // input
.db_in0 (db_in4), // input[7:0]
.rq_in0 (rq_in4), // input
.start_in0 (start_in4), // output
......
x393.v
View file @ b721ae66
......@@ -97,29 +97,23 @@ module x393 #(
// localparam COLADDR_NUMBER=10;
// Source for reset and clock
(* keep = "true" *)
wire [3:0] fclk; // PL Clocks [3:0], output
wire [3:0] fclk; // PL Clocks [3:0], output
(* keep = "true" *)
wire [3:0] frst; // PL Clocks [3:0], output
wire [3:0] frst; // PL Clocks [3:0], output
// AXI write interface signals
//(* keep = "true" *)
wire axi_aclk; // clock - should be buffered
// wire axi_naclk; // debugging
// wire axi_aresetn; // reset, active low
wire axi_aclk; // clock - should be buffered
//(* dont_touch = "true" *)
wire axi_rst; // reset, active high
wire axi_grst; // reset, active high, global (try to get rid of)
// AXI Write Address
wire [31:0] maxi0_awaddr; // AWADDR[31:0], input
wire maxi0_awvalid; // AWVALID, input
wire maxi0_awready; // AWREADY, output
wire [11:0] maxi0_awid; // AWID[11:0], input
// input [ 1:0] awlock, // AWLOCK[1:0], input
// input [ 3:0] awcache, // AWCACHE[3:0], input
// input [ 2:0] awprot, // AWPROT[2:0], input
wire [31:0] maxi0_awaddr; // AWADDR[31:0], input
wire maxi0_awvalid; // AWVALID, input
wire maxi0_awready; // AWREADY, output
wire [11:0] maxi0_awid; // AWID[11:0], input
wire [ 3:0] maxi0_awlen; // AWLEN[3:0], input
wire [ 1:0] maxi0_awsize; // AWSIZE[1:0], input
wire [ 1:0] maxi0_awburst; // AWBURST[1:0], input
// input [ 3:0] awqos, // AWQOS[3:0], input
// AXI PS Master GP0: Write Data
wire [31:0] maxi0_wdata; // WDATA[31:0], input
wire maxi0_wvalid; // WVALID, input
......@@ -139,7 +133,7 @@ module x393 #(
wire axiwr_dev_ready; // extrernal combinatorial ready signal, multiplexed from different sources according to pre_awaddr@start_burst
wire axiwr_wclk;
wire [AXI_WR_ADDR_BITS-1:0] axiwr_waddr;
wire axiwr_wen; // external memory write enable, (internally combined with registered dev_ready
wire axiwr_wen; // external memory write enable, (internally combined with registered dev_ready
// SuppressWarnings VEditor unused (yet?)
wire [3:0] axiwr_bram_wstb;
wire [31:0] axiwr_wdata;
......@@ -149,13 +143,9 @@ module x393 #(
wire maxi0_arvalid; // ARVALID, input
wire maxi0_arready; // ARREADY, output
wire [11:0] maxi0_arid; // ARID[11:0], input
// input [ 1:0] arlock, // ARLOCK[1:0], input
// input [ 3:0] archache,// ARCACHE[3:0], input
// input [ 2:0] arprot, // ARPROT[2:0], input
wire [ 3:0] maxi0_arlen; // ARLEN[3:0], input
wire [ 1:0] maxi0_arsize; // ARSIZE[1:0], input
wire [ 1:0] maxi0_arburst; // ARBURST[1:0], input
// input [ 3:0] adqos, // ARQOS[3:0], input
// AXI Read Data
wire [31:0] maxi0_rdata; // RDATA[31:0], output
wire maxi0_rvalid; // RVALID, output
......@@ -195,6 +185,7 @@ module x393 #(
// global clocks
wire mclk; // global clock, memory controller, command/status network (currently 200MHz)
wire mcntrl_locked; // to generate syn resets
wire ref_clk; // global clock for idelay_ctrl calibration
wire hclk; // global clock, axi_hp (150MHz) derived from aclk_in = 50MHz
......@@ -212,6 +203,19 @@ module x393 #(
// Make it independent of pixel, compressor and mclk so it can be frozen
wire logger_clk; // global clock for the event logger. Use 100 MHz, shared with camsync_clk
assign logger_clk = camsync_clk;
wire mrst; // @ posedge mclk
wire prst; // @ posedge pclk
wire xrst; // @ posedge xclk
wire crst; // @ posedge camsync_clk
wire lrst; // @ posedge logger_clk;
wire arst; // @ posedge axi_aclk;
wire hrst; // @ posedge hclk;
wire idelay_ctrl_reset; // to reset idelay_cntrl
wire time_ref; // RTC reference: integer number of microseconds, less than mclk/2. Not a global clock
......@@ -533,30 +537,31 @@ module x393 #(
// delay status_selected and mcntrl_axird_selected to match data for multiplexing
always @(posedge axi_rst or posedge axird_bram_rclk) begin // axird_bram_rclk==axi_aclk
// always @(posedge axi_rst or posedge axi_aclk) begin
if (axi_rst) status_selected_ren <= 1'b0;
// always @(posedge axi_grst or posedge axird_bram_rclk) begin // axird_bram_rclk==axi_aclk
always @(posedge axird_bram_rclk) begin // axird_bram_rclk==axi_aclk
if (arst) status_selected_ren <= 1'b0;
else if (axird_ren) status_selected_ren <= status_selected;
if (axi_rst) status_selected_regen <= 1'b0;
if (arst) status_selected_regen <= 1'b0;
else if (axird_regen) status_selected_regen <= status_selected_ren;
if (axi_rst) readback_selected_ren <= 1'b0;
if (arst) readback_selected_ren <= 1'b0;
else if (axird_ren) readback_selected_ren <= readback_selected;
if (axi_rst) readback_selected_regen <= 1'b0;
if (arst) readback_selected_regen <= 1'b0;
else if (axird_regen) readback_selected_regen <= readback_selected_ren;
if (axi_rst) mcntrl_axird_selected_ren <= 1'b0;
if (arst) mcntrl_axird_selected_ren <= 1'b0;
else if (axird_ren) mcntrl_axird_selected_ren <= mcntrl_axird_selected;
if (axi_rst) mcntrl_axird_selected_regen <= 1'b0;
if (arst) mcntrl_axird_selected_regen <= 1'b0;
else if (axird_regen) mcntrl_axird_selected_regen <= mcntrl_axird_selected_ren;
end
always @(posedge comb_rst or posedge axi_aclk) begin
always @(posedge comb_rst or posedge axi_aclk) begin
if (comb_rst) axi_rst_pre <= 1'b1;
else axi_rst_pre <= 1'b0;
end
......@@ -592,21 +597,8 @@ module x393 #(
end
`endif
BUFG bufg_axi_rst_i (.O(axi_rst),.I(axi_rst_pre));
/*
BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
axi_hp_clk #(
.CLKIN_PERIOD(CLKIN_PERIOD),
.CLKFBOUT_MULT_AXIHP(CLKFBOUT_MULT_AXIHP),
.CLKFBOUT_DIV_AXIHP(CLKFBOUT_DIV_AXIHP)
) axi_hp_clk_i (
.rst (axi_rst), // input
.clk_in (axi_aclk), // input
.clk_axihp (hclk), // output
.locked_axihp () // output // not controlled?
);
BUFG bufg_axi_rst_i (.O(axi_grst),.I(axi_rst_pre)); // will go only to memory controller (to minimize changes), later - remove from there too
*/
// channel test module
mcntrl393_test01 #(
.MCNTRL_TEST01_ADDR (MCNTRL_TEST01_ADDR),
......@@ -625,37 +617,37 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR (MCNTRL_TEST01_STATUS_REG_CHN3_ADDR),
.MCNTRL_TEST01_STATUS_REG_CHN4_ADDR (MCNTRL_TEST01_STATUS_REG_CHN4_ADDR)
) mcntrl393_test01_i (
.rst (axi_rst), // input
.mclk (mclk), // input
.cmd_ad (cmd_test01_ad), // input[7:0]
.cmd_stb (cmd_test01_stb), // input
.status_ad (status_test01_ad), // output[7:0]
.status_rq (status_test01_rq), // output
.status_start (status_test01_start), // input
.frame_start_chn1 (), //frame_start_chn1), // output
.next_page_chn1 (), //next_page_chn1), // output
.page_ready_chn1 (1'b0), // page_ready_chn1), // input
.frame_done_chn1 (1'b0), //frame_done_chn1), // input
.line_unfinished_chn1 (16'b0), //line_unfinished_chn1), // input[15:0]
.suspend_chn1 (), //suspend_chn1), // output
.frame_start_chn2 (frame_start_chn2), // output
.next_page_chn2 (next_page_chn2), // output
.page_ready_chn2 (page_ready_chn2), // input
.frame_done_chn2 (frame_done_chn2), // input
.mrst (mrst), // input
.mclk (mclk), // input
.cmd_ad (cmd_test01_ad), // input[7:0]
.cmd_stb (cmd_test01_stb), // input
.status_ad (status_test01_ad), // output[7:0]
.status_rq (status_test01_rq), // output
.status_start (status_test01_start), // input
.frame_start_chn1 (), //frame_start_chn1), // output
.next_page_chn1 (), //next_page_chn1), // output
.page_ready_chn1 (1'b0), // page_ready_chn1), // input
.frame_done_chn1 (1'b0), //frame_done_chn1), // input
.line_unfinished_chn1 (16'b0), //line_unfinished_chn1), // input[15:0]
.suspend_chn1 (), //suspend_chn1), // output
.frame_start_chn2 (frame_start_chn2), // output
.next_page_chn2 (next_page_chn2), // output
.page_ready_chn2 (page_ready_chn2), // input
.frame_done_chn2 (frame_done_chn2), // input
.line_unfinished_chn2 (line_unfinished_chn2), // input[15:0]
.suspend_chn2 (suspend_chn2), // output
.frame_start_chn3 (frame_start_chn3), // output
.next_page_chn3 (next_page_chn3), // output
.page_ready_chn3 (page_ready_chn3), // input
.frame_done_chn3 (frame_done_chn3), // input
.suspend_chn2 (suspend_chn2), // output
.frame_start_chn3 (frame_start_chn3), // output
.next_page_chn3 (next_page_chn3), // output
.page_ready_chn3 (page_ready_chn3), // input
.frame_done_chn3 (frame_done_chn3), // input
.line_unfinished_chn3 (line_unfinished_chn3), // input[15:0]
.suspend_chn3 (suspend_chn3), // output
.frame_start_chn4 (frame_start_chn4), // output
.next_page_chn4 (next_page_chn4), // output
.page_ready_chn4 (page_ready_chn4), // input
.frame_done_chn4 (frame_done_chn4), // input
.suspend_chn3 (suspend_chn3), // output
.frame_start_chn4 (frame_start_chn4), // output
.next_page_chn4 (next_page_chn4), // output
.page_ready_chn4 (page_ready_chn4), // input
.frame_done_chn4 (frame_done_chn4), // input
.line_unfinished_chn4 (line_unfinished_chn4), // input[15:0]
.suspend_chn4 (suspend_chn4) // output
.suspend_chn4 (suspend_chn4) // output
);
// Interface to channels to read/write memory (including 4 page BRAM buffers)
......@@ -701,7 +693,8 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
) cmd_mux_i ( // SuppressThisWarning ISExst: Output port <par_data>,<par_waddr>, <cseq_ackn> of the instance <cmd_mux_i> is unconnected or connected to loadless signal.
.axi_clk (axiwr_wclk), // input
.mclk (mclk), // input
.rst (axi_rst), // input
.mrst (mrst), // input
.arst (arst), // input
.pre_waddr (axiwr_pre_awaddr[AXI_WR_ADDR_BITS-1:0]), // input[12:0] // SuppressThisWarning VivadoSynthesis: [Synth 8-3295] tying undriven pin #cmd_mux_i:pre_waddr[9:0] to constant 0
.start_wburst (axiwr_start_burst), // input
.waddr (axiwr_waddr[AXI_WR_ADDR_BITS-1:0]), // input[12:0]
......@@ -735,7 +728,7 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.CMDFRAMESEQ_RST_BIT (CMDFRAMESEQ_RST_BIT),
.CMDFRAMESEQ_RUN_BIT (CMDFRAMESEQ_RUN_BIT)
) cmd_frame_sequencer_i (
.rst (axi_rst), // input
.mrst (mrst), // input
.mclk (mclk), // input
.cmd_ad (cmd_sequencer_ad), // input[7:0]
.cmd_stb (cmd_sequencer_stb), // input
......@@ -755,7 +748,7 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.CMDSEQMUX_STATUS (CMDSEQMUX_STATUS),
.AXI_WR_ADDR_BITS (AXI_WR_ADDR_BITS)
) cmd_seq_mux_i (
.rst (axi_rst), // input
.mrst (mrst), // input
.mclk (mclk), // input
.cmd_ad (cmd_sequencer_ad), // input[7:0]
.cmd_stb (cmd_sequencer_stb), // input
......@@ -802,18 +795,19 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.CONTROL_RBACK_ADDR (CONTROL_RBACK_ADDR),
.CONTROL_RBACK_ADDR_MASK (CONTROL_RBACK_ADDR_MASK)
) cmd_readback_i (
.rst (axi_rst), // input
.mclk (mclk), // input
.axi_clk (axird_bram_rclk), // input
.par_waddr (par_waddr), // input[13:0]
.par_data (par_data), // input[31:0]
.ad_stb (cmd_root_stb), // input
.axird_pre_araddr (axird_pre_araddr), // input[13:0]
.axird_start_burst (axird_start_burst), // input
.mrst (mrst), // input
.arst (arst), // input
.mclk (mclk), // input
.axi_clk (axird_bram_rclk), // input
.par_waddr (par_waddr), // input[13:0]
.par_data (par_data), // input[31:0]
.ad_stb (cmd_root_stb), // input
.axird_pre_araddr (axird_pre_araddr), // input[13:0]
.axird_start_burst (axird_start_burst), // input
.axird_raddr (axird_raddr[CONTROL_RBACK_DEPTH-1:0]), // input[9:0]
.axird_ren (axird_ren), // input
.axird_rdata (readback_rdata), // output[31:0]
.axird_selected (readback_selected) // output
.axird_ren (axird_ren), // input
.axird_rdata (readback_rdata), // output[31:0]
.axird_selected (readback_selected) // output
);
status_read #(
......@@ -822,100 +816,96 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.AXI_RD_ADDR_BITS (AXI_RD_ADDR_BITS),
.STATUS_DEPTH (STATUS_DEPTH)
) status_read_i (
.rst (axi_rst), // input
.clk (mclk), // input
.axi_clk (axird_bram_rclk), // input == axi_aclk
.axird_pre_araddr (axird_pre_araddr), // input[7:0] // SuppressThisWarning VivadoSynthesis: [Synth 8-3295] tying undriven pin #status_read_i:axird_pre_araddr[9:0] to constant 0
.axird_start_burst(axird_start_burst), // input
.mrst (mrst), // input
.arst (arst), // input
.clk (mclk), // input
.axi_clk (axird_bram_rclk), // input == axi_aclk
.axird_pre_araddr (axird_pre_araddr), // input[7:0] // SuppressThisWarning VivadoSynthesis: [Synth 8-3295] tying undriven pin #status_read_i:axird_pre_araddr[9:0] to constant 0
.axird_start_burst(axird_start_burst), // input
.axird_raddr (axird_raddr[STATUS_DEPTH-1:0]), // input[7:0]
.axird_ren (axird_ren), // input
.axird_regen (axird_regen), // input
.axird_rdata (status_rdata), // output[31:0]
.axird_selected (status_selected), // output
.ad (status_root_ad), // input[7:0]
.rq (status_root_rq), // input
.start (status_root_start) // output
.axird_ren (axird_ren), // input
.axird_regen (axird_regen), // input
.axird_rdata (status_rdata), // output[31:0]
.axird_selected (status_selected), // output
.ad (status_root_ad), // input[7:0]
.rq (status_root_rq), // input
.start (status_root_start) // output
);
// mux status info from the memory controller and other modules
status_router16 status_router16_top_i (
.rst (axi_rst), // input
.clk (mclk), // input
.db_in0 (status_mcontr_ad), // input[7:0]
.rq_in0 (status_mcontr_rq), // input
.start_in0 (status_mcontr_start), // output
.rst (1'b0), //axi_rst), // input
.clk (mclk), // input
.srst (mrst), // input
.db_in0 (status_mcontr_ad), // input[7:0]
.rq_in0 (status_mcontr_rq), // input
.start_in0 (status_mcontr_start), // output
.db_in1 (status_test01_ad), // input[7:0]
.rq_in1 (status_test01_rq), // input
.start_in1 (status_test01_start), // output
.db_in1 (status_test01_ad), // input[7:0]
.rq_in1 (status_test01_rq), // input
.start_in1 (status_test01_start), // output
.db_in2 (status_membridge_ad), // input[7:0]
.rq_in2 (status_membridge_rq), // input
.start_in2 (status_membridge_start), // output
.db_in2 (status_membridge_ad), // input[7:0]
.rq_in2 (status_membridge_rq), // input
.start_in2 (status_membridge_start), // output
// .db_in3 (status_other_ad), // input[7:0]
// .rq_in3 (status_other_rq), // input
// .start_in3 (status_other_start), // output
.db_in3 (status_sensor_ad), // input[7:0]
.rq_in3 (status_sensor_rq), // input
.start_in3 (status_sensor_start), // output
.db_in3 (status_sensor_ad), // input[7:0]
.rq_in3 (status_sensor_rq), // input
.start_in3 (status_sensor_start), // output
.db_in4 (status_compressor_ad), // input[7:0]
.rq_in4 (status_compressor_rq), // input
.db_in4 (status_compressor_ad), // input[7:0]
.rq_in4 (status_compressor_rq), // input
.start_in4 (status_compressor_start), // output
.db_in5 (status_sequencer_ad), // input[7:0]
.rq_in5 (status_sequencer_rq), // input
.start_in5 (status_sequencer_start), // output
.db_in5 (status_sequencer_ad), // input[7:0]
.rq_in5 (status_sequencer_rq), // input
.start_in5 (status_sequencer_start), // output
.db_in6 (status_logger_ad), // input[7:0]
.rq_in6 (status_logger_rq), // input
.start_in6 (status_logger_start), // output
.db_in6 (status_logger_ad), // input[7:0]
.rq_in6 (status_logger_rq), // input
.start_in6 (status_logger_start), // output
.db_in7 (status_timing_ad), // input[7:0]
.rq_in7 (status_timing_rq), // input
.start_in7 (status_timing_start), // output
.db_in8 (status_gpio_ad), // input[7:0]
.rq_in8 (status_gpio_rq), // input
.start_in8 (status_gpio_start), // output
.rq_in7 (status_timing_rq), // input
.start_in7 (status_timing_start), // output
.db_in9 (status_saxi1wr_ad), // input[7:0]
.rq_in9 (status_saxi1wr_rq), // input
.start_in9 (status_saxi1wr_start), // output
.db_in8 (status_gpio_ad), // input[7:0]
.rq_in8 (status_gpio_rq), // input
.start_in8 (status_gpio_start), // output
.db_in10 (status_clocks_ad), // input[7:0]
.rq_in10 (status_clocks_rq), // input
.start_in10(status_clocks_start), // output
.db_in9 (status_saxi1wr_ad), // input[7:0]
.rq_in9 (status_saxi1wr_rq), // input
.start_in9 (status_saxi1wr_start), // output
.db_in11 (8'b0), // input[7:0]
.rq_in11 (1'b0), // input
.start_in11(), // output
.db_in10 (status_clocks_ad), // input[7:0]
.rq_in10 (status_clocks_rq), // input
.start_in10(status_clocks_start), // output
.db_in12 (8'b0), // input[7:0]
.rq_in12 (1'b0), // input
.start_in12(), // output
.db_in11 (8'b0), // input[7:0]
.rq_in11 (1'b0), // input
.start_in11(), // output
.db_in13 (8'b0), // input[7:0]
.rq_in13 (1'b0), // input
.start_in13(), // output
.db_in12 (8'b0), // input[7:0]
.rq_in12 (1'b0), // input
.start_in12(), // output
.db_in14 (8'b0), // input[7:0]
.rq_in14 (1'b0), // input
.start_in14(), // output
.db_in13 (8'b0), // input[7:0]
.rq_in13 (1'b0), // input
.start_in13(), // output
.db_in15 (8'b0), // input[7:0]
.rq_in15 (1'b0), // input
.start_in15(), // output
.db_in14 (8'b0), // input[7:0]
.rq_in14 (1'b0), // input
.start_in14(), // output
.db_in15 (8'b0), // input[7:0]
.rq_in15 (1'b0), // input
.start_in15(), // output
.db_out (status_root_ad), // output[7:0]
.rq_out (status_root_rq), // output
.start_out (status_root_start) // input
.db_out (status_root_ad), // output[7:0]
.rq_out (status_root_rq), // output
.start_out (status_root_start) // input
);
/* Instance template for module mcntrl393 */
mcntrl393 #(
.MCONTR_SENS_BASE('h680),
.MCONTR_SENS_INC('h10),
......@@ -1055,10 +1045,14 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.RSEL (RSEL),
.WSEL (WSEL)
) mcntrl393_i (
.rst_in (axi_rst), // input
.rst_in (axi_grst), // input global reset, but does not need to be global
.clk_in (axi_aclk), // == axird_bram_rclk SuppressThisWarning VivadoSynthesis: [Synth 8-3295] tying undriven pin #mcntrl393_i:clk_in to constant 0
.mclk (mclk), // output
.mrst (mrst),
.locked (mcntrl_locked), // to generate sync reset
.ref_clk (ref_clk), // output
.idelay_ctrl_reset (idelay_ctrl_reset), // output
.cmd_ad (cmd_mcontr_ad), // input[7:0]
.cmd_stb (cmd_mcontr_stb), // input
.status_ad (status_mcontr_ad[7:0]), // output[7:0]
......@@ -1230,73 +1224,74 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.FRAME_HEIGHT_BITS (FRAME_HEIGHT_BITS),
.FRAME_WIDTH_BITS (FRAME_WIDTH_BITS)
) membridge_i (
.rst (axi_rst), // input
.mclk (mclk), // input
.hclk (hclk), // input
.cmd_ad (cmd_membridge_ad), // input[7:0]
.cmd_stb (cmd_membridge_stb), // input
.mrst (mrst), // input
.hrst (hrst), // input
.mclk (mclk), // input
.hclk (hclk), // input
.cmd_ad (cmd_membridge_ad), // input[7:0]
.cmd_stb (cmd_membridge_stb), // input
.status_ad (status_membridge_ad[7:0]), // output[7:0]
.status_rq (status_membridge_rq), // output
.status_start (status_membridge_start), // input
.frame_start_chn (frame_start_chn1), // output
.next_page_chn (next_page_chn1), // output
.cmd_wrmem (cmd_wrmem_chn1), // input
.page_ready_chn (page_ready_chn1), // input
.frame_done_chn (frame_done_chn1), // input
.line_unfinished_chn1 (line_unfinished_chn1), // input[15:0]
.suspend_chn1 (suspend_chn1), // output
.xfer_reset_page_rd (xfer_reset_page1_rd), // input
.buf_wpage_nxt (buf_wpage_nxt_chn1), // input
.buf_wr (buf_wr_chn1), // input
.buf_wdata (buf_wdata_chn1[63:0]), // input[63:0]
.xfer_reset_page_wr (xfer_reset_page1_wr), // input
.buf_rpage_nxt (rpage_nxt_chn1), // input
.buf_rd (buf_rd_chn1), // input
.buf_rdata (buf_rdata_chn1[63:0]), // output[63:0]
.afi_awaddr (afi0_awaddr), // output[31:0]
.afi_awvalid (afi0_awvalid), // output
.afi_awready (afi0_awready), // input
.afi_awid (afi0_awid), // output[5:0]
.afi_awlock (afi0_awlock), // output[1:0]
.afi_awcache (afi0_awcache), // output[3:0]
.afi_awprot (afi0_awprot), // output[2:0]
.afi_awlen (afi0_awlen), // output[3:0]
.afi_awsize (afi0_awsize), // output[2:0]
.afi_awburst (afi0_awburst), // output[1:0]
.afi_awqos (afi0_awqos), // output[3:0]
.afi_wdata (afi0_wdata), // output[63:0]
.afi_wvalid (afi0_wvalid), // output
.afi_wready (afi0_wready), // input
.afi_wid (afi0_wid), // output[5:0]
.afi_wlast (afi0_wlast), // output
.afi_wstrb (afi0_wstrb), // output[7:0]
.afi_bvalid (afi0_bvalid), // input
.afi_bready (afi0_bready), // output
.afi_bid (afi0_bid), // input[5:0]
.afi_bresp (afi0_bresp), // input[1:0]
.afi_wcount (afi0_wcount), // input[7:0]
.afi_wacount (afi0_wacount), // input[5:0]
.afi_wrissuecap1en (afi0_wrissuecap1en), // output
.afi_araddr (afi0_araddr), // output[31:0]
.afi_arvalid (afi0_arvalid), // output
.afi_arready (afi0_arready), // input
.afi_arid (afi0_arid), // output[5:0]
.afi_arlock (afi0_arlock), // output[1:0]
.afi_arcache (afi0_arcache), // output[3:0]
.afi_arprot (afi0_arprot), // output[2:0]
.afi_arlen (afi0_arlen), // output[3:0]
.afi_arsize (afi0_arsize), // output[2:0]
.afi_arburst (afi0_arburst), // output[1:0]
.afi_arqos (afi0_arqos), // output[3:0]
.afi_rdata (afi0_rdata), // input[63:0]
.afi_rvalid (afi0_rvalid), // input
.afi_rready (afi0_rready), // output
.afi_rid (afi0_rid), // input[5:0]
.afi_rlast (afi0_rlast), // input
.afi_rresp (afi0_rresp), // input[2:0]
.afi_rcount (afi0_rcount), // input[7:0]
.afi_racount (afi0_racount), // input[2:0]
.afi_rdissuecap1en (afi0_rdissuecap1en) // output
.frame_start_chn (frame_start_chn1), // output
.next_page_chn (next_page_chn1), // output
.cmd_wrmem (cmd_wrmem_chn1), // input
.page_ready_chn (page_ready_chn1), // input
.frame_done_chn (frame_done_chn1), // input
.line_unfinished_chn1 (line_unfinished_chn1), // input[15:0]
.suspend_chn1 (suspend_chn1), // output
.xfer_reset_page_rd (xfer_reset_page1_rd), // input
.buf_wpage_nxt (buf_wpage_nxt_chn1), // input
.buf_wr (buf_wr_chn1), // input
.buf_wdata (buf_wdata_chn1[63:0]), // input[63:0]
.xfer_reset_page_wr (xfer_reset_page1_wr), // input
.buf_rpage_nxt (rpage_nxt_chn1), // input
.buf_rd (buf_rd_chn1), // input
.buf_rdata (buf_rdata_chn1[63:0]), // output[63:0]
.afi_awaddr (afi0_awaddr), // output[31:0]
.afi_awvalid (afi0_awvalid), // output
.afi_awready (afi0_awready), // input
.afi_awid (afi0_awid), // output[5:0]
.afi_awlock (afi0_awlock), // output[1:0]
.afi_awcache (afi0_awcache), // output[3:0]
.afi_awprot (afi0_awprot), // output[2:0]
.afi_awlen (afi0_awlen), // output[3:0]
.afi_awsize (afi0_awsize), // output[2:0]
.afi_awburst (afi0_awburst), // output[1:0]
.afi_awqos (afi0_awqos), // output[3:0]
.afi_wdata (afi0_wdata), // output[63:0]
.afi_wvalid (afi0_wvalid), // output
.afi_wready (afi0_wready), // input
.afi_wid (afi0_wid), // output[5:0]
.afi_wlast (afi0_wlast), // output
.afi_wstrb (afi0_wstrb), // output[7:0]
.afi_bvalid (afi0_bvalid), // input
.afi_bready (afi0_bready), // output
.afi_bid (afi0_bid), // input[5:0]
.afi_bresp (afi0_bresp), // input[1:0]
.afi_wcount (afi0_wcount), // input[7:0]
.afi_wacount (afi0_wacount), // input[5:0]
.afi_wrissuecap1en (afi0_wrissuecap1en), // output
.afi_araddr (afi0_araddr), // output[31:0]
.afi_arvalid (afi0_arvalid), // output
.afi_arready (afi0_arready), // input
.afi_arid (afi0_arid), // output[5:0]
.afi_arlock (afi0_arlock), // output[1:0]
.afi_arcache (afi0_arcache), // output[3:0]
.afi_arprot (afi0_arprot), // output[2:0]
.afi_arlen (afi0_arlen), // output[3:0]
.afi_arsize (afi0_arsize), // output[2:0]
.afi_arburst (afi0_arburst), // output[1:0]
.afi_arqos (afi0_arqos), // output[3:0]
.afi_rdata (afi0_rdata), // input[63:0]
.afi_rvalid (afi0_rvalid), // input
.afi_rready (afi0_rready), // output
.afi_rid (afi0_rid), // input[5:0]
.afi_rlast (afi0_rlast), // input
.afi_rresp (afi0_rresp), // input[2:0]
.afi_rcount (afi0_rcount), // input[7:0]
.afi_racount (afi0_racount), // input[2:0]
.afi_rdissuecap1en (afi0_rdissuecap1en) // output
);
// SAXIGP0 signals (read unused) (for the histograms)
......@@ -1458,11 +1453,15 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD)
) sensors393_i (
.rst (axi_rst), // input
// .rst (axi_rst), // input
.pclk (pclk), // input
.pclk2x (pclk2x), // input
.ref_clk (ref_clk), // input
.dly_rst (axi_rst), // input
.dly_rst (idelay_ctrl_reset), // input
.mrst (mrst), // input
.prst (prst), // input
.arst (arst), // input
.mclk (mclk), // input
.cmd_ad_in (cmd_sensor_ad), // input[7:0]
.cmd_stb_in (cmd_sensor_stb), // input
......@@ -1575,10 +1574,6 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
wire [ 5:0] afi2_wacount; // input[5:0]
wire afi2_wrissuecap1en; // output
compressor393 #(
.CMPRS_NUM_AFI_CHN (CMPRS_NUM_AFI_CHN),
.CMPRS_GROUP_ADDR (CMPRS_GROUP_ADDR),
......@@ -1660,10 +1655,14 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.CMPRS_AFIMUX_CYCBITS (CMPRS_AFIMUX_CYCBITS),
.AFI_MUX_BUF_LATENCY (AFI_MUX_BUF_LATENCY)
) compressor393_i (
.rst (axi_rst), // input
// .rst (axi_rst), // input
.xclk (xclk), // input
.xclk2x (xclk2x), // input
.mclk (mclk), // input
.mrst (mrst), // input
.xrst (xrst), // input
.hrst (hrst), // input
.cmd_ad (cmd_compressor_ad), // input[7:0]
.cmd_stb (cmd_compressor_stb), // input
.status_ad (status_compressor_ad), // output[7:0]
......@@ -1760,8 +1759,9 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.GPIO_N (GPIO_N),
.GPIO_PORTEN (GPIO_PORTEN)
) gpio393_i (
.rst (axi_rst), // input
// .rst (axi_rst), // input
.mclk (mclk), // input
.mrst (mrst), // input
.cmd_ad (cmd_gpio_ad), // input[7:0]
.cmd_stb (cmd_gpio_stb), // input
.status_ad (status_gpio_ad), // output[7:0]
......@@ -1777,7 +1777,6 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.dc_en (gpio_logger_en) // input[9:0]
);
/* Instance template for module timing393 */
timing393 #(
.RTC_ADDR (RTC_ADDR),
.CAMSYNC_ADDR (CAMSYNC_ADDR),
......@@ -1807,9 +1806,11 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.RTC_SET_CORR (RTC_SET_CORR),
.RTC_SET_STATUS (RTC_SET_STATUS)
) timing393_i (
.rst (axi_rst), // input
// .rst (axi_rst), // input
.mclk (mclk), // input
.pclk (camsync_clk), // global clock used for external synchronization. 96MHz in x353. Make it independent
.mrst (mrst), // input
.prst (crst), // input
.refclk (time_ref), // RTC reference: integer number of microseconds, less than mclk/2. Not a global clock
.cmd_ad (cmd_timing_ad), // input[7:0]
.cmd_stb (cmd_timing_stb), // input
......@@ -1837,9 +1838,10 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.ts_stb_chn3 (ts_pre_stb[3]), // output
.ts_data_chn3 (ts_data[3 * 8 +: 8]), // output[7:0]
.lclk (logger_clk), // input global clock, common with the logger (use 100 MHz?)
.ts_logger_snap (logger_snap), // input
.ts_logger_stb (ts_pre_logger_stb), // output
.ts_logger_data (ts_logegr_data) // output[7:0]
.lrst (lrst), // input
.ts_logger_snap (logger_snap), // input
.ts_logger_stb (ts_pre_logger_stb), // output
.ts_logger_data (ts_logegr_data) // output[7:0]
);
event_logger #(
......@@ -1869,9 +1871,11 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.LOGGER_CONF_DBG_BITS (LOGGER_CONF_DBG_BITS),
.GPIO_N (GPIO_N)
) event_logger_i (
.rst (axi_rst), // input
// .rst (axi_rst), // input
.mclk (mclk), // input
.xclk (logger_clk), // input
.mrst (mrst), // input
.xrst (lrst), // input
.cmd_ad (cmd_logger_ad), // input[7:0]
.cmd_stb (cmd_logger_stb), // input
.status_ad (status_logger_ad), // output[7:0]
......@@ -1928,9 +1932,11 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.MULT_SAXI_ADV_WR (MULT_SAXI_ADV_WR),
.MULT_SAXI_ADV_RD (MULT_SAXI_ADV_RD)
) mult_saxi_wr_i (
.rst (axi_rst), // input
// .rst (axi_rst), // input
.mclk (mclk), // input
.aclk (saxi1_aclk), // input
.aclk (saxi1_aclk), // input == hclk
.mrst (mrst), // input
.arst (hrst), // input
.cmd_ad (cmd_saxi1wr_ad), // input[7:0]
.cmd_stb (cmd_saxi1wr_stb), // input
.status_ad (status_saxi1wr_ad), // output[7:0]
......@@ -2033,8 +2039,9 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.FFCLK1_IFD_DELAY_VALUE (FFCLK1_IFD_DELAY_VALUE),
.FFCLK1_IOSTANDARD (FFCLK1_IOSTANDARD)
) clocks393_i (
.rst (axi_rst), // input
// .rst (axi_rst), // input
.mclk (mclk), // input
.mrst (mrst),
.cmd_ad (cmd_clocks_ad), // input[7:0]
.cmd_stb (cmd_clocks_stb), // input
.status_ad (status_clocks_ad), // output[7:0]
......@@ -2057,11 +2064,22 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.extra_status ({1'b0,idelay_ctrl_rdy}) // input[1:0]
);
sync_resets #(
.WIDTH(7),
.REGISTER(4),
.LATE_MASTER(1)
) sync_resets_i (
.arst(), // input
.mlocked(mcntrl_locked), // input
.clk({hclk, axi_aclk, logger_clk, camsync_clk, xclk, pclk, mclk}), // input[0:0]
.rst({hrst, arst, lrst, crst, xrst, prst, mrst}) // output[0:0]
);
axibram_write #(
.ADDRESS_BITS(AXI_WR_ADDR_BITS)
) axibram_write_i ( //SuppressThisWarning ISExst Output port <bram_wstb> of the instance <axibram_write_i> is unconnected or connected to loadless signal.
.aclk (axi_aclk), // input
.rst (axi_rst), // input
.arst (arst), // input
.awaddr (maxi0_awaddr[31:0]), // input[31:0] // SuppressThisWarning VivadoSynthesis: [Synth 8-3295] tying undriven pin #axibram_write_i:awaddr[31:16,1:0] to constant 0
.awvalid (maxi0_awvalid), // input
.awready (maxi0_awready), // output
......@@ -2115,7 +2133,8 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.ADDRESS_BITS(AXI_RD_ADDR_BITS)
) axibram_read_i ( //SuppressThisWarning ISExst Output port <bram_rclk> of the instance <axibram_read_i> is unconnected or connected to loadless signal.
.aclk (axi_aclk), // input
.rst (axi_rst), // input
.arst (arst),
// .rst (axi_rst), // input
.araddr (maxi0_araddr[31:0]), // input[31:0] // SuppressThisWarning VivadoSynthesis: [Synth 8-3295] tying undriven pin #axibram_read_i:araddr[31:16,1:0] to constant 0
.arvalid (maxi0_arvalid), // input
.arready (maxi0_arready), // output
......
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