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Commit b721ae66 authored by Andrey Filippov's avatar Andrey Filippov
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axi/axibram_read.v
View file @ b721ae66
......@@ -25,20 +25,16 @@ module axibram_read #(
parameter ADDRESS_BITS = 10 // number of memory address bits
)(
input aclk, // clock - should be buffered
// input aresetn, // reset, active low
input rst, // reset, active high
// input rst, // reset, active high
input arst, // @posedge aclk sync reset, active high
// AXI Read Address
input [31:0] araddr, // ARADDR[31:0], input
input arvalid, // ARVALID, input
output arready, // ARREADY, output
input [11:0] arid, // ARID[11:0], input
// input [ 1:0] arlock, // ARLOCK[1:0], input
// input [ 3:0] archache,// ARCACHE[3:0], input
// input [ 2:0] arprot, // ARPROT[2:0], input
input [ 3:0] arlen, // ARLEN[3:0], input
input [ 1:0] arsize, // ARSIZE[1:0], input
input [ 1:0] arburst, // ARBURST[1:0], input
// input [ 3:0] adqos, // ARQOS[3:0], input
// AXI Read Data
output [31:0] rdata, // RDATA[31:0], output
output reg rvalid, // RVALID, output
......@@ -145,30 +141,30 @@ module axibram_read #(
assign rdata[31:0] = bram_rdata; // data out
always @ (posedge aclk or posedge rst) begin
always @ (posedge aclk) begin
`ifdef USE_SHORT_REN_REGEN
if (rst) bram_regen_r <= 0;
if (arst) bram_regen_r <= 0;
else bram_regen_r <= bram_ren;
`endif
if (rst) pre_last_in_burst_r <= 0;
if (arst) pre_last_in_burst_r <= 0;
// else if (start_read_burst_w) pre_last_in_burst_r <= (read_left==4'b0);
else if (bram_reg_re_w) pre_last_in_burst_r <= (read_left==4'b0);
if (rst) rburst[1:0] <= 0;
if (arst) rburst[1:0] <= 0;
else if (start_read_burst_w) rburst[1:0] <= arburst_out[1:0];
if (rst) rlen[3:0] <= 0;
if (arst) rlen[3:0] <= 0;
else if (start_read_burst_w) rlen[3:0] <= arlen_out[3:0];
if (rst) read_in_progress <= 0;
if (arst) read_in_progress <= 0;
else read_in_progress <= read_in_progress_w;
if (rst) read_in_progress_d <= 0;
if (arst) read_in_progress_d <= 0;
// else read_in_progress_d <= read_in_progress_d_w;
else if (bram_reg_re_w) read_in_progress_d <= read_in_progress_d_w;
if (rst) read_in_progress_or <= 0;
if (arst) read_in_progress_or <= 0;
// else read_in_progress_or <= read_in_progress_d_w || read_in_progress_w;
// else if (bram_reg_re_w) read_in_progress_or <= read_in_progress_d_w || read_in_progress_w;
// FIXME:
......@@ -177,22 +173,23 @@ module axibram_read #(
// reg read_in_progress_d=0; // delayed by one active cycle (not skipped)
// reg read_in_progress_or=0; // read_in_progress || read_in_progress_d
if (rst) read_left <= 0;
if (arst) read_left <= 0;
else if (start_read_burst_w) read_left <= arlen_out[3:0]; // precedence over inc
else if (bram_reg_re_w) read_left <= read_left-1; //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target.
if (rst) read_address <= {ADDRESS_BITS{1'b0}};
if (arst) read_address <= {ADDRESS_BITS{1'b0}};
else if (start_read_burst_w) read_address <= araddr_out[ADDRESS_BITS-1:0]; // precedence over inc
else if (bram_reg_re_w) read_address <= next_rd_address_w;
if (rst) rvalid <= 1'b0;
if (arst) rvalid <= 1'b0;
else if (bram_reg_re_w && read_in_progress_d) rvalid <= 1'b1;
else if (rready) rvalid <= 1'b0;
if (rst) rlast <= 1'b0;
if (arst) rlast <= 1'b0;
else if (last_in_burst_d_w) rlast <= 1'b1;
else if (rready) rlast <= 1'b0;
end
always @ (posedge aclk) begin //SuppressThisWarning ISExst Assignment to bram_reg_re_0 ignored, since the identifier is never used
// bram_reg_re_0 <= read_in_progress_w && !pre_rvalid_w;
......@@ -240,9 +237,9 @@ module axibram_read #(
fifo_same_clock #( .DATA_WIDTH(ADDRESS_BITS+20),.DATA_DEPTH(4))
raddr_i (
.rst(rst),
.rst(1'b0),
.clk(aclk),
.sync_rst(1'b0), // input
.sync_rst(arst),
.we(arvalid && arready),
.re(start_read_burst_w),
.data_in({arid[11:0], arburst[1:0],arsize[1:0],arlen[3:0],araddr[ADDRESS_BITS+1:2]}),
......
axi/axibram_write.v
View file @ b721ae66
......@@ -26,21 +26,16 @@ module axibram_write #(
parameter ADDRESS_BITS = 10 // number of memory address bits
)(
input aclk, // clock - should be buffered
// input aresetn, // reset, active low
input rst, // reset, active highw
input arst, // @aclk sync reset, active high
// AXI Write Address
input [31:0] awaddr, // AWADDR[31:0], input
input awvalid, // AWVALID, input
output awready, // AWREADY, output
input [11:0] awid, // AWID[11:0], input
// input [ 1:0] awlock, // AWLOCK[1:0], input
// input [ 3:0] awcache, // AWCACHE[3:0], input
// input [ 2:0] awprot, // AWPROT[2:0], input
input [ 3:0] awlen, // AWLEN[3:0], input
input [ 1:0] awsize, // AWSIZE[1:0], input
input [ 1:0] awburst, // AWBURST[1:0], input
// input [ 3:0] awqos, // AWQOS[3:0], input
// AXI PS Master GP0: Write Data
input [31:0] wdata, // WDATA[31:0], input
input wvalid, // WVALID, input
......@@ -141,44 +136,30 @@ module axibram_write #(
assign start_write_burst_w=w_nempty_ready && aw_nempty_ready && (!write_in_progress || (w_nempty_ready && ((write_left[3:0]==4'b0) || wlast_out)));
assign write_in_progress_w=w_nempty_ready && aw_nempty_ready || (write_in_progress && !(w_nempty_ready && ((write_left[3:0]==4'b0) || wlast_out)));
always @ (posedge aclk or posedge rst) begin
if (rst) wburst[1:0] <= 0;
always @ (posedge aclk) begin
if (arst) wburst[1:0] <= 0;
else if (start_write_burst_w) wburst[1:0] <= awburst_out[1:0];
if (rst) wlen[3:0] <= 0;
if (arst) wlen[3:0] <= 0;
else if (start_write_burst_w) wlen[3:0] <= awlen_out[3:0];
if (rst) write_in_progress <= 0;
else write_in_progress <= write_in_progress_w;
if (arst) write_in_progress <= 0;
else write_in_progress <= write_in_progress_w;
if (rst) write_left <= 0;
if (arst) write_left <= 0;
else if (start_write_burst_w) write_left <= awlen_out[3:0]; // precedence over inc
else if (bram_we_w) write_left <= write_left-1; //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target.
if (rst) write_address <= {ADDRESS_BITS{1'b0}};
if (arst) write_address <= {ADDRESS_BITS{1'b0}};
else if (start_write_burst_w) write_address <= awaddr_out[ADDRESS_BITS-1:0]; // precedence over inc
else if (bram_we_w) write_address <= next_wr_address_w;
if (rst) dev_ready_r <= 1'b0;
else dev_ready_r <= dev_ready;
if (arst) dev_ready_r <= 1'b0;
else dev_ready_r <= dev_ready;
end
// **** Write response channel ****
wire [ 1:0] bresp_in;
assign bresp_in=2'b0;
/*
output bvalid, // BVALID, output
input bready, // BREADY, input
output [11:0] bid, // BID[11:0], output
output [ 1:0] bresp // BRESP[1:0], output
*/
/*
reg bram_reg_re_r;
always @ (posedge aclk) begin
bram_reg_re_r <= bram_reg_re_w;
end
*/
// external memory interface (write only)
assign pre_awaddr=awaddr_out[ADDRESS_BITS-1:0];
......@@ -199,9 +180,9 @@ module axibram_write #(
`endif
fifo_same_clock #( .DATA_WIDTH(20+ADDRESS_BITS),.DATA_DEPTH(4))
waddr_i (
.rst (rst),
.rst (1'b0), //rst),
.clk (aclk),
.sync_rst (1'b0),
.sync_rst (arst),
.we (awvalid && awready),
.re (start_write_burst_w),
.data_in ({awid[11:0], awburst[1:0],awsize[1:0],awlen[3:0],awaddr[ADDRESS_BITS+1:2]}),
......@@ -219,9 +200,9 @@ fifo_same_clock #( .DATA_WIDTH(20+ADDRESS_BITS),.DATA_DEPTH(4))
);
fifo_same_clock #( .DATA_WIDTH(49),.DATA_DEPTH(4))
wdata_i (
.rst(rst),
.rst(1'b0), //rst),
.clk(aclk),
.sync_rst (1'b0),
.sync_rst (arst),
.we(wvalid && wready),
.re(bram_we_w), //start_write_burst_w), // wrong
.data_in({wid[11:0],wlast,wstb[3:0],wdata[31:0]}),
......@@ -241,16 +222,16 @@ fifo_same_clock #( .DATA_WIDTH(49),.DATA_DEPTH(4))
reg was_bresp_re=0;
wire bresp_re;
assign bresp_re=bready && bvalid && !was_bresp_re;
always @ (posedge rst or posedge aclk) begin
if (rst) was_bresp_re<=0;
else was_bresp_re <= bresp_re;
always @ (posedge aclk) begin
if (arst) was_bresp_re<=0;
else was_bresp_re <= bresp_re;
end
fifo_same_clock #( .DATA_WIDTH(14),.DATA_DEPTH(4))
wresp_i (
.rst(rst),
.rst(1'b0), //rst),
.clk(aclk),
.sync_rst (1'b0),
.sync_rst (arst),
.we(bram_we_w &&((write_left[3:0]==4'b0) || wlast_out)), // added ((write_left[3:0]==4'b0) || wlast_out) - only last wrtite -> bresp
// .re(bready && bvalid),
.re(bresp_re), // not allowing RE next cycle after bvalid
......
axi/cmprs_afi_mux.v
View file @ b721ae66
......@@ -34,9 +34,11 @@ module cmprs_afi_mux#(
parameter CMPRS_AFIMUX_CYCBITS = 3,
parameter AFI_MUX_BUF_LATENCY = 2 // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
)(
input rst,
// input rst,
input mclk, // for command/status
input hclk, // global clock to run axi_hp @ 150MHz, shared by all compressor channels
input mrst, // @posedge mclk, sync reset
input hrst, // @posedge xclk, sync reset
// programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
......@@ -386,8 +388,9 @@ module cmprs_afi_mux#(
.ADDR_WIDTH (4),
.DATA_WIDTH (32)
) cmd_deser_32bit_i (
.rst (rst), // input
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[3:0]
......@@ -436,9 +439,11 @@ module cmprs_afi_mux#(
.CMPRS_AFIMUX_WIDTH(CMPRS_AFIMUX_WIDTH),
.CMPRS_AFIMUX_CYCBITS(CMPRS_AFIMUX_CYCBITS)
) cmprs_afi_mux_status_i (
.rst (rst), // input
// .rst (rst), // input
.hclk (hclk), // input
.mclk (mclk), // input
.mrst (mrst), // input
.hrst (hrst), // input
.cmd_data (cmd_data[15:0]), // input[15:0]
.cmd_a (cmd_a[1:0]), // input[1:0]
.status_we (cmd_we_status_w), // input
......
axi/cmprs_afi_mux_status.v
View file @ b721ae66
......@@ -29,9 +29,11 @@ module cmprs_afi_mux_status #(
parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26)
parameter CMPRS_AFIMUX_CYCBITS = 3
) (
input rst,
// input rst,
input hclk, // global clock to run axi_hp @ 150MHz, shared by all compressor channels
input mclk, // for command/status
input mrst, // @posedge mclk, sync reset
input hrst, // @posedge xclk, sync reset
// mclk domain
input [15:0] cmd_data, //
input [ 1:0] cmd_a, //
......@@ -100,11 +102,12 @@ module cmprs_afi_mux_status #(
end
pulse_cross_clock mode_we_hclk_i (.rst(rst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(mode_we), .out_pulse(mode_we_hclk),.busy());
pulse_cross_clock stb_mclk_i (.rst(rst), .src_clk(hclk), .dst_clk(mclk), .in_pulse(stb_r), .out_pulse(stb_mclk), .busy());
pulse_cross_clock mode_we_hclk_i (.rst(mrst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(mode_we), .out_pulse(mode_we_hclk),.busy());
pulse_cross_clock stb_mclk_i (.rst(hrst), .src_clk(hclk), .dst_clk(mclk), .in_pulse(stb_r), .out_pulse(stb_mclk), .busy());
status_router4 status_router4_i (
.rst (rst), // input
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.db_in0 (ad[0 * 8 +: 8]), // input[7:0]
.rq_in0 (rq[0]), // input
.start_in0 (start[0]), // output
......@@ -127,8 +130,9 @@ module cmprs_afi_mux_status #(
.STATUS_REG_ADDR (CMPRS_AFIMUX_STATUS_REG_ADDR+0),
.PAYLOAD_BITS (CMPRS_AFIMUX_WIDTH)
) status_generate0_i (
.rst (rst), // input
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (status_we && (cmd_a==0)), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_data[0 * CMPRS_AFIMUX_WIDTH +: CMPRS_AFIMUX_WIDTH]), // input[25:0]
......@@ -141,8 +145,9 @@ module cmprs_afi_mux_status #(
.STATUS_REG_ADDR (CMPRS_AFIMUX_STATUS_REG_ADDR+0),
.PAYLOAD_BITS (CMPRS_AFIMUX_WIDTH)
) status_generate1_i (
.rst (rst), // input
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (status_we && (cmd_a==1)), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_data[1 * CMPRS_AFIMUX_WIDTH +: CMPRS_AFIMUX_WIDTH]), // input[25:0]
......@@ -155,8 +160,9 @@ module cmprs_afi_mux_status #(
.STATUS_REG_ADDR (CMPRS_AFIMUX_STATUS_REG_ADDR+0),
.PAYLOAD_BITS (CMPRS_AFIMUX_WIDTH)
) status_generate2_i (
.rst (rst), // input
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (status_we && (cmd_a==2)), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_data[2 * CMPRS_AFIMUX_WIDTH +: CMPRS_AFIMUX_WIDTH]), // input[25:0]
......@@ -169,8 +175,9 @@ module cmprs_afi_mux_status #(
.STATUS_REG_ADDR (CMPRS_AFIMUX_STATUS_REG_ADDR+0),
.PAYLOAD_BITS (CMPRS_AFIMUX_WIDTH)
) status_generate3_i (
.rst (rst), // input
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (status_we && (cmd_a==3)), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_data[3 * CMPRS_AFIMUX_WIDTH +: CMPRS_AFIMUX_WIDTH]), // input[25:0]
......
axi/histogram_saxi.v
View file @ b721ae66
......@@ -37,9 +37,12 @@ module histogram_saxi#(
// parameter HIST_SAXI_STATUS_REG = 'h34,
parameter NUM_FRAME_BITS = 4 // number of bits use for frame number
)(
input rst,
// input rst,
input mclk, // for command/status
input aclk, // global clock to run s_axi (@150MHz?)
input mrst, // @posedge mclk, sync reset
input arst, // @posedge aclk, sync reset
// sensor 0, data valid @posedge mclk
input [NUM_FRAME_BITS-1:0] frame0, // frame number for which the histogram is provided
input hist_request0, // request to transfer a burst
......@@ -248,8 +251,8 @@ module histogram_saxi#(
assign page_sent_aclk = block_run[1] && !block_run[0];
// command interface
always @(posedge rst or posedge mclk) begin
if (rst) mode <= 0;
always @(posedge mclk) begin
if (mrst) mode <= 0;
else if (we_mode) mode <= cmd_data[HIST_SAXI_MODE_WIDTH-1:0];
end
always @(posedge mclk) begin
......@@ -357,7 +360,7 @@ module histogram_saxi#(
pulse_cross_clock pulse_cross_clock_page_sent_i (
.rst (rst), // input
.rst (arst), // input
.src_clk (aclk), // input
.dst_clk (mclk), // input
.in_pulse (page_sent_aclk), // input
......@@ -365,7 +368,7 @@ module histogram_saxi#(
.busy() // output
);
pulse_cross_clock pulse_cross_clock_page_written_aclk_i (
.rst (rst), // input
.rst (mrst), // input
.src_clk (mclk), // input
.dst_clk (aclk), // input
.in_pulse (burst_done_w), // input
......@@ -384,12 +387,13 @@ module histogram_saxi#(
.ADDR2 (0),
.ADDR_MASK2 (0)
) cmd_deser_sens_i2c_i (
.rst (rst), // input
.clk (mclk), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_wa), // output[3:0]
.data (cmd_data), // output[31:0]
.rst (1'b0), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_wa), // output[3:0]
.data (cmd_data), // output[31:0]
.we ({we_mode,we_addr}) // output
);
......@@ -399,31 +403,32 @@ module histogram_saxi#(
.LOG2WIDTH_RD(5),
.DUMMY(0)
) ram_var_w_var_r_i (
.rclk (aclk), // input
.raddr ({page_rd[1:0],page_ra[7:0]}), // input[9:0]
.ren (buf_re[0]), // input
.regen (buf_re[1]), // input
.data_out (inter_buf_data), // output[31:0]
.wclk (mclk), // input
.rclk (aclk), // input
.raddr ({page_rd[1:0],page_ra[7:0]}), // input[9:0]
.ren (buf_re[0]), // input
.regen (buf_re[1]), // input
.data_out (inter_buf_data), // output[31:0]
.wclk (mclk), // input
.waddr ({page_wr[1:0], page_wa[7:0]}), // input[9:0]
.we (dav_r), // input
.web (8'hff), // input[7:0]
.data_in (din_r) // input[31:0]
.we (dav_r), // input
.web (8'hff), // input[7:0]
.data_in (din_r) // input[31:0]
);
// Small extra FIFO to tolerate ram_var_w_var_r latency
fifo_same_clock #(
.DATA_WIDTH(32),
.DATA_DEPTH(4)
) fifo_same_clock_i (
.rst (rst), // input
.clk (aclk), // input
.sync_rst (!en_aclk), // input
.we (buf_re[2]), // input
.re (fifo_re), // input
.rst (1'b0), // input
.clk (aclk), // input
.sync_rst (arst), // input
.sync_rst (!en_aclk), // input
.we (buf_re[2]), // input
.re (fifo_re), // input
.data_in (inter_buf_data), // input[31:0]
.data_out (saxi_wdata), // output[31:0]
.nempty (fifo_nempty), // output
.half_full (fifo_half_full) // output reg
.data_out (saxi_wdata), // output[31:0]
.nempty (fifo_nempty), // output
.half_full (fifo_half_full) // output reg
);
endmodule
axi/membridge.v
View file @ b721ae66
......@@ -37,9 +37,12 @@ module membridge#(
// ,parameter MCNTRL_SCANLINE_FRAME_PAGE_RESET= 1'b0 // reset internal page number to zero at the frame start (false - only when hard/soft reset)
)(
input rst,
input mclk, // for command/status
input hclk, // global clock to run axi_hp @ 150MHz
// input rst,
input mrst, // @posedge mclk - sync reset
input hrst, // @posedge hclk - sync reset
input mclk, // for command/status
input hclk, // global clock to run axi_hp @ 150MHz
// programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
......@@ -208,24 +211,24 @@ module membridge#(
width64_minus1_mclk <= width64_mclk-1;
end
always @ (posedge mclk or posedge rst) begin
if (rst) rdwr_en_mclk <= 0;
always @ (posedge mclk) begin
if (mrst) rdwr_en_mclk <= 0;
else if (set_ctrl_w) rdwr_en_mclk <= cmd_data[0];
if (rst) start_mclk <= 0;
else start_mclk <= set_ctrl_w & cmd_data[1];
if (mrst) start_mclk <= 0;
else start_mclk <= set_ctrl_w & cmd_data[1];
if (rst) mode_reg_mclk <= 5'h03;
if (mrst) mode_reg_mclk <= 5'h03;
else if (set_mode_w) mode_reg_mclk <= cmd_data[4:0];
`ifdef MEMBRIDGE_DEBUG_READ
if (rst) debug_aw_mclk <= 0;
if (mrst) debug_aw_mclk <= 0;
else debug_aw_mclk <= set_ctrl_w & cmd_data[2];
if (rst) debug_w_mclk <= 0;
if (mrst) debug_w_mclk <= 0;
else debug_w_mclk <= set_ctrl_w & cmd_data[3];
if (rst) debug_disable_set_mclk <= 0;
if (mrst) debug_disable_set_mclk <= 0;
else debug_disable_set_mclk <= set_ctrl_w & cmd_data[4];
......@@ -286,48 +289,50 @@ module membridge#(
last_addr1k <= size64[28:4] - 1;
end
always @ (posedge hclk or posedge rst) begin
if (rst) rdwr_en <= 0;
else rdwr_en <= rdwr_en_mclk;
always @ (posedge hclk) begin
if (hrst) rdwr_en <= 0;
else rdwr_en <= rdwr_en_mclk;
if (rst) rdwr_start <= 0;
else rdwr_start <= {rdwr_start[1:0],start_hclk};
if (hrst) rdwr_start <= 0;
else rdwr_start <= {rdwr_start[1:0],start_hclk};
if (rst) rd_start <= 0;
else rd_start <= rdwr_start[2] && !wr_mode; // later to enable adders+ to propagate
if (hrst) rd_start <= 0;
else rd_start <= rdwr_start[2] && !wr_mode; // later to enable adders+ to propagate
if (rst) wr_start <= 0;
else wr_start <= rdwr_start[2] && wr_mode;
if (hrst) wr_start <= 0;
else wr_start <= rdwr_start[2] && wr_mode;
page_ready_rd <= page_ready && !wr_mode;
if (rst) rd_id <= 0;
if (hrst) rd_id <= 0;
else if (rd_start) rd_id <= rd_id +1;
if (rst) wr_id <= 0;
if (hrst) wr_id <= 0;
else if (wr_start) wr_id <= wr_id +1;
end
// mclk -> hclk
pulse_cross_clock start_i (.rst(rst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(start_mclk), .out_pulse(start_hclk),.busy());
pulse_cross_clock page_ready_i (.rst(rst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(page_ready_chn), .out_pulse(page_ready),.busy());
pulse_cross_clock frame_done_i (.rst(rst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(frame_done_chn), .out_pulse(frame_done),.busy());
pulse_cross_clock reset_page_wr_i (.rst(rst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(xfer_reset_page_wr), .out_pulse(reset_page_wr),.busy());
pulse_cross_clock start_i (.rst(mrst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(start_mclk), .out_pulse(start_hclk),.busy());
pulse_cross_clock page_ready_i (.rst(mrst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(page_ready_chn), .out_pulse(page_ready),.busy());
pulse_cross_clock frame_done_i (.rst(mrst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(frame_done_chn), .out_pulse(frame_done),.busy());
pulse_cross_clock reset_page_wr_i (.rst(mrst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(xfer_reset_page_wr), .out_pulse(reset_page_wr),.busy());
`ifdef MEMBRIDGE_DEBUG_READ
// mclk -> hclk, debug-only
pulse_cross_clock debug_aw_i (.rst(rst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(debug_aw_mclk), .out_pulse(debug_aw),.busy());
pulse_cross_clock debug_w_i (.rst(rst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(debug_w_mclk), .out_pulse(debug_w), .busy());
pulse_cross_clock debug_disable_set_i(.rst(rst),.src_clk(mclk),.dst_clk(hclk), .in_pulse(debug_disable_set_mclk),.out_pulse(debug_disable_set), .busy());
pulse_cross_clock debug_aw_i (.rst(hrst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(debug_aw_mclk), .out_pulse(debug_aw),.busy());
pulse_cross_clock debug_w_i (.rst(hrst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(debug_w_mclk), .out_pulse(debug_w), .busy());
pulse_cross_clock debug_disable_set_i(.rst(hrst),.src_clk(mclk),.dst_clk(hclk), .in_pulse(debug_disable_set_mclk),.out_pulse(debug_disable_set), .busy());
`endif
// negedge mclk -> hclk (verify clock inversion is absorbed)
pulse_cross_clock reset_page_rd_i (.rst(rst), .src_clk(~mclk),.dst_clk(hclk), .in_pulse(xfer_reset_page_rd), .out_pulse(reset_page_rd),.busy());
reg mrstn = 1;
always @ (negedge mclk) mrstn <= mrst;
pulse_cross_clock reset_page_rd_i (.rst(mrstn), .src_clk(~mclk),.dst_clk(hclk), .in_pulse(xfer_reset_page_rd), .out_pulse(reset_page_rd),.busy());
// hclk -> mclk
pulse_cross_clock next_page_i (.rst(rst), .src_clk(hclk), .dst_clk(mclk), .in_pulse(next_page), .out_pulse(next_page_chn),.busy(busy_next_page));
pulse_cross_clock next_page_i (.rst(hrst), .src_clk(hclk), .dst_clk(mclk), .in_pulse(next_page), .out_pulse(next_page_chn),.busy(busy_next_page));
// Common to both directions
localparam DELAY_ADVANCE_ADDR=3;
......@@ -359,10 +364,9 @@ module membridge#(
assign afi_araddr={axi_addr64,3'b0};
assign left_zero = low4_zero && last_burst;
always @ (posedge hclk or posedge rst) begin
if (rst) advance_rel_addr_d <= 0;
// else if (advance_rel_addr_w) advance_rel_addr_d <= {DELAY_ADVANCE_ADDR{1'b1}};
else advance_rel_addr_d <= {advance_rel_addr_d[DELAY_ADVANCE_ADDR-2:0],advance_rel_addr};
always @ (posedge hclk) begin
if (hrst) advance_rel_addr_d <= 0;
else advance_rel_addr_d <= {advance_rel_addr_d[DELAY_ADVANCE_ADDR-2:0],advance_rel_addr};
end
......@@ -441,31 +445,31 @@ module membridge#(
`endif
assign afi_awvalid=advance_rel_addr && read_started;
always @ (posedge hclk or posedge rst) begin
if (rst) read_busy <= 0;
always @ (posedge hclk) begin
if (hrst) read_busy <= 0;
else if (rd_start) read_busy <= 1;
else if (read_over) read_busy <= 0;
if (rst) read_started <= 0;
if (hrst) read_started <= 0;
else if (!read_busy) read_started <= 0;
else if (wr_mode) read_started <= 0; // just debugging, making sure read is disabled in write mode
else if (page_ready) read_started <= 1; // first page is in the buffer - use it to mask page number comparison
`ifdef MEMBRIDGE_DEBUG_READ
if (rst) debug_aw_allowed <= 0;
if (hrst) debug_aw_allowed <= 0;
else if (!read_busy) debug_aw_allowed <= 0;
else if ( debug_aw && !afi_awvalid) debug_aw_allowed <= debug_aw_allowed + 1;
else if (!debug_aw && afi_awvalid) debug_aw_allowed <= debug_aw_allowed - 1;
if (rst) debug_w_allowed <= 0;
if (hrst) debug_w_allowed <= 0;
else if (!read_busy) debug_w_allowed <= 0;
else if ( debug_w && !(afi_wvalid && afi_wlast)) debug_w_allowed <= debug_w_allowed + 1;
else if (!debug_w && (afi_wvalid && afi_wlast)) debug_w_allowed <= debug_w_allowed - 1;
if (rst) debug_disable <= 0;
if (hrst) debug_disable <= 0;
else if (!read_busy) debug_disable <= 0;
else if (debug_disable_set) debug_disable <= 1;
`endif
......@@ -473,36 +477,34 @@ module membridge#(
afi_bvalid_r <=afi_bvalid;
if (rst) wresp_conf <= 0;
if (hrst) wresp_conf <= 0;
else if (!read_busy) wresp_conf <= 0;
else if (afi_bvalid_r) wresp_conf <= wresp_conf +1;
read_over <= left_zero && (axi_wr_pending == 0) && read_started;
// read_over <= ((left_zero && (axi_wr_pending == 0)) || frame_done) && read_started ; // WRONG, just for debugging
// else if (frame_done) read_busy <= 0;
if (rst) read_page <= 0;
if (hrst) read_page <= 0;
else if (reset_page_rd) read_page <= 0;
else if (next_page_rd_w) read_page <= read_page + 1;
if (rst) read_pages_ready <= 0;
if (hrst) read_pages_ready <= 0;
else if (!read_busy) read_pages_ready <= 0;
else if ( page_ready_rd && !next_page_rd_w) read_pages_ready <= read_pages_ready +1;
else if (!page_ready_rd && next_page_rd_w) read_pages_ready <= read_pages_ready -1;
if (rst) afi_wd_safe_not_full <= 0;
else afi_wd_safe_not_full <= rdwr_en && (!afi_wcount[7] && !(&afi_wcount[6:3]));
if (hrst) afi_wd_safe_not_full <= 0;
else afi_wd_safe_not_full <= rdwr_en && (!afi_wcount[7] && !(&afi_wcount[6:3]));
if (rst) afi_wa_safe_not_full <= 0;
else afi_wa_safe_not_full <= rdwr_en && (!afi_wacount[5] && !(&afi_wacount[4:2]));
if (hrst) afi_wa_safe_not_full <= 0;
else afi_wa_safe_not_full <= rdwr_en && (!afi_wacount[5] && !(&afi_wacount[4:2]));
if (rst) busy <= 0;
else busy <= read_busy || write_busy;
if (hrst) busy <= 0;
else busy <= read_busy || write_busy;
if (rst) pre_done <= 0; // delay done to turn on same time busy is off
if (hrst) pre_done <= 0; // delay done to turn on same time busy is off
else pre_done <= (write_busy && frame_done) || (read_busy && read_over);
if (rst) done <= 0;
if (hrst) done <= 0;
else if (!rdwr_en) done <= 0; // disabling when idle will reset done
else if (pre_done) done <= 1;
else if (rdwr_start) done <= 0;
......@@ -586,43 +588,43 @@ module membridge#(
assign afi_rready = bufwr_we[0];
always @ (posedge hclk or posedge rst) begin
if (rst) write_busy <= 0;
always @ (posedge hclk) begin
if (hrst) write_busy <= 0;
else if (wr_start) write_busy <= 1;
else if (!wr_mode) write_busy <= 0; // Just debugging, making sure write mode is disabled in read mode
else if (frame_done) write_busy <= 0;
if (rst) axi_arw_requested <= 0;
if (hrst) axi_arw_requested <= 0;
else if (!write_busy && !read_started) axi_arw_requested <= 0;
else if (advance_rel_addr) axi_arw_requested <= axi_arw_requested + afi_len_plus1;