Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
X
x393
Project
Project
Details
Activity
Releases
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Commits
Open sidebar
Elphel
x393
Commits
944ff196
Commit
944ff196
authored
Dec 22, 2015
by
Andrey Filippov
Browse files
Options
Browse Files
Download
Plain Diff
Merge branch 'serial-sensors' to master
parents
8af3d0c0
2413557f
Changes
42
Expand all
Hide whitespace changes
Inline
Side-by-side
Showing
42 changed files
with
71973 additions
and
70615 deletions
+71973
-70615
.project
.project
+8
-8
cmprs_afi_mux.v
axi/cmprs_afi_mux.v
+19
-7
membridge.v
axi/membridge.v
+2
-1
bit_stuffer_metadata.v
compressor_jp/bit_stuffer_metadata.v
+1
-1
cmprs_pixel_buf_iface.v
compressor_jp/cmprs_pixel_buf_iface.v
+28
-9
csconvert.v
compressor_jp/csconvert.v
+16
-15
huffman_stuffer_meta.v
compressor_jp/huffman_stuffer_meta.v
+5
-0
jp_channel.v
compressor_jp/jp_channel.v
+38
-16
fpga_version.vh
fpga_version.vh
+11
-1
x393_parameters.vh
includes/x393_parameters.vh
+4
-1
x393_simulation_parameters.vh
includes/x393_simulation_parameters.vh
+28
-1
mcntrl393.v
memctrl/mcntrl393.v
+3
-0
mcntrl_buf_rd.v
memctrl/mcntrl_buf_rd.v
+12
-0
mcntrl_ps_pio.v
memctrl/mcntrl_ps_pio.v
+26
-25
x393_mcntrl.pickle
py393/dbg/x393_mcntrl.pickle
+69334
-70148
hargs
py393/hargs
+1
-0
imgsrv.py
py393/imgsrv.py
+166
-0
test_mcntrl.py
py393/test_mcntrl.py
+104
-6
vrlg.py
py393/vrlg.py
+119
-119
x393_axi_control_status.py
py393/x393_axi_control_status.py
+3
-0
x393_cmprs.py
py393/x393_cmprs.py
+16
-11
x393_cmprs_afi.py
py393/x393_cmprs_afi.py
+31
-7
x393_jpeg.py
py393/x393_jpeg.py
+243
-14
x393_mcntrl.py
py393/x393_mcntrl.py
+14
-11
x393_mcntrl_membridge.py
py393/x393_mcntrl_membridge.py
+1
-0
x393_mcntrl_tests.py
py393/x393_mcntrl_tests.py
+4
-0
x393_mcntrl_timing.py
py393/x393_mcntrl_timing.py
+2
-1
x393_sens_cmprs.py
py393/x393_sens_cmprs.py
+637
-78
x393_sensor.py
py393/x393_sensor.py
+170
-14
x393_utils.py
py393/x393_utils.py
+15
-2
sens_10398.v
sensor/sens_10398.v
+22
-4
sens_hispi12l4.v
sensor/sens_hispi12l4.v
+58
-18
sens_hispi_fifo.v
sensor/sens_hispi_fifo.v
+16
-2
sensor_channel.v
sensor/sensor_channel.v
+34
-3
sensors393.v
sensor/sensors393.v
+8
-1
status_read.v
status_read.v
+4
-1
system_defines.vh
system_defines.vh
+2
-1
debug_master.v
util_modules/debug_master.v
+2
-1
resync_data.v
util_modules/resync_data.v
+81
-0
x393.v
x393.v
+4
-1
x393_testbench03.sav
x393_testbench03.sav
+553
-35
x393_testbench03.tf
x393_testbench03.tf
+128
-52
No files found.
.project
View file @
944ff196
...
...
@@ -62,42 +62,42 @@
<link>
<name>
vivado_logs/VivadoBitstream.log
</name>
<type>
1
</type>
<location>
/home/andrey/git/x393/vivado_logs/VivadoBitstream-201511
07204814914
.log
</location>
<location>
/home/andrey/git/x393/vivado_logs/VivadoBitstream-201511
17233913191
.log
</location>
</link>
<link>
<name>
vivado_logs/VivadoOpt.log
</name>
<type>
1
</type>
<location>
/home/andrey/git/x393/vivado_logs/VivadoOpt-201511
07161051349
.log
</location>
<location>
/home/andrey/git/x393/vivado_logs/VivadoOpt-201511
17233913191
.log
</location>
</link>
<link>
<name>
vivado_logs/VivadoOptPhys.log
</name>
<type>
1
</type>
<location>
/home/andrey/git/x393/vivado_logs/VivadoOptPhys-201511
07161322372
.log
</location>
<location>
/home/andrey/git/x393/vivado_logs/VivadoOptPhys-201511
17233913191
.log
</location>
</link>
<link>
<name>
vivado_logs/VivadoOptPower.log
</name>
<type>
1
</type>
<location>
/home/andrey/git/x393/vivado_logs/VivadoOptPower-201511
07161051349
.log
</location>
<location>
/home/andrey/git/x393/vivado_logs/VivadoOptPower-201511
17233913191
.log
</location>
</link>
<link>
<name>
vivado_logs/VivadoPlace.log
</name>
<type>
1
</type>
<location>
/home/andrey/git/x393/vivado_logs/VivadoPlace-201511
07161322372
.log
</location>
<location>
/home/andrey/git/x393/vivado_logs/VivadoPlace-201511
17233913191
.log
</location>
</link>
<link>
<name>
vivado_logs/VivadoRoute.log
</name>
<type>
1
</type>
<location>
/home/andrey/git/x393/vivado_logs/VivadoRoute-201511
07161322372
.log
</location>
<location>
/home/andrey/git/x393/vivado_logs/VivadoRoute-201511
17233913191
.log
</location>
</link>
<link>
<name>
vivado_logs/VivadoSynthesis.log
</name>
<type>
1
</type>
<location>
/home/andrey/git/x393/vivado_logs/VivadoSynthesis-201511
07160339590
.log
</location>
<location>
/home/andrey/git/x393/vivado_logs/VivadoSynthesis-201511
17233307674
.log
</location>
</link>
<link>
<name>
vivado_logs/VivadoTimimgSummaryReportImplemented.log
</name>
<type>
1
</type>
<location>
/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-201511
07204814914
.log
</location>
<location>
/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-201511
17233913191
.log
</location>
</link>
<link>
<name>
vivado_logs/VivadoTimimgSummaryReportSynthesis.log
</name>
...
...
axi/cmprs_afi_mux.v
View file @
944ff196
...
...
@@ -195,11 +195,12 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
// reg [2:0] cur_chn; // 'b0xx - none, 'b1** - ** - channel number (should match fifo_ren*)
reg
[
1
:
0
]
cur_chn
;
// 'b0xx - none, 'b1** - ** - channel number (should match fifo_ren*)
reg
[
31
:
0
]
left_to_eof
;
// number of chunks left to end of frame
reg
[
31
:
0
]
left_to_eof
;
// number of chunks left to end of frame
(one less: 3 means 4 left)
reg
[
3
:
0
]
fifo_flush_d
;
// fifo_flush* delayed by 1 clk (to detect rising edge
reg
[
3
:
0
]
eof_stb
;
// single-cycle pulse after fifo_flush is asserted
// reg [1:0] w64_cnt; // count 64-bit words in a chunk
// adjusted counters used for channel arbitration
// pessimistic FIFO content counter - decrements (form FIFO counter) on FIFO reads, knows nothing of writes
reg
[
35
:
0
]
counts_corr0
;
// registers to hold corrected (decremented currently processed ones if any) fifo count values, MSB - needs flush
reg
[
17
:
0
]
counts_corr1
;
// first arbitration level winning values
reg
[
8
:
0
]
counts_corr2
;
// second arbitration level winning values
...
...
@@ -231,6 +232,8 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
// 3'h4 :
// ({1'b0,left_to_eof[winner2 * 8 +: 2]} + 3'h1);
// Why it has priority for |counts_corr2[7:2] ? If next frame started, it may skip EOF? Or not?
// it is just to pass to a channel, actual transfer size will be decided here (depending on EOF)
wire
[
1
:
0
]
pre_chunk_inc_m1
=
(
|
counts_corr2
[
7
:
2
])
?
// Would like to increment, if not roll-over
2'h3
:
left_to_eof
[
winner2
*
8
+:
2
]
;
...
...
@@ -252,12 +255,15 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
wire
[
26
:
0
]
chunk_ptr_rd
;
wire
[
3
:
0
]
chunk_ptr_ra
;
// If flushing - whatever is left to EOF, otherwise corrected FIFO contents of the winner
wire
[
7
:
0
]
items_left
=
counts_corr2
[
8
]
?
left_to_eof
[(
winner2
*
8
)
+:
8
]
:
counts_corr2
[
7
:
0
]
;
reg
[
5
:
0
]
afi_awid_r
;
// "rollover" - roll over destination memory range
wire
[
2
:
0
]
max_wlen
;
// 0,1,2,3,7 (7 - not limited by rollover) - calculated by cmprs_afi_mux_ptr
wire
[
1
:
0
]
want_wleft32
=
(
|
items_left
[
7
:
2
])
?
2'b11
:
items_left
[
1
:
0
]
;
// want to set wleft[3:2] if not roll-over
// wants to write (want_wleft32+1) 32-byte chunks (4,3,2,1)
wire
[
1
:
0
]
want_wleft32
=
(
|
items_left
[
7
:
2
])
?
2'b11
:
items_left
[
1
:
0
]
;
// want to set wleft[3:2] if not roll-over (actually "3" means 2)
assign
cmd_we_status_w
=
cmd_we
&&
((
cmd_a
&
'hc
)
==
CMPRS_AFIMUX_STATUS_CNTRL
)
;
assign
cmd_we_mode_w
=
cmd_we
&&
(
cmd_a
==
CMPRS_AFIMUX_MODE
)
;
...
...
@@ -366,16 +372,22 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
// TODO: change &w64_cnt[1:0] so left_to_eof[*] will be updated earlier and valid at pre_busy_w
// Done, updating at the first (not last) word of 4
// Now seems that eof_stb[i] & fifo_ren{i} == 0
if
(
eof_stb
[
0
])
left_to_eof
[
0
*
8
+:
8
]
<=
fifo_count0_m1
-
(
fifo_ren0
&
(
&
wleft
[
1
:
0
]))
;
// Seems needs to decrement fifo_count0_m1 regardless of &wleft[1:0] - if started, will eventually decrement
// How to make sure that decremented value always >0?
// if (eof_stb[0]) left_to_eof[0 * 8 +: 8] <= fifo_count0_m1 - (fifo_ren0 & (&wleft[1:0]));
if
(
eof_stb
[
0
])
left_to_eof
[
0
*
8
+:
8
]
<=
fifo_count0_m1
-
fifo_ren0
;
else
if
(
fifo_ren0
&
(
&
wleft
[
1
:
0
]))
left_to_eof
[
0
*
8
+:
8
]
<=
left_to_eof
[
0
*
8
+:
8
]
-
1
;
if
(
eof_stb
[
1
])
left_to_eof
[
1
*
8
+:
8
]
<=
fifo_count1_m1
-
(
fifo_ren1
&
(
&
wleft
[
1
:
0
]))
;
// if (eof_stb[1]) left_to_eof[1 * 8 +: 8] <= fifo_count1_m1 - (fifo_ren1 & (&wleft[1:0]));
if
(
eof_stb
[
1
])
left_to_eof
[
1
*
8
+:
8
]
<=
fifo_count1_m1
-
fifo_ren1
;
else
if
(
fifo_ren1
&
(
&
wleft
[
1
:
0
]))
left_to_eof
[
1
*
8
+:
8
]
<=
left_to_eof
[
1
*
8
+:
8
]
-
1
;
if
(
eof_stb
[
2
])
left_to_eof
[
2
*
8
+:
8
]
<=
fifo_count2_m1
-
(
fifo_ren2
&
(
&
wleft
[
1
:
0
]))
;
// if (eof_stb[2]) left_to_eof[2 * 8 +: 8] <= fifo_count2_m1 - (fifo_ren2 & (&wleft[1:0]));
if
(
eof_stb
[
2
])
left_to_eof
[
2
*
8
+:
8
]
<=
fifo_count2_m1
-
fifo_ren2
;
else
if
(
fifo_ren2
&
(
&
wleft
[
1
:
0
]))
left_to_eof
[
2
*
8
+:
8
]
<=
left_to_eof
[
2
*
8
+:
8
]
-
1
;
if
(
eof_stb
[
3
])
left_to_eof
[
3
*
8
+:
8
]
<=
fifo_count3_m1
-
(
fifo_ren3
&
(
&
wleft
[
1
:
0
]))
;
// if (eof_stb[3]) left_to_eof[3 * 8 +: 8] <= fifo_count3_m1 - (fifo_ren3 & (&wleft[1:0]));
if
(
eof_stb
[
3
])
left_to_eof
[
3
*
8
+:
8
]
<=
fifo_count3_m1
-
fifo_ren3
;
else
if
(
fifo_ren3
&
(
&
wleft
[
1
:
0
]))
left_to_eof
[
3
*
8
+:
8
]
<=
left_to_eof
[
3
*
8
+:
8
]
-
1
;
// Calculate corrected values decrementing currently served channel (if any) values by 1 (latency 1 clk)
...
...
axi/membridge.v
View file @
944ff196
...
...
@@ -748,7 +748,8 @@ wire [63:0] afi_wdata0;
.
ext_raddr
(
{
read_page
,
buf_in_line64
[
6
:
0
]
}
)
,
// input[8:0]
.
ext_rd
(
bufrd_rd
[
0
])
,
// input
.
ext_regen
(
bufrd_rd
[
1
])
,
// input
.
ext_data_out
(
afi_wdata0
)
,
// output[63:0]
.
ext_data_out
(
afi_wdata0
)
,
// output[63:0]
// .emul64 (1'b0), // input Modify buffer addresses (used for JP4 until a 64-wide mode is implemented)
.
wclk
(
!
mclk
)
,
// input
.
wpage_in
(
2'b0
)
,
// input[1:0]
.
wpage_set
(
xfer_reset_page_rd
)
,
// input TODO: Generate @ negedge mclk on frame start
...
...
compressor_jp/bit_stuffer_metadata.v
View file @
944ff196
...
...
@@ -146,7 +146,7 @@ module bit_stuffer_metadata(
// just for testing
`ifdef
DEBUG_RING
assign
dbg_
=
ts_rstb
;
assign
dbg_
ts_rstb
=
ts_rstb
;
assign
dbg_ts_dout
=
ts_dout
;
always
@
(
posedge
xclk
)
begin
...
...
compressor_jp/cmprs_pixel_buf_iface.v
View file @
944ff196
...
...
@@ -67,9 +67,11 @@ module cmprs_pixel_buf_iface #(
// controller this can just be the same as mb_pre_end_in
input
mb_pre_start
,
// 1 clock cycle before stream of addresses to the buffer
input
[
1
:
0
]
start_page
,
// page to read next tile from (or first of several pages)
input
[
6
:
0
]
macroblock_x
,
// macroblock left pixel x relative to a tile (page) Maximal page - 128 bytes wide
input
[
6
:
0
]
macroblock_x
,
// macroblock left pixel x relative to a tile (page) Maximal page - 128 bytes wide.
// valid 3 cycles before mb_pre_start
output
reg
[
7
:
0
]
data_out
,
//
output
pre_first_out
,
// For each macroblock in a frame
output
pre2_first_out
,
// 1 cycle before pre_first_out
output
reg
data_valid
//
)
;
localparam
PERIOD_COLOR18
=
384
;
// >18*18, limited by 6*64 (macroblocks)
...
...
@@ -105,9 +107,14 @@ module cmprs_pixel_buf_iface #(
reg
[
8
:
0
]
period_cntr
;
reg
mb_pre_end_r
;
reg
mb_release_buf_r
;
reg
pre_first_out_r
;
reg
[
CMPRS_BUF_EXTRA_LATENCY
+
2
:
0
]
pre_first_out_r
;
reg
[
2
:
0
]
mb_col_number
;
// number of tile column where macrobloc starts - valid 2 cycles before mb_pre_start
wire
[
9
:
0
]
extra_start_addr_w
=
mb_col_number
*
mb_h_m1
;
//added to mb_start_addr when non-zero column
reg
[
5
:
0
]
extra_start_addr_r
;
// reg [ 5:0] mb_h; // macroblock height (lost MSB - OK)
reg
[
9
:
0
]
mb_start_addr
;
// was macroblock_x, noccrected for multi-column. valid with mb_pre_start
assign
buf_ra
=
bufa_r
;
assign
tile_width_or
=
tile_width
[
1
]
?
(
tile_width
[
0
]
?
0
:
'h40
)
:
(
tile_width
[
0
]
?
'h60
:
'h70
)
;
assign
column_width_or
=
tile_col_width
?
0
:
'h10
;
...
...
@@ -119,22 +126,32 @@ module cmprs_pixel_buf_iface #(
assign
mb_release_buf
=
mb_release_buf_r
;
assign
buf_rd
=
buf_re
[
1
:
0
]
;
// assign data_out = do_r;
assign
pre_first_out
=
pre_first_out_r
;
assign
pre_first_out
=
pre_first_out_r
[
0
]
;
assign
pre2_first_out
=
pre_first_out_r
[
1
]
;
always
@
(
posedge
xclk
)
begin
// mb_h <= mb_h_m1+1; // macroblock height
mb_col_number
<=
{
macroblock_x
[
6
:
5
]
,
tile_col_width
?
1'b0
:
macroblock_x
[
4
]
};
extra_start_addr_r
<=
extra_start_addr_w
[
5
:
0
]
;
mb_start_addr
<=
{
3'b0
,
macroblock_x
}
+
{
extra_start_addr_r
,
4'b0
};
if
(
!
frame_en
)
buf_re
[
0
]
<=
0
;
else
if
(
mb_pre_start
)
buf_re
[
0
]
<=
1'b1
;
else
if
(
addr_run_end
)
buf_re
[
0
]
<=
1'b0
;
if
(
!
frame_en
)
buf_re
[
CMPRS_BUF_EXTRA_LATENCY
+
3
:
1
]
<=
0
;
else
buf_re
[
CMPRS_BUF_EXTRA_LATENCY
+
3
:
1
]
<=
{
buf_re
[
CMPRS_BUF_EXTRA_LATENCY
+
2
:
0
]
};
else
buf_re
[
CMPRS_BUF_EXTRA_LATENCY
+
3
:
1
]
<=
{
buf_re
[
CMPRS_BUF_EXTRA_LATENCY
+
2
:
0
]
};
// Buffer data read:
if
(
buf_re
[
CMPRS_BUF_EXTRA_LATENCY
+
2
])
data_out
<=
buf_di
;
//mb_pre_start
if
(
!
frame_en
)
pre_first_out_r
<=
0
;
else
pre_first_out_r
<=
buf_re
[
CMPRS_BUF_EXTRA_LATENCY
+
1
]
&&
!
buf_re
[
CMPRS_BUF_EXTRA_LATENCY
+
2
]
;
else
pre_first_out_r
<=
{
mb_pre_start
,
pre_first_out_r
[
CMPRS_BUF_EXTRA_LATENCY
+
2
:
1
]
};
// else pre_first_out_r <= buf_re[CMPRS_BUF_EXTRA_LATENCY+1] && ! buf_re[CMPRS_BUF_EXTRA_LATENCY+2];
// if (!frame_en) pre2_first_out <= 0;
// else pre2_first_out <= buf_re[CMPRS_BUF_EXTRA_LATENCY + 0] && ! buf_re[CMPRS_BUF_EXTRA_LATENCY + 1];
if
(
mb_pre_start
)
rows_left
<=
mb_h_m1
;
else
if
(
last_col
)
rows_left
<=
rows_left
-
1
;
...
...
@@ -153,7 +170,8 @@ module cmprs_pixel_buf_iface #(
first_col
<=
(
mb_pre_start
||
(
last_col
&&
!
last_row
))
;
if
(
mb_pre_start
)
row_sa
<=
{
start_page
,
3'b0
,
macroblock_x
};
// if (mb_pre_start) row_sa <= {start_page,3'b0,mb_start_addr}; // macroblock_x};
if
(
mb_pre_start
)
row_sa
<=
{
start_page
,
mb_start_addr
};
// macroblock_x};
else
if
(
first_col
)
row_sa
<=
row_sa
+
(
tile_col_width
?
12'h20
:
12'h10
)
;
if
(
mb_pre_start
)
tile_sa
<=
0
;
...
...
@@ -172,7 +190,8 @@ module cmprs_pixel_buf_iface #(
else
if
(
last_in_tile
)
bufa_r
[
11
:
10
]
<=
bufa_r
[
11
:
10
]
+
1
;
// Most time critical - calculation of the buffer address
if
(
mb_pre_start
)
bufa_r
[
9
:
0
]
<=
{
3'b0
,
macroblock_x
};
// if (mb_pre_start) bufa_r[9:0] <= {3'b0,mb_start_addr}; // macroblock_x};
if
(
mb_pre_start
)
bufa_r
[
9
:
0
]
<=
{
mb_start_addr
};
// macroblock_x};
else
if
(
last_col
)
bufa_r
[
9
:
0
]
<=
row_sa
[
9
:
0
]
;
// 'bx next cycle after AFTER mb_pre_start
else
if
(
last_in_tile
)
bufa_r
[
9
:
0
]
<=
tile_sa
;
else
if
(
buf_re
[
0
])
bufa_r
[
9
:
0
]
<=
bufa_r
[
9
:
0
]
+
{
last_in_col
?
col_inc
[
9
:
4
]
:
6'b0
,
4'b1
};
...
...
compressor_jp/csconvert.v
View file @
944ff196
...
...
@@ -55,7 +55,7 @@ module csconvert#(
input
[
9
:
0
]
m_cr
,
// [9:0] scale for CB - default 0.713 (10'hb6)
input
[
7
:
0
]
mb_din
,
// input bayer data in scanline sequence, GR/BG sequence
input
[
1
:
0
]
bayer_phase
,
input
pre
_first_in
,
// marks the first input pixel
input
pre
2_first_in
,
// marks the first input pixel (2 cycles ahead)
output
reg
[
8
:
0
]
signed_y
,
// - now signed char, -128(black) to +127 (white)
output
reg
[
8
:
0
]
signed_c
,
// new, q is just signed char
...
...
@@ -69,7 +69,7 @@ module csconvert#(
// output reg ccv_out_start, //TODO: adjust to minimal latency?
output
reg
[
7
:
0
]
n000
,
// not clear how they are used, make them just with latency1 from old
output
reg
[
7
:
0
]
n255
)
;
reg
pre_first_in
;
// outputs to be multiplexed:
wire
[
7
:
0
]
conv18_signed_y
,
conv20_signed_y
,
mono16_signed_y
,
jp4_signed_y
;
wire
[
8
:
0
]
jp4diff_signed_y
,
conv18_signed_c
,
conv20_signed_c
;
...
...
@@ -100,7 +100,8 @@ module csconvert#(
reg [5:0] component_firstsS; // first_r this component in a frame (DC absolute, otherwise - difference to previous)
*/
always
@
(
posedge
xclk
)
begin
if
(
pre_first_in
)
begin
pre_first_in
<=
pre2_first_in
;
if
(
pre2_first_in
)
begin
converter_type_r
[
2
:
0
]
<=
converter_type
[
2
:
0
]
;
ignore_color_r
<=
ignore_color
;
// jp4_dc_improved_r <= jp4_dc_improved;
...
...
@@ -116,23 +117,23 @@ module csconvert#(
end
// generate one-hot converter enable
if
(
!
frame_en
)
en_converters
[
CMPRS_COLOR18
]
<=
0
;
else
if
(
pre_first_in
)
en_converters
[
CMPRS_COLOR18
]
<=
converter_type
==
CMPRS_COLOR18
;
if
(
!
frame_en
)
en_converters
[
CMPRS_COLOR18
]
<=
0
;
else
if
(
pre
2
_first_in
)
en_converters
[
CMPRS_COLOR18
]
<=
converter_type
==
CMPRS_COLOR18
;
if
(
!
frame_en
)
en_converters
[
CMPRS_COLOR20
]
<=
0
;
else
if
(
pre_first_in
)
en_converters
[
CMPRS_COLOR20
]
<=
converter_type
==
CMPRS_COLOR20
;
if
(
!
frame_en
)
en_converters
[
CMPRS_COLOR20
]
<=
0
;
else
if
(
pre
2
_first_in
)
en_converters
[
CMPRS_COLOR20
]
<=
converter_type
==
CMPRS_COLOR20
;
if
(
!
frame_en
)
en_converters
[
CMPRS_MONO16
]
<=
0
;
else
if
(
pre_first_in
)
en_converters
[
CMPRS_MONO16
]
<=
converter_type
==
CMPRS_MONO16
;
if
(
!
frame_en
)
en_converters
[
CMPRS_MONO16
]
<=
0
;
else
if
(
pre
2
_first_in
)
en_converters
[
CMPRS_MONO16
]
<=
converter_type
==
CMPRS_MONO16
;
if
(
!
frame_en
)
en_converters
[
CMPRS_JP4
]
<=
0
;
else
if
(
pre_first_in
)
en_converters
[
CMPRS_JP4
]
<=
converter_type
==
CMPRS_JP4
;
if
(
!
frame_en
)
en_converters
[
CMPRS_JP4
]
<=
0
;
else
if
(
pre
2
_first_in
)
en_converters
[
CMPRS_JP4
]
<=
converter_type
==
CMPRS_JP4
;
if
(
!
frame_en
)
en_converters
[
CMPRS_JP4DIFF
]
<=
0
;
else
if
(
pre_first_in
)
en_converters
[
CMPRS_JP4DIFF
]
<=
converter_type
==
CMPRS_JP4DIFF
;
if
(
!
frame_en
)
en_converters
[
CMPRS_JP4DIFF
]
<=
0
;
else
if
(
pre
2
_first_in
)
en_converters
[
CMPRS_JP4DIFF
]
<=
converter_type
==
CMPRS_JP4DIFF
;
if
(
!
frame_en
)
en_converters
[
CMPRS_MONO8
]
<=
0
;
else
if
(
pre_first_in
)
en_converters
[
CMPRS_MONO8
]
<=
converter_type
==
CMPRS_MONO8
;
if
(
!
frame_en
)
en_converters
[
CMPRS_MONO8
]
<=
0
;
else
if
(
pre
2
_first_in
)
en_converters
[
CMPRS_MONO8
]
<=
converter_type
==
CMPRS_MONO8
;
end
...
...
compressor_jp/huffman_stuffer_meta.v
View file @
944ff196
...
...
@@ -161,6 +161,11 @@ module huffman_stuffer_meta(
.
data_out_valid
(
data_out_valid
)
,
// output reg
.
done
(
done
)
,
// output reg
.
running
(
running
)
// output reg
`ifdef
DEBUG_RING
,.
dbg_etrax_dma
(
dbg_etrax_dma
)
,
// output[3:0] reg
.
dbg_ts_rstb
(
dbg_ts_rstb
)
,
// output
.
dbg_ts_dout
(
dbg_ts_dout
)
// output[7:0]
`endif
)
;
endmodule
...
...
compressor_jp/jp_channel.v
View file @
944ff196
...
...
@@ -262,6 +262,7 @@ module jp_channel#(
// signals connecting modules: chn_rd_buf_i and ???:
wire
[
7
:
0
]
mb_data_out
;
// Macroblock data out in scanline order
wire
mb_pre_first_out
;
// Macroblock data out strobe - 1 cycle just before data valid
wire
mb_pre2_first_out
;
// Macroblock data out strobe - 2 cycles just before data valid
// wire mb_data_valid; // Macroblock data out valid
wire
limit_diff
=
1'b1
;
// as in the prototype - just a constant 1
...
...
@@ -376,6 +377,7 @@ module jp_channel#(
// wire flush; // output reg @ negedge xclk2x
wire
last_block
=
0
;
// @negedge xxlk2x - used to copy timestamp in stuffer
wire
stuffer_rdy
=
1
;
// receiver (bit stuffer) is ready to accept data;
wire
xrst2xn
=
xrst
;
`endif
...
...
@@ -418,7 +420,19 @@ module jp_channel#(
reg
[
15
:
0
]
dbg_zds_cntr
;
wire
[
2
:
0
]
dbg_block_mem_wa
;
wire
[
2
:
0
]
dbg_block_mem_wa_save
;
`ifndef
USE_XCLK2X
// temporarily assigning unused debug signals to 0
// assign dbg_add_invalid = 0;
// assign dbg_mb_release_buf = 0;
// assign etrax_dma = 0;
// assign dbg_ts_rstb = 0; // output
// assign dbg_ts_dout = 0; //output [7:0]
assign
dbg_flushing
=
0
;
// still not used in huffman_stuffer_meta
// assign dbg_test_lbw = 0;
// assign dbg_gotLastBlock = 0;
assign
dbg_fifo_or_full
=
0
;
// still not used in huffman_stuffer_meta
`endif
timestamp_to_parallel
dbg_timestamp_to_parallel_i
(
`ifdef
USE_XCLK2X
.
clk
(
~
xclk2x
)
,
// input
...
...
@@ -428,7 +442,7 @@ module jp_channel#(
.
pre_stb
(
dbg_ts_rstb
)
,
// input
.
tdata
(
dbg_ts_dout
)
,
// input[7:0]
.
sec
(
dbg_sec
)
,
// output[31:0] reg
.
usec
(
dbg_usec
)
,
// output[19:0] reg
.
usec
(
dbg_usec
[
19
:
0
]
)
,
// output[19:0] reg
.
done
()
// output
)
;
...
...
@@ -599,22 +613,29 @@ module jp_channel#(
.
start
(
status_start
)
// input
)
;
//hifreq
// Port buffer - TODO: Move to memory controller
// Not needed?
// reg emul64;
// always @ (negedge mclk) begin
// emul64 <= tile_width[1]; // will not work for monochrome (128 pixel wide) - chnge to 64?
// end
mcntrl_buf_rd
#(
.
LOG2WIDTH_RD
(
3
)
// 64 bit external interface
)
chn_rd_buf_i
(
.
ext_clk
(
xclk
)
,
// input
.
ext_raddr
(
buf_ra
)
,
// input[11:0]
.
ext_rd
(
buf_rd
[
0
])
,
// input
.
ext_regen
(
buf_rd
[
1
])
,
// input
.
ext_data_out
(
buf_pxd
)
,
// output[7:0]
.
wclk
(
!
mclk
)
,
// input
.
wpage_in
(
2'b0
)
,
// input[1:0]
.
ext_clk
(
xclk
)
,
// input
.
ext_raddr
(
buf_ra
)
,
// input[11:0]
.
ext_rd
(
buf_rd
[
0
])
,
// input
.
ext_regen
(
buf_rd
[
1
])
,
// input
.
ext_data_out
(
buf_pxd
)
,
// output[7:0]
// .emul64 (1'b0), //emul64), // input Modify buffer addresses (used for JP4 until a 64-wide mode is implemented)
.
wclk
(
!
mclk
)
,
// input
.
wpage_in
(
2'b0
)
,
// input[1:0]
.
wpage_set
(
xfer_reset_page_rd
)
,
// input TODO: Generate @ negedge mclk on frame start
.
page_next
(
buf_wpage_nxt
)
,
// input
.
page
()
,
// output[1:0]
.
we
(
buf_we
)
,
// input
.
data_in
(
buf_din
)
// input[63:0]
.
page_next
(
buf_wpage_nxt
)
,
// input
.
page
()
,
// output[1:0]
.
we
(
buf_we
)
,
// input
.
data_in
(
buf_din
)
// input[63:0]
)
;
cmprs_cmd_decode
#(
...
...
@@ -824,7 +845,8 @@ module jp_channel#(
.
data_out
(
mb_data_out
)
,
// output[7:0] // Macroblock data out in scanline order
.
pre_first_out
(
mb_pre_first_out
)
,
// output // Macroblock data out strobe - 1 cycle just before data valid == old pre_first_pixel?
// .data_valid (mb_data_valid) // output // Macroblock data out valid
.
data_valid
()
// output // Macroblock data out valid Unused
.
pre2_first_out
(
mb_pre2_first_out
)
,
// output reg
.
data_valid
()
// output reg // Macroblock data out valid Unused
)
;
csconvert
#(
...
...
@@ -846,7 +868,7 @@ module jp_channel#(
.
m_cr
(
m_cr
)
,
// input[9:0]
.
mb_din
(
mb_data_out
)
,
// input[7:0]
.
bayer_phase
(
bayer_phase
)
,
// input[1:0]
.
pre
_first_in
(
mb_pre_first_out
)
,
// input
.
pre
2_first_in
(
mb_pre2_first_out
)
,
// input
.
signed_y
(
signed_y
)
,
// output[8:0] reg
.
signed_c
(
signed_c
)
,
// output[8:0] reg
.
yaddrw
(
yaddrw
)
,
// output[7:0] reg
...
...
fpga_version.vh
View file @
944ff196
...
...
@@ -31,8 +31,18 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
parameter FPGA_VERSION = 32'h0393006a; // modified clock generation, trying with HiSPi - 72.77% utilization
parameter FPGA_VERSION = 32'h03930071; // Fixing AXI HP multiplexer xclk -0.083 -1.968 44 / 15163 (77.17%)
// parameter FPGA_VERSION = 32'h03930070; // Fixing HiSPi xclk -0.049 -0.291 17, utilization 15139 (77.04%)
// parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xcl -0.002 -0.004 2, utilization 15144 (77.07 %)
// parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xclk -0.209/-2.744/23, utilization 15127 (76.98%)
// parameter FPGA_VERSION = 32'h0393006e; // Trying lane switch again after bug fix, failing 1 in ddr3_mclk -> ddr3_clk_div by -0.023
// parameter FPGA_VERSION = 32'h0393006d; // -1 with lane switch - does not work
// parameter FPGA_VERSION = 32'h0393006d; // Reversing pixels/lanes order xclk violated -0.154
// parameter FPGA_VERSION = 32'h0393006c; // will try debug for HiSPi. xclk violated by -0.030, slices 15062 (76.65%)
// parameter FPGA_VERSION = 32'h0393006b; // Correcting sensor external clock generation - was wrong division. xclk violated by 0.095 ns
// parameter FPGA_VERSION = 32'h0393006a; // modified clock generation, trying with HiSPi - 72.77% utilization x40..x60
// parameter FPGA_VERSION = 32'h03930069; // modified clock generation, rebuilding for parallel sensors - all met, 71.8% utilization
// Worked OK, but different phase for sensor 0 (all quadrants as 1,3 OK)
// parameter FPGA_VERSION = 32'h03930068; // trying BUFR/FUFIO on all sensors ipclk/ipclk2x
// parameter FPGA_VERSION = 32'h03930067; // removing DUMMY_TO_KEEP, moving IOSTANDARD to HDL code
// parameter FPGA_VERSION = 32'h03930066; // trying just one histogram to watch utilization - with 4 was: Slice 15913 (80.98%), now Slice = 14318 (72.87%)
...
...
includes/x393_parameters.vh
View file @
944ff196
...
...
@@ -598,7 +598,10 @@
parameter HISPI_MMCM1 = "FALSE",
parameter HISPI_MMCM2 = "TRUE",
parameter HISPI_MMCM3 = "FALSE",
parameter HISPI_KEEP_IRST = 5, // number of cycles to keep irst on after release of prst (small number - use 1 hot)
parameter HISPI_WAIT_ALL_LANES = 4'h8, // number of output pixel cycles to wait after the earliest lane
parameter HISPI_FIFO_DEPTH = 4,
parameter HISPI_FIFO_START = 7,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
parameter HISPI_DQS_BIAS = "TRUE",
...
...
includes/x393_simulation_parameters.vh
View file @
944ff196
...
...
@@ -41,7 +41,11 @@
parameter SIMUL_AXI_READ_WIDTH=16,
parameter MEMCLK_PERIOD = 5.0,
parameter FCLK0_PERIOD = 41.667, // 10.417, 24MHz
`ifdef HISPI
parameter FCLK0_PERIOD = 40.91, // 24.444MHz
`else
parameter FCLK0_PERIOD = 41.667, // 24MHz
`endif
parameter FCLK1_PERIOD = 0.0,
// parameter SENSOR12BITS_LLINE = 192, // 1664;// line duration in clocks
...
...
@@ -55,6 +59,29 @@
parameter SENSOR_IMAGE_TYPE1 = "RUN1",
parameter SENSOR_IMAGE_TYPE2 = "NORM", // "RUN1",
parameter SENSOR_IMAGE_TYPE3 = "RUN1",
parameter SIMULATE_CMPRS_CMODE0 = CMPRS_CBIT_CMODE_JPEG18,
parameter SIMULATE_CMPRS_CMODE1 = CMPRS_CBIT_CMODE_JPEG18,
parameter SIMULATE_CMPRS_CMODE2 = CMPRS_CBIT_CMODE_JP4,
parameter SIMULATE_CMPRS_CMODE3 = CMPRS_CBIT_CMODE_JP4,
// CMPRS_CBIT_CMODE_JPEG18, //input [31:0] cmode; // [13:9] color mode:
// parameter CMPRS_CBIT_CMODE_JPEG18 = 4'h0, // color 4:2:0
// parameter CMPRS_CBIT_CMODE_MONO6 = 4'h1, // mono 4:2:0 (6 blocks)
// parameter CMPRS_CBIT_CMODE_JP46 = 4'h2, // jp4, 6 blocks, original
// parameter CMPRS_CBIT_CMODE_JP46DC = 4'h3, // jp4, 6 blocks, dc -improved
// parameter CMPRS_CBIT_CMODE_JPEG20 = 4'h4, // mono, 4 blocks (but still not actual monochrome JPEG as the blocks are scanned in 2x2 macroblocks)
// parameter CMPRS_CBIT_CMODE_JP4 = 4'h5, // jp4, 4 blocks, dc-improved
// parameter CMPRS_CBIT_CMODE_JP4DC = 4'h6, // jp4, 4 blocks, dc-improved
// parameter CMPRS_CBIT_CMODE_JP4DIFF = 4'h7, // jp4, 4 blocks, differential
// parameter CMPRS_CBIT_CMODE_JP4DIFFHDR = 4'h8, // jp4, 4 blocks, differential, hdr
// parameter CMPRS_CBIT_CMODE_JP4DIFFDIV2 = 4'h9, // jp4, 4 blocks, differential, divide by 2
// parameter CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = 4'ha, // jp4, 4 blocks, differential, hdr,divide by 2
// parameter CMPRS_CBIT_CMODE_MONO1 = 4'hb, // mono JPEG (not yet implemented)
// parameter CMPRS_CBIT_CMODE_MONO4 = 4'he, // mono 4 blocks
parameter SENSOR12BITS_NGPL = 8, // bpf to hact
parameter SENSOR12BITS_NVLO = 1, // VACT=0 in video mode (clocks)
//parameter tMD = 14; //
...
...
memctrl/mcntrl393.v
View file @
944ff196
...
...
@@ -947,6 +947,7 @@ module mcntrl393 #(
.
ext_rd
(
buf2rd_rd
)
,
// input
.
ext_regen
(
buf2rd_regen
)
,
// input
.
ext_data_out
(
buf2rd_data
)
,
// output[31:0]
// .emul64 (1'b0), // input Modify buffer addresses (used for JP4 until a 64-wide mode is implemented)
.
wclk
(
!
mclk
)
,
// input
.
wpage_in
(
2'b0
)
,
// input[1:0]
.
wpage_set
(
xfer_reset_page2_rd
)
,
// input TODO: Generate @ negedge mclk on frame start
...
...
@@ -982,6 +983,7 @@ module mcntrl393 #(
.
ext_rd
(
buf3rd_rd
)
,
// input
.
ext_regen
(
buf3rd_regen
)
,
// input
.
ext_data_out
(
buf3rd_data
)
,
// output[31:0]
// .emul64 (1'b0), // input Modify buffer addresses (used for JP4 until a 64-wide mode is implemented)
.
wclk
(
!
mclk
)
,
// input
.
wpage_in
(
2'b0
)
,
// input[1:0]
.
wpage_set
(
xfer_reset_page3_rd
)
,
// input @ negedge mclk
...
...
@@ -1017,6 +1019,7 @@ module mcntrl393 #(
.
ext_rd
(
buf4rd_rd
)
,
// input
.
ext_regen
(
buf4rd_regen
)
,
// input
.
ext_data_out
(
buf4rd_data
)
,
// output[31:0]
// .emul64 (1'b0), // input Modify buffer addresses (used for JP4 until a 64-wide mode is implemented)
.
wclk
(
!
mclk
)
,
// input
.
wpage_in
(
2'b0
)
,
// input[1:0]
.
wpage_set
(
xfer_reset_page4_rd
)
,
// input @ negedge mclk
...
...
memctrl/mcntrl_buf_rd.v
View file @
944ff196
...
...
@@ -43,6 +43,8 @@ module mcntrl_buf_rd #(
input
ext_regen
,
// output register enable
output
[(
1
<<
LOG2WIDTH_RD
)
-
1
:
0
]
ext_data_out
,
// data out
// input emul64, // emulate 64 pixel wide reads with actual 32-wide columns
// in the future - use rd64/wr64 for JP4 mode
input
wclk
,
// !mclk (inverted)
input
[
1
:
0
]
wpage_in
,
// will register to wclk, input OK with mclk
input
wpage_set
,
// set internal write page to wpage_in
...
...
@@ -54,6 +56,9 @@ module mcntrl_buf_rd #(
reg
[
1
:
0
]
page_r
;
reg
[
6
:
0
]
waddr
;
assign
page
=
page_r
;
// wire [4:0] next62_norm = waddr[6:2] + 1;
// wire [4:0] next62_rot = {waddr[2],waddr[6:3]} + 1;
// wire [4:0] next62_emul64 = {next62_rot[3:0],next62_rot[4]};
always
@
(
posedge
wclk
)
begin
if
(
wpage_set
)
page_r
<=
wpage_in
;
...
...
@@ -61,6 +66,13 @@ module mcntrl_buf_rd #(
if
(
page_next
||
wpage_set
)
waddr
<=
0
;
else
if
(
we
)
waddr
<=
waddr
+
1
;
// if (page_next || wpage_set) waddr[1:0] <= 0;
// else if (we) waddr[1:0] <= waddr[1:0] + 1;
// if (page_next || wpage_set) waddr[6:2] <= 0;
// else if (we && (&waddr[1:0])) waddr[6:2] <= emul64 ? next62_emul64 : next62_norm;
end
// ram_512x64w_1kx32r #(
ram_var_w_var_r
#(
...
...
memctrl/mcntrl_ps_pio.v
View file @
944ff196
...
...
@@ -247,35 +247,36 @@ fifo_same_clock #(
mcntrl_buf_rd
#(
.
LOG2WIDTH_RD
(
5
)
)
chn0_buf_i
(
.
ext_clk
(
port0_clk
)
,
// input
.
ext_raddr
(
port0_addr
)
,
// input[9:0]
.
ext_rd
(
port0_re
)
,
// input
.
ext_regen
(
port0_regen
)
,
// input
.
ext_data_out
(
port0_data
)
,
// output[31:0]
.
wclk
(
!
mclk
)
,
// input
.
ext_clk
(
port0_clk
)
,
// input
.
ext_raddr
(
port0_addr
)
,
// input[9:0]
.
ext_rd
(
port0_re
)
,
// input
.
ext_regen
(
port0_regen
)
,
// input
.
ext_data_out
(
port0_data
)
,
// output[31:0]
// .emul64 (1'b0), // input Modify buffer addresses (used for JP4 until a 64-wide mode is implemented)
.
wclk
(
!
mclk
)
,
// input
.
wpage_in
(
page_out_r_negedge
)
,
// page_neg), // input[1:0]
.
wpage_set
(
page_w_set_negedge
)
,
//wpage_set_chn0_neg), // input
.
page_next
(
buf_wpage_nxt
)
,
// input
.
page
()
,
// output[1:0]
.
we
(
buf_wr
)
,
// input
.
data_in
(
buf_wdata
)
// input[63:0]
.
wpage_set
(
page_w_set_negedge
)
,
//
wpage_set_chn0_neg), // input
.
page_next
(
buf_wpage_nxt
)
,
// input
.
page
()
,
// output[1:0]
.
we
(
buf_wr
)
,
// input
.
data_in
(
buf_wdata
)
// input[63:0]
)
;
// Port 1 (write DDR from AXI) buffer
mcntrl_buf_wr
#(
.
LOG2WIDTH_WR
(
5
)
)
chn1_buf_i
(
.
ext_clk
(
port1_clk
)
,
// input
.
ext_waddr
(
port1_addr
)
,
// input[9:0]
.
ext_we
(
port1_we
)
,
// input
.
ext_data_in
(
port1_data
)
,
// input[31:0]
.
rclk
(
mclk
)
,
// input
.
rpage_in
(
page_out_r
)
,
//
page), // input[1:0]
.
rpage_set
(
page_r_set
)
,
// rpage_set_chn1), // input
.
page_next
(
buf_rpage_nxt
)
,
// input
.
page
()
,
// output[1:0]
.
rd
(
buf_rd
)
,
// input
.
data_out
(
buf_rdata
)
// output[63:0]
.
ext_clk
(
port1_clk
)
,
// input
.
ext_waddr
(
port1_addr
)
,
// input[9:0]
.
ext_we
(
port1_we
)
,
// input
.
ext_data_in
(
port1_data
)
,
// input[31:0]
.
rclk
(
mclk
)
,
// input
.
rpage_in
(
page_out_r
)
,
//
page), // input[1:0]
.
rpage_set
(
page_r_set
)
,
// rpage_set_chn1), // input
.
page_next
(
buf_rpage_nxt
)
,
// input
.
page
()
,
// output[1:0]
.
rd
(
buf_rd
)
,
// input
.
data_out
(
buf_rdata
)
// output[63:0]
)
;
fifo_same_clock
#(
...
...
@@ -283,13 +284,13 @@ fifo_same_clock #(
.
DATA_DEPTH
(
PAGE_FIFO_DEPTH
)
)
page_fifo1_i
(
.
rst
(
1'b0
)
,
.
clk
(
mclk
)
,
// posedge
.
clk
(
mclk
)
,
// posedge
.
sync_rst
(
mrst
||
!
nreset_page_fifo
)
,
// synchronously reset fifo;
.
we
(
channel_pgm_en
)
,
.
re
(
buf_run
)
,
.
data_in
(
{
cmd_wr
,
cmd_page
}
)
,
//
page),
.
data_in
(
{
cmd_wr
,
cmd_page
}
)
,
//
page),
.
data_out
(
{
cmd_wr_out
,
page_out
}
)
,
.
nempty
()
,
//
page_fifo1_nempty),
.
nempty
()
,
//
page_fifo1_nempty),
.
half_full
()
)
;
...
...
py393/dbg/x393_mcntrl.pickle
View file @
944ff196
This diff is collapsed.
Click to expand it.
py393/hargs
View file @
944ff196
...
...
@@ -3,4 +3,5 @@
-f /usr/local/verilog/x393_parameters.vh /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh
-l /usr/local/verilog/x393_cur_params_target.vh
-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
-c copy /usr/local/bin/imgsrv.py /www/pages
-i
\ No newline at end of file
py393/imgsrv.py
0 → 100644
View file @
944ff196
#!/usr/bin/python
from
__future__
import
division
from
__future__
import
print_function
'''
# Copyright (C) 2015, Elphel.inc.
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http:#www.gnu.org/licenses/>.
@author: Andrey Filippov
@copyright: 2015 Elphel, Inc.
@license: GPLv3.0+
@contact: andrey@elphel.coml
@deffield updated: Updated
'''
__author__
=
"Andrey Filippov"
__copyright__
=
"Copyright 2015, Elphel, Inc."
__license__
=
"GPL"
__version__
=
"3.0+"
__maintainer__
=
"Andrey Filippov"
__email__
=
"andrey@elphel.com"
__status__
=
"Development"
import
os
import
urlparse
import
time
import
socket
import
shutil
import
sys
path
=
"/www/pages/img.jpeg"
PORT
=
8888
def
communicate
(
port
,
snd_str
):
sock
=
socket
.
socket
(
socket
.
AF_INET
,
socket
.
SOCK_STREAM
)
sock
.
connect
((
'localhost'
,
port
))
sock
.
send
(
snd_str
)
reply
=
sock
.
recv
(
16384
)
# limit reply to 16K
sock
.
close
()
return
reply
try
:
qs
=
urlparse
.
parse_qs
(
os
.
environ
[
'QUERY_STRING'
])
except
:
print
(
"failed in os.environ['QUERY_STRING']"
)
qs
=
{}
acquisition_parameters
=
{
"file_path"
:
"img.jpeg"
,
"channel"
:
"0"
,
"cmode"
:
"0"
,
"bayer"
:
None
,
"y_quality"
:
None
,
"c_quality"
:
None
,
"portrait"
:
None
,
"gamma"
:
None
,
"black"
:
None
,
"colorsat_blue"
:
None
,
"colorsat_red"
:
None
,
"server_root"
:
"/www/pages/"
,
"gain_r"
:
None
,
"gain_gr"
:
None
,
"gain_gb"
:
None
,
"gain_b"
:
None
,
"expos"
:
None
,
"flip_x"
:
None
,
"flip_y"
:
None
,
"verbose"
:
"0"
}
for
k
in
qs
:
if
k
==
"cmode"
:
if
qs
[
k
][
0
]
.
upper
()
==
"JP4"
:
acquisition_parameters
[
k
]
=
"5"
else
:
acquisition_parameters
[
k
]
=
"0"
else
:
acquisition_parameters
[
k
]
=
qs
[
k
][
0
]
#correct bayer (if specified) for flips
if
((
not
acquisition_parameters
[
"bayer"
]
is
None
)
and