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Commit 944ff196 authored by Andrey Filippov's avatar Andrey Filippov
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Merge branch 'serial-sensors' to master

parents 8af3d0c0 2413557f
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.project
View file @ 944ff196
......@@ -62,42 +62,42 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151107204814914.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151117233913191.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151107161051349.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151117233913191.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151107161322372.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151117233913191.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151107161051349.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151117233913191.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151107161322372.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151117233913191.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151107161322372.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151117233913191.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151107160339590.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151117233307674.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151107204814914.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151117233913191.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
......
axi/cmprs_afi_mux.v
View file @ 944ff196
......@@ -195,11 +195,12 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
// reg [2:0] cur_chn; // 'b0xx - none, 'b1** - ** - channel number (should match fifo_ren*)
reg [1:0] cur_chn; // 'b0xx - none, 'b1** - ** - channel number (should match fifo_ren*)
reg [31:0] left_to_eof; // number of chunks left to end of frame
reg [31:0] left_to_eof; // number of chunks left to end of frame (one less: 3 means 4 left)
reg [3:0] fifo_flush_d; // fifo_flush* delayed by 1 clk (to detect rising edge
reg [3:0] eof_stb; // single-cycle pulse after fifo_flush is asserted
// reg [1:0] w64_cnt; // count 64-bit words in a chunk
// adjusted counters used for channel arbitration
// pessimistic FIFO content counter - decrements (form FIFO counter) on FIFO reads, knows nothing of writes
reg [35:0] counts_corr0; // registers to hold corrected (decremented currently processed ones if any) fifo count values, MSB - needs flush
reg [17:0] counts_corr1; // first arbitration level winning values
reg [8:0] counts_corr2; // second arbitration level winning values
......@@ -231,6 +232,8 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
// 3'h4 :
// ({1'b0,left_to_eof[winner2 * 8 +: 2]} + 3'h1);
// Why it has priority for |counts_corr2[7:2] ? If next frame started, it may skip EOF? Or not?
// it is just to pass to a channel, actual transfer size will be decided here (depending on EOF)
wire [1:0] pre_chunk_inc_m1 = (|counts_corr2[7:2])? // Would like to increment, if not roll-over
2'h3 :
left_to_eof[winner2 * 8 +: 2];
......@@ -252,12 +255,15 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
wire [26:0] chunk_ptr_rd;
wire [ 3:0] chunk_ptr_ra;
// If flushing - whatever is left to EOF, otherwise corrected FIFO contents of the winner
wire [ 7:0] items_left = counts_corr2[8] ? left_to_eof[(winner2 * 8) +: 8] : counts_corr2[7:0];
reg [5:0] afi_awid_r;
// "rollover" - roll over destination memory range
wire [2:0] max_wlen; // 0,1,2,3,7 (7 - not limited by rollover) - calculated by cmprs_afi_mux_ptr
wire [1:0] want_wleft32 = (|items_left[7:2])? 2'b11 : items_left[1:0]; // want to set wleft[3:2] if not roll-over
// wants to write (want_wleft32+1) 32-byte chunks (4,3,2,1)
wire [1:0] want_wleft32 = (|items_left[7:2])? 2'b11 : items_left[1:0]; // want to set wleft[3:2] if not roll-over (actually "3" means 2)
assign cmd_we_status_w = cmd_we && ((cmd_a & 'hc) == CMPRS_AFIMUX_STATUS_CNTRL);
assign cmd_we_mode_w = cmd_we && (cmd_a == CMPRS_AFIMUX_MODE);
......@@ -366,16 +372,22 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
// TODO: change &w64_cnt[1:0] so left_to_eof[*] will be updated earlier and valid at pre_busy_w
// Done, updating at the first (not last) word of 4
// Now seems that eof_stb[i] & fifo_ren{i} == 0
if (eof_stb[0]) left_to_eof[0 * 8 +: 8] <= fifo_count0_m1 - (fifo_ren0 & (&wleft[1:0]));
// Seems needs to decrement fifo_count0_m1 regardless of &wleft[1:0] - if started, will eventually decrement
// How to make sure that decremented value always >0?
// if (eof_stb[0]) left_to_eof[0 * 8 +: 8] <= fifo_count0_m1 - (fifo_ren0 & (&wleft[1:0]));
if (eof_stb[0]) left_to_eof[0 * 8 +: 8] <= fifo_count0_m1 - fifo_ren0;
else if (fifo_ren0 & (&wleft[1:0])) left_to_eof[0 * 8 +: 8] <= left_to_eof[0 * 8 +: 8] - 1;
if (eof_stb[1]) left_to_eof[1 * 8 +: 8] <= fifo_count1_m1 - (fifo_ren1 & (&wleft[1:0]));
// if (eof_stb[1]) left_to_eof[1 * 8 +: 8] <= fifo_count1_m1 - (fifo_ren1 & (&wleft[1:0]));
if (eof_stb[1]) left_to_eof[1 * 8 +: 8] <= fifo_count1_m1 - fifo_ren1;
else if (fifo_ren1 & (&wleft[1:0])) left_to_eof[1 * 8 +: 8] <= left_to_eof[1 * 8 +: 8] - 1;
if (eof_stb[2]) left_to_eof[2 * 8 +: 8] <= fifo_count2_m1 - (fifo_ren2 & (&wleft[1:0]));
// if (eof_stb[2]) left_to_eof[2 * 8 +: 8] <= fifo_count2_m1 - (fifo_ren2 & (&wleft[1:0]));
if (eof_stb[2]) left_to_eof[2 * 8 +: 8] <= fifo_count2_m1 - fifo_ren2;
else if (fifo_ren2 & (&wleft[1:0])) left_to_eof[2 * 8 +: 8] <= left_to_eof[2 * 8 +: 8] - 1;
if (eof_stb[3]) left_to_eof[3 * 8 +: 8] <= fifo_count3_m1 - (fifo_ren3 & (&wleft[1:0]));
// if (eof_stb[3]) left_to_eof[3 * 8 +: 8] <= fifo_count3_m1 - (fifo_ren3 & (&wleft[1:0]));
if (eof_stb[3]) left_to_eof[3 * 8 +: 8] <= fifo_count3_m1 - fifo_ren3;
else if (fifo_ren3 & (&wleft[1:0])) left_to_eof[3 * 8 +: 8] <= left_to_eof[3 * 8 +: 8] - 1;
// Calculate corrected values decrementing currently served channel (if any) values by 1 (latency 1 clk)
......
axi/membridge.v
View file @ 944ff196
......@@ -748,7 +748,8 @@ wire [63:0] afi_wdata0;
.ext_raddr ({read_page,buf_in_line64[6:0]}), // input[8:0]
.ext_rd (bufrd_rd[0]), // input
.ext_regen (bufrd_rd[1]), // input
.ext_data_out (afi_wdata0), // output[63:0]
.ext_data_out (afi_wdata0), // output[63:0]
// .emul64 (1'b0), // input Modify buffer addresses (used for JP4 until a 64-wide mode is implemented)
.wclk (!mclk), // input
.wpage_in (2'b0), // input[1:0]
.wpage_set (xfer_reset_page_rd), // input TODO: Generate @ negedge mclk on frame start
......
compressor_jp/bit_stuffer_metadata.v
View file @ 944ff196
......@@ -146,7 +146,7 @@ module bit_stuffer_metadata(
// just for testing
`ifdef DEBUG_RING
assign dbg_ = ts_rstb;
assign dbg_ts_rstb = ts_rstb;
assign dbg_ts_dout = ts_dout;
always @ (posedge xclk) begin
......
compressor_jp/cmprs_pixel_buf_iface.v
View file @ 944ff196
......@@ -67,9 +67,11 @@ module cmprs_pixel_buf_iface #(
// controller this can just be the same as mb_pre_end_in
input mb_pre_start, // 1 clock cycle before stream of addresses to the buffer
input [ 1:0] start_page, // page to read next tile from (or first of several pages)
input [ 6:0] macroblock_x, // macroblock left pixel x relative to a tile (page) Maximal page - 128 bytes wide
input [ 6:0] macroblock_x, // macroblock left pixel x relative to a tile (page) Maximal page - 128 bytes wide.
// valid 3 cycles before mb_pre_start
output reg [ 7:0] data_out, //
output pre_first_out, // For each macroblock in a frame
output pre2_first_out, // 1 cycle before pre_first_out
output reg data_valid //
);
localparam PERIOD_COLOR18 = 384; // >18*18, limited by 6*64 (macroblocks)
......@@ -105,9 +107,14 @@ module cmprs_pixel_buf_iface #(
reg [ 8:0] period_cntr;
reg mb_pre_end_r;
reg mb_release_buf_r;
reg pre_first_out_r;
reg [CMPRS_BUF_EXTRA_LATENCY+2:0] pre_first_out_r;
reg [ 2:0] mb_col_number; // number of tile column where macrobloc starts - valid 2 cycles before mb_pre_start
wire [ 9:0] extra_start_addr_w = mb_col_number * mb_h_m1; //added to mb_start_addr when non-zero column
reg [ 5:0] extra_start_addr_r;
// reg [ 5:0] mb_h; // macroblock height (lost MSB - OK)
reg [ 9:0] mb_start_addr; // was macroblock_x, noccrected for multi-column. valid with mb_pre_start
assign buf_ra = bufa_r;
assign tile_width_or= tile_width[1]?(tile_width[0]?0:'h40):(tile_width[0]?'h60:'h70);
assign column_width_or = tile_col_width? 0: 'h10;
......@@ -119,22 +126,32 @@ module cmprs_pixel_buf_iface #(
assign mb_release_buf = mb_release_buf_r;
assign buf_rd = buf_re[1:0];
// assign data_out = do_r;
assign pre_first_out = pre_first_out_r;
assign pre_first_out = pre_first_out_r[0];
assign pre2_first_out = pre_first_out_r[1];
always @(posedge xclk) begin
// mb_h <= mb_h_m1+1; // macroblock height
mb_col_number <= {macroblock_x[6:5],tile_col_width?1'b0:macroblock_x[4]};
extra_start_addr_r <= extra_start_addr_w[5:0];
mb_start_addr <= {3'b0,macroblock_x} + {extra_start_addr_r,4'b0};
if (!frame_en) buf_re[0] <= 0;
else if (mb_pre_start) buf_re[0] <= 1'b1;
else if (addr_run_end) buf_re[0] <= 1'b0;
if (!frame_en) buf_re[CMPRS_BUF_EXTRA_LATENCY+3:1] <= 0;
else buf_re[CMPRS_BUF_EXTRA_LATENCY+3:1] <= {buf_re[CMPRS_BUF_EXTRA_LATENCY+2:0]};
else buf_re[CMPRS_BUF_EXTRA_LATENCY+3:1] <= {buf_re[CMPRS_BUF_EXTRA_LATENCY + 2:0]};
// Buffer data read:
if (buf_re[CMPRS_BUF_EXTRA_LATENCY+2]) data_out <= buf_di;
//mb_pre_start
if (!frame_en) pre_first_out_r <= 0;
else pre_first_out_r <= buf_re[CMPRS_BUF_EXTRA_LATENCY+1] && ! buf_re[CMPRS_BUF_EXTRA_LATENCY+2];
else pre_first_out_r <= {mb_pre_start, pre_first_out_r[CMPRS_BUF_EXTRA_LATENCY + 2 : 1]};
// else pre_first_out_r <= buf_re[CMPRS_BUF_EXTRA_LATENCY+1] && ! buf_re[CMPRS_BUF_EXTRA_LATENCY+2];
// if (!frame_en) pre2_first_out <= 0;
// else pre2_first_out <= buf_re[CMPRS_BUF_EXTRA_LATENCY + 0] && ! buf_re[CMPRS_BUF_EXTRA_LATENCY + 1];
if (mb_pre_start) rows_left <= mb_h_m1;
else if (last_col) rows_left <= rows_left - 1;
......@@ -153,7 +170,8 @@ module cmprs_pixel_buf_iface #(
first_col <= (mb_pre_start || (last_col && !last_row));
if (mb_pre_start) row_sa <= {start_page,3'b0,macroblock_x};
// if (mb_pre_start) row_sa <= {start_page,3'b0,mb_start_addr}; // macroblock_x};
if (mb_pre_start) row_sa <= {start_page,mb_start_addr}; // macroblock_x};
else if (first_col) row_sa <= row_sa + (tile_col_width ? 12'h20:12'h10);
if (mb_pre_start) tile_sa <= 0;
......@@ -172,7 +190,8 @@ module cmprs_pixel_buf_iface #(
else if (last_in_tile) bufa_r[11:10] <= bufa_r[11:10] + 1;
// Most time critical - calculation of the buffer address
if (mb_pre_start) bufa_r[9:0] <= {3'b0,macroblock_x};
// if (mb_pre_start) bufa_r[9:0] <= {3'b0,mb_start_addr}; // macroblock_x};
if (mb_pre_start) bufa_r[9:0] <= {mb_start_addr}; // macroblock_x};
else if (last_col) bufa_r[9:0] <= row_sa[9:0]; // 'bx next cycle after AFTER mb_pre_start
else if (last_in_tile) bufa_r[9:0] <= tile_sa;
else if (buf_re[0]) bufa_r[9:0] <= bufa_r[9:0] + {last_in_col?col_inc[9:4]:6'b0,4'b1};
......
compressor_jp/csconvert.v
View file @ 944ff196
......@@ -55,7 +55,7 @@ module csconvert#(
input [ 9:0] m_cr, // [9:0] scale for CB - default 0.713 (10'hb6)
input [ 7:0] mb_din, // input bayer data in scanline sequence, GR/BG sequence
input [ 1:0] bayer_phase,
input pre_first_in, // marks the first input pixel
input pre2_first_in, // marks the first input pixel (2 cycles ahead)
output reg [ 8:0] signed_y, // - now signed char, -128(black) to +127 (white)
output reg [ 8:0] signed_c, // new, q is just signed char
......@@ -69,7 +69,7 @@ module csconvert#(
// output reg ccv_out_start, //TODO: adjust to minimal latency?
output reg [ 7:0] n000, // not clear how they are used, make them just with latency1 from old
output reg [ 7:0] n255);
reg pre_first_in;
// outputs to be multiplexed:
wire [7:0] conv18_signed_y, conv20_signed_y, mono16_signed_y, jp4_signed_y;
wire [8:0] jp4diff_signed_y, conv18_signed_c, conv20_signed_c;
......@@ -100,7 +100,8 @@ module csconvert#(
reg [5:0] component_firstsS; // first_r this component in a frame (DC absolute, otherwise - difference to previous)
*/
always @ (posedge xclk) begin
if (pre_first_in) begin
pre_first_in <= pre2_first_in;
if (pre2_first_in) begin
converter_type_r [2:0] <= converter_type[2:0];
ignore_color_r <= ignore_color;
// jp4_dc_improved_r <= jp4_dc_improved;
......@@ -116,23 +117,23 @@ module csconvert#(
end
// generate one-hot converter enable
if (!frame_en) en_converters[CMPRS_COLOR18] <= 0;
else if (pre_first_in) en_converters[CMPRS_COLOR18] <= converter_type == CMPRS_COLOR18;
if (!frame_en) en_converters[CMPRS_COLOR18] <= 0;
else if (pre2_first_in) en_converters[CMPRS_COLOR18] <= converter_type == CMPRS_COLOR18;
if (!frame_en) en_converters[CMPRS_COLOR20] <= 0;
else if (pre_first_in) en_converters[CMPRS_COLOR20] <= converter_type == CMPRS_COLOR20;
if (!frame_en) en_converters[CMPRS_COLOR20] <= 0;
else if (pre2_first_in) en_converters[CMPRS_COLOR20] <= converter_type == CMPRS_COLOR20;
if (!frame_en) en_converters[CMPRS_MONO16] <= 0;
else if (pre_first_in) en_converters[CMPRS_MONO16] <= converter_type == CMPRS_MONO16;
if (!frame_en) en_converters[CMPRS_MONO16] <= 0;
else if (pre2_first_in) en_converters[CMPRS_MONO16] <= converter_type == CMPRS_MONO16;
if (!frame_en) en_converters[CMPRS_JP4] <= 0;
else if (pre_first_in) en_converters[CMPRS_JP4] <= converter_type == CMPRS_JP4;
if (!frame_en) en_converters[CMPRS_JP4] <= 0;
else if (pre2_first_in) en_converters[CMPRS_JP4] <= converter_type == CMPRS_JP4;
if (!frame_en) en_converters[CMPRS_JP4DIFF] <= 0;
else if (pre_first_in) en_converters[CMPRS_JP4DIFF] <= converter_type == CMPRS_JP4DIFF;
if (!frame_en) en_converters[CMPRS_JP4DIFF] <= 0;
else if (pre2_first_in) en_converters[CMPRS_JP4DIFF] <= converter_type == CMPRS_JP4DIFF;
if (!frame_en) en_converters[CMPRS_MONO8] <= 0;
else if (pre_first_in) en_converters[CMPRS_MONO8] <= converter_type == CMPRS_MONO8;
if (!frame_en) en_converters[CMPRS_MONO8] <= 0;
else if (pre2_first_in) en_converters[CMPRS_MONO8] <= converter_type == CMPRS_MONO8;
end
......
compressor_jp/huffman_stuffer_meta.v
View file @ 944ff196
......@@ -161,6 +161,11 @@ module huffman_stuffer_meta(
.data_out_valid (data_out_valid), // output reg
.done (done), // output reg
.running (running) // output reg
`ifdef DEBUG_RING
,.dbg_etrax_dma (dbg_etrax_dma), // output[3:0] reg
.dbg_ts_rstb (dbg_ts_rstb), // output
.dbg_ts_dout (dbg_ts_dout) // output[7:0]
`endif
);
endmodule
......
compressor_jp/jp_channel.v
View file @ 944ff196
......@@ -262,6 +262,7 @@ module jp_channel#(
// signals connecting modules: chn_rd_buf_i and ???:
wire [ 7:0] mb_data_out; // Macroblock data out in scanline order
wire mb_pre_first_out; // Macroblock data out strobe - 1 cycle just before data valid
wire mb_pre2_first_out; // Macroblock data out strobe - 2 cycles just before data valid
// wire mb_data_valid; // Macroblock data out valid
wire limit_diff = 1'b1; // as in the prototype - just a constant 1
......@@ -376,6 +377,7 @@ module jp_channel#(
// wire flush; // output reg @ negedge xclk2x
wire last_block = 0; // @negedge xxlk2x - used to copy timestamp in stuffer
wire stuffer_rdy = 1; // receiver (bit stuffer) is ready to accept data;
wire xrst2xn = xrst;
`endif
......@@ -418,7 +420,19 @@ module jp_channel#(
reg [15:0] dbg_zds_cntr;
wire [2:0] dbg_block_mem_wa;
wire [2:0] dbg_block_mem_wa_save;
`ifndef USE_XCLK2X
// temporarily assigning unused debug signals to 0
// assign dbg_add_invalid = 0;
// assign dbg_mb_release_buf = 0;
// assign etrax_dma = 0;
// assign dbg_ts_rstb = 0; // output
// assign dbg_ts_dout = 0; //output [7:0]
assign dbg_flushing = 0; // still not used in huffman_stuffer_meta
// assign dbg_test_lbw = 0;
// assign dbg_gotLastBlock = 0;
assign dbg_fifo_or_full = 0; // still not used in huffman_stuffer_meta
`endif
timestamp_to_parallel dbg_timestamp_to_parallel_i (
`ifdef USE_XCLK2X
.clk (~xclk2x), // input
......@@ -428,7 +442,7 @@ module jp_channel#(
.pre_stb (dbg_ts_rstb), // input
.tdata (dbg_ts_dout), // input[7:0]
.sec (dbg_sec), // output[31:0] reg
.usec (dbg_usec), // output[19:0] reg
.usec (dbg_usec[19:0]), // output[19:0] reg
.done() // output
);
......@@ -599,22 +613,29 @@ module jp_channel#(
.start (status_start) // input
);
//hifreq
// Port buffer - TODO: Move to memory controller
// Not needed?
// reg emul64;
// always @ (negedge mclk) begin
// emul64 <= tile_width[1]; // will not work for monochrome (128 pixel wide) - chnge to 64?
// end
mcntrl_buf_rd #(
.LOG2WIDTH_RD(3) // 64 bit external interface
) chn_rd_buf_i (
.ext_clk (xclk), // input
.ext_raddr (buf_ra), // input[11:0]
.ext_rd (buf_rd[0]), // input
.ext_regen (buf_rd[1]), // input
.ext_data_out (buf_pxd), // output[7:0]
.wclk (!mclk), // input
.wpage_in (2'b0), // input[1:0]
.ext_clk (xclk), // input
.ext_raddr (buf_ra), // input[11:0]
.ext_rd (buf_rd[0]), // input
.ext_regen (buf_rd[1]), // input
.ext_data_out (buf_pxd), // output[7:0]
// .emul64 (1'b0), //emul64), // input Modify buffer addresses (used for JP4 until a 64-wide mode is implemented)
.wclk (!mclk), // input
.wpage_in (2'b0), // input[1:0]
.wpage_set (xfer_reset_page_rd), // input TODO: Generate @ negedge mclk on frame start
.page_next (buf_wpage_nxt), // input
.page (), // output[1:0]
.we (buf_we), // input
.data_in (buf_din) // input[63:0]
.page_next (buf_wpage_nxt), // input
.page (), // output[1:0]
.we (buf_we), // input
.data_in (buf_din) // input[63:0]
);
cmprs_cmd_decode #(
......@@ -824,7 +845,8 @@ module jp_channel#(
.data_out (mb_data_out), // output[7:0] // Macroblock data out in scanline order
.pre_first_out (mb_pre_first_out), // output // Macroblock data out strobe - 1 cycle just before data valid == old pre_first_pixel?
// .data_valid (mb_data_valid) // output // Macroblock data out valid
.data_valid () // output // Macroblock data out valid Unused
.pre2_first_out (mb_pre2_first_out), // output reg
.data_valid () // output reg // Macroblock data out valid Unused
);
csconvert #(
......@@ -846,7 +868,7 @@ module jp_channel#(
.m_cr (m_cr), // input[9:0]
.mb_din (mb_data_out), // input[7:0]
.bayer_phase (bayer_phase), // input[1:0]
.pre_first_in (mb_pre_first_out), // input
.pre2_first_in (mb_pre2_first_out),// input
.signed_y (signed_y), // output[8:0] reg
.signed_c (signed_c), // output[8:0] reg
.yaddrw (yaddrw), // output[7:0] reg
......
fpga_version.vh
View file @ 944ff196
......@@ -31,8 +31,18 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
parameter FPGA_VERSION = 32'h0393006a; // modified clock generation, trying with HiSPi - 72.77% utilization
parameter FPGA_VERSION = 32'h03930071; // Fixing AXI HP multiplexer xclk -0.083 -1.968 44 / 15163 (77.17%)
// parameter FPGA_VERSION = 32'h03930070; // Fixing HiSPi xclk -0.049 -0.291 17, utilization 15139 (77.04%)
// parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xcl -0.002 -0.004 2, utilization 15144 (77.07 %)
// parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xclk -0.209/-2.744/23, utilization 15127 (76.98%)
// parameter FPGA_VERSION = 32'h0393006e; // Trying lane switch again after bug fix, failing 1 in ddr3_mclk -> ddr3_clk_div by -0.023
// parameter FPGA_VERSION = 32'h0393006d; // -1 with lane switch - does not work
// parameter FPGA_VERSION = 32'h0393006d; // Reversing pixels/lanes order xclk violated -0.154
// parameter FPGA_VERSION = 32'h0393006c; // will try debug for HiSPi. xclk violated by -0.030, slices 15062 (76.65%)
// parameter FPGA_VERSION = 32'h0393006b; // Correcting sensor external clock generation - was wrong division. xclk violated by 0.095 ns
// parameter FPGA_VERSION = 32'h0393006a; // modified clock generation, trying with HiSPi - 72.77% utilization x40..x60
// parameter FPGA_VERSION = 32'h03930069; // modified clock generation, rebuilding for parallel sensors - all met, 71.8% utilization
// Worked OK, but different phase for sensor 0 (all quadrants as 1,3 OK)
// parameter FPGA_VERSION = 32'h03930068; // trying BUFR/FUFIO on all sensors ipclk/ipclk2x
// parameter FPGA_VERSION = 32'h03930067; // removing DUMMY_TO_KEEP, moving IOSTANDARD to HDL code
// parameter FPGA_VERSION = 32'h03930066; // trying just one histogram to watch utilization - with 4 was: Slice 15913 (80.98%), now Slice = 14318 (72.87%)
......
includes/x393_parameters.vh
View file @ 944ff196
......@@ -598,7 +598,10 @@
parameter HISPI_MMCM1 = "FALSE",
parameter HISPI_MMCM2 = "TRUE",
parameter HISPI_MMCM3 = "FALSE",
parameter HISPI_KEEP_IRST = 5, // number of cycles to keep irst on after release of prst (small number - use 1 hot)
parameter HISPI_WAIT_ALL_LANES = 4'h8, // number of output pixel cycles to wait after the earliest lane
parameter HISPI_FIFO_DEPTH = 4,
parameter HISPI_FIFO_START = 7,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
parameter HISPI_DQS_BIAS = "TRUE",
......
includes/x393_simulation_parameters.vh
View file @ 944ff196
......@@ -41,7 +41,11 @@
parameter SIMUL_AXI_READ_WIDTH=16,
parameter MEMCLK_PERIOD = 5.0,
parameter FCLK0_PERIOD = 41.667, // 10.417, 24MHz
`ifdef HISPI
parameter FCLK0_PERIOD = 40.91, // 24.444MHz
`else
parameter FCLK0_PERIOD = 41.667, // 24MHz
`endif
parameter FCLK1_PERIOD = 0.0,
// parameter SENSOR12BITS_LLINE = 192, // 1664;// line duration in clocks
......@@ -55,6 +59,29 @@
parameter SENSOR_IMAGE_TYPE1 = "RUN1",
parameter SENSOR_IMAGE_TYPE2 = "NORM", // "RUN1",
parameter SENSOR_IMAGE_TYPE3 = "RUN1",
parameter SIMULATE_CMPRS_CMODE0 = CMPRS_CBIT_CMODE_JPEG18,
parameter SIMULATE_CMPRS_CMODE1 = CMPRS_CBIT_CMODE_JPEG18,
parameter SIMULATE_CMPRS_CMODE2 = CMPRS_CBIT_CMODE_JP4,
parameter SIMULATE_CMPRS_CMODE3 = CMPRS_CBIT_CMODE_JP4,
// CMPRS_CBIT_CMODE_JPEG18, //input [31:0] cmode; // [13:9] color mode:
// parameter CMPRS_CBIT_CMODE_JPEG18 = 4'h0, // color 4:2:0
// parameter CMPRS_CBIT_CMODE_MONO6 = 4'h1, // mono 4:2:0 (6 blocks)
// parameter CMPRS_CBIT_CMODE_JP46 = 4'h2, // jp4, 6 blocks, original
// parameter CMPRS_CBIT_CMODE_JP46DC = 4'h3, // jp4, 6 blocks, dc -improved
// parameter CMPRS_CBIT_CMODE_JPEG20 = 4'h4, // mono, 4 blocks (but still not actual monochrome JPEG as the blocks are scanned in 2x2 macroblocks)
// parameter CMPRS_CBIT_CMODE_JP4 = 4'h5, // jp4, 4 blocks, dc-improved
// parameter CMPRS_CBIT_CMODE_JP4DC = 4'h6, // jp4, 4 blocks, dc-improved
// parameter CMPRS_CBIT_CMODE_JP4DIFF = 4'h7, // jp4, 4 blocks, differential
// parameter CMPRS_CBIT_CMODE_JP4DIFFHDR = 4'h8, // jp4, 4 blocks, differential, hdr
// parameter CMPRS_CBIT_CMODE_JP4DIFFDIV2 = 4'h9, // jp4, 4 blocks, differential, divide by 2
// parameter CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = 4'ha, // jp4, 4 blocks, differential, hdr,divide by 2
// parameter CMPRS_CBIT_CMODE_MONO1 = 4'hb, // mono JPEG (not yet implemented)
// parameter CMPRS_CBIT_CMODE_MONO4 = 4'he, // mono 4 blocks
parameter SENSOR12BITS_NGPL = 8, // bpf to hact
parameter SENSOR12BITS_NVLO = 1, // VACT=0 in video mode (clocks)
//parameter tMD = 14; //
......
memctrl/mcntrl393.v
View file @ 944ff196
......@@ -947,6 +947,7 @@ module mcntrl393 #(
.ext_rd (buf2rd_rd), // input
.ext_regen (buf2rd_regen), // input
.ext_data_out (buf2rd_data), // output[31:0]
// .emul64 (1'b0), // input Modify buffer addresses (used for JP4 until a 64-wide mode is implemented)
.wclk (!mclk), // input
.wpage_in (2'b0), // input[1:0]
.wpage_set (xfer_reset_page2_rd), // input TODO: Generate @ negedge mclk on frame start
......@@ -982,6 +983,7 @@ module mcntrl393 #(
.ext_rd (buf3rd_rd), // input
.ext_regen (buf3rd_regen), // input
.ext_data_out (buf3rd_data), // output[31:0]
// .emul64 (1'b0), // input Modify buffer addresses (used for JP4 until a 64-wide mode is implemented)
.wclk (!mclk), // input
.wpage_in (2'b0), // input[1:0]
.wpage_set (xfer_reset_page3_rd), // input @ negedge mclk
......@@ -1017,6 +1019,7 @@ module mcntrl393 #(
.ext_rd (buf4rd_rd), // input
.ext_regen (buf4rd_regen), // input
.ext_data_out (buf4rd_data), // output[31:0]
// .emul64 (1'b0), // input Modify buffer addresses (used for JP4 until a 64-wide mode is implemented)
.wclk (!mclk), // input
.wpage_in (2'b0), // input[1:0]
.wpage_set (xfer_reset_page4_rd), // input @ negedge mclk
......
memctrl/mcntrl_buf_rd.v
View file @ 944ff196
......@@ -43,6 +43,8 @@ module mcntrl_buf_rd #(
input ext_regen, // output register enable
output [(1 << LOG2WIDTH_RD)-1:0] ext_data_out, // data out
// input emul64, // emulate 64 pixel wide reads with actual 32-wide columns
// in the future - use rd64/wr64 for JP4 mode
input wclk, // !mclk (inverted)
input [1:0] wpage_in, // will register to wclk, input OK with mclk
input wpage_set, // set internal write page to wpage_in
......@@ -54,6 +56,9 @@ module mcntrl_buf_rd #(
reg [1:0] page_r;
reg [6:0] waddr;
assign page=page_r;
// wire [4:0] next62_norm = waddr[6:2] + 1;
// wire [4:0] next62_rot = {waddr[2],waddr[6:3]} + 1;
// wire [4:0] next62_emul64 = {next62_rot[3:0],next62_rot[4]};
always @ (posedge wclk) begin
if (wpage_set) page_r <= wpage_in;
......@@ -61,6 +66,13 @@ module mcntrl_buf_rd #(
if (page_next || wpage_set) waddr <= 0;
else if (we) waddr <= waddr+1;
// if (page_next || wpage_set) waddr[1:0] <= 0;
// else if (we) waddr[1:0] <= waddr[1:0] + 1;
// if (page_next || wpage_set) waddr[6:2] <= 0;
// else if (we && (&waddr[1:0])) waddr[6:2] <= emul64 ? next62_emul64 : next62_norm;
end
// ram_512x64w_1kx32r #(
ram_var_w_var_r #(
......
memctrl/mcntrl_ps_pio.v
View file @ 944ff196
......@@ -247,35 +247,36 @@ fifo_same_clock #(
mcntrl_buf_rd #(
.LOG2WIDTH_RD(5)
) chn0_buf_i (
.ext_clk (port0_clk), // input
.ext_raddr (port0_addr), // input[9:0]
.ext_rd (port0_re), // input
.ext_regen (port0_regen), // input
.ext_data_out (port0_data), // output[31:0]
.wclk (!mclk), // input
.ext_clk (port0_clk), // input
.ext_raddr (port0_addr), // input[9:0]
.ext_rd (port0_re), // input
.ext_regen (port0_regen), // input
.ext_data_out (port0_data), // output[31:0]
// .emul64 (1'b0), // input Modify buffer addresses (used for JP4 until a 64-wide mode is implemented)
.wclk (!mclk), // input
.wpage_in (page_out_r_negedge), // page_neg), // input[1:0]
.wpage_set (page_w_set_negedge), //wpage_set_chn0_neg), // input
.page_next (buf_wpage_nxt), // input
.page (), // output[1:0]
.we (buf_wr), // input
.data_in (buf_wdata) // input[63:0]
.wpage_set (page_w_set_negedge), // wpage_set_chn0_neg), // input
.page_next (buf_wpage_nxt), // input
.page (), // output[1:0]
.we (buf_wr), // input
.data_in (buf_wdata) // input[63:0]
);
// Port 1 (write DDR from AXI) buffer
mcntrl_buf_wr #(
.LOG2WIDTH_WR(5)
) chn1_buf_i (
.ext_clk (port1_clk), // input
.ext_waddr (port1_addr), // input[9:0]
.ext_we (port1_we), // input
.ext_data_in (port1_data), // input[31:0]
.rclk (mclk), // input
.rpage_in (page_out_r), //page), // input[1:0]
.rpage_set (page_r_set), // rpage_set_chn1), // input
.page_next (buf_rpage_nxt), // input
.page (), // output[1:0]
.rd (buf_rd), // input
.data_out (buf_rdata) // output[63:0]
.ext_clk (port1_clk), // input
.ext_waddr (port1_addr), // input[9:0]
.ext_we (port1_we), // input
.ext_data_in (port1_data), // input[31:0]
.rclk (mclk), // input
.rpage_in (page_out_r), // page), // input[1:0]
.rpage_set (page_r_set), // rpage_set_chn1), // input
.page_next (buf_rpage_nxt), // input
.page (), // output[1:0]
.rd (buf_rd), // input
.data_out (buf_rdata) // output[63:0]
);
fifo_same_clock #(
......@@ -283,13 +284,13 @@ fifo_same_clock #(
.DATA_DEPTH(PAGE_FIFO_DEPTH)
) page_fifo1_i (
.rst (1'b0),
.clk (mclk), // posedge
.clk (mclk), // posedge
.sync_rst (mrst || !nreset_page_fifo), // synchronously reset fifo;
.we (channel_pgm_en),
.re (buf_run),
.data_in ({cmd_wr,cmd_page}), //page),
.data_in ({cmd_wr,cmd_page}), // page),
.data_out ({cmd_wr_out,page_out}),
.nempty (), //page_fifo1_nempty),
.nempty (), // page_fifo1_nempty),
.half_full ()
);
......
py393/dbg/x393_mcntrl.pickle
View file @ 944ff196
This source diff could not be displayed because it is too large. You can view the blob instead.
py393/hargs
View file @ 944ff196
......@@ -3,4 +3,5 @@
-f /usr/local/verilog/x393_parameters.vh /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh
-l /usr/local/verilog/x393_cur_params_target.vh
-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
-c copy /usr/local/bin/imgsrv.py /www/pages
-i
\ No newline at end of file
py393/imgsrv.py 0 → 100644
View file @ 944ff196
#!/usr/bin/python
from __future__ import division
from __future__ import print_function
'''
# Copyright (C) 2015, Elphel.inc.
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http:#www.gnu.org/licenses/>.
@author: Andrey Filippov
@copyright: 2015 Elphel, Inc.
@license: GPLv3.0+
@contact: andrey@elphel.coml
@deffield updated: Updated
'''
__author__ = "Andrey Filippov"
__copyright__ = "Copyright 2015, Elphel, Inc."
__license__ = "GPL"
__version__ = "3.0+"
__maintainer__ = "Andrey Filippov"
__email__ = "andrey@elphel.com"
__status__ = "Development"
import os
import urlparse
import time
import socket
import shutil
import sys
path="/www/pages/img.jpeg"
PORT=8888
def communicate(port,snd_str):
sock = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
sock.connect(('localhost', port))
sock.send(snd_str)
reply = sock.recv(16384) # limit reply to 16K
sock.close()
return reply
try:
qs=urlparse.parse_qs(os.environ['QUERY_STRING'])
except:
print("failed in os.environ['QUERY_STRING']")
qs={}
acquisition_parameters={
"file_path": "img.jpeg",
"channel": "0",
"cmode": "0",
"bayer": None,
"y_quality": None,
"c_quality": None,
"portrait": None,
"gamma": None,
"black": None,
"colorsat_blue":None,
"colorsat_red": None,
"server_root": "/www/pages/",
"gain_r": None,
"gain_gr": None,
"gain_gb": None,
"gain_b": None,
"expos": None,
"flip_x": None,
"flip_y": None,
"verbose": "0"}
for k in qs:
if k == "cmode":
if qs[k][0].upper() == "JP4":
acquisition_parameters[k] = "5"
else:
acquisition_parameters[k] = "0"
else:
acquisition_parameters[k] = qs[k][0]
#correct bayer (if specified) for flips
if ((not acquisition_parameters["bayer"] is None) and
((not acquisition_parameters["flip_x"] is None) or
(not acquisition_parameters["flip_y"] is None))):
ibayer= int (acquisition_parameters["bayer"])
if acquisition_parameters["flip_x"]:
if int (acquisition_parameters["flip_x"]):
ibayer ^= 1
if int (acquisition_parameters["flip_y"]):
ibayer ^= 2
acquisition_parameters["bayer"] = str(ibayer)
cmd_str = "jpeg_acquire_write %s %s %s %s %s %s %s %s %s %s %s %s %s"%(
str(acquisition_parameters["file_path"]),
str(acquisition_parameters["channel"]),
str(acquisition_parameters["cmode"]),
str(acquisition_parameters["bayer"]),
str(acquisition_parameters["y_quality"]),
str(acquisition_parameters["c_quality"]),
str(acquisition_parameters["portrait"]),
str(acquisition_parameters["gamma"]),
str(acquisition_parameters["black"]),
str(acquisition_parameters["colorsat_blue"]),
str(acquisition_parameters["colorsat_red"]),
str(acquisition_parameters["server_root"]),
str(acquisition_parameters["verbose"]))
gains_exp_changed = False
geometry_changed = False
#change gains/exposure if needed
if ((not acquisition_parameters["gain_r"] is None) or
(not acquisition_parameters["gain_gr"] is None) or
(not acquisition_parameters["gain_gb"] is None) or
(not acquisition_parameters["gain_b"] is None) or
(not acquisition_parameters["expos"] is None)):
gains_exp_changed = True
gstr = "set_sensor_gains_exposure %s %s %s %s %s %s %s"%(
str(acquisition_parameters["channel"]),
str(acquisition_parameters["gain_r"]),
str(acquisition_parameters["gain_gr"]),
str(acquisition_parameters["gain_gb"]),
str(acquisition_parameters["gain_b"]),
str(acquisition_parameters["expos"]),
str(acquisition_parameters["verbose"]))
communicate(PORT, gstr)
#change flips if needed
if ((not acquisition_parameters["flip_x"] is None) or
(not acquisition_parameters["flip_yr"] is None)):
geometry_changed = True
fstr = "set_sensor_flipXY %s %s %s %s"%(
str(acquisition_parameters["channel"]),
str(acquisition_parameters["flip_x"]),
str(acquisition_parameters["flip_y"]),
str(acquisition_parameters["verbose"]))
communicate(PORT, fstr)
#How many bad/non modified frames are to be skipped (just a guess)
skip_frames = 0
if geometry_changed:
skip_frames = 2
elif gains_exp_changed:
skip_frames = 1
if (str(acquisition_parameters["channel"])[0].upper() == 'A'):
channel_mask = 0x0f
else:
channel_mask = 1 << int(acquisition_parameters["channel"])
skip_str= "skip_frame %d"%(channel_mask)
for i in range(skip_frames):
communicate(PORT, skip_str)
# Now - get that image
reply = communicate(PORT,cmd_str)
if (acquisition_parameters["cmode"] =="5"):
path = path.replace("jpeg","jp4")
timestamp =str(time.time()).replace(".","_") # later use image timestamp
print("Content-Type: image/jpeg")
print("Content-Disposition: inline; filename=\"elphelimg_%s.jpeg\""%(timestamp))
print("Content-Length: %d\n"%(os.path.getsize(path))) # extra \n
with open(path, "r") as f:
shutil.copyfileobj(f, sys.stdout)
py393/test_mcntrl.py
View file @ 944ff196
......@@ -22,6 +22,7 @@
@contact: andrey@elphel.coml
@deffield updated: Updated
'''
from __future__ import print_function
from __builtin__ import str
__author__ = "Andrey Filippov"
__copyright__ = "Copyright 2015, Elphel, Inc."
......@@ -43,6 +44,10 @@ from argparse import ArgumentParser
#import argparse
from argparse import RawDescriptionHelpFormatter
import time
#import shutil
import socket
import select
from import_verilog_parameters import ImportVerilogParameters
#from import_verilog_parameters import VerilogParameters
from verilog_utils import hx
......@@ -217,6 +222,8 @@ USAGE
parser.add_argument("-x", "--exceptions", dest="exceptions", action="count", help="Exit on more exceptions [default: %(default)s]")
parser.add_argument("-l", "--localparams", dest="localparams", action="store", default="",
help="path were modified parameters are saved [default: %(default)s]", metavar="path")
parser.add_argument("-P", "--socket-port", dest="socket_port", action="store", default="",
help="port to use for socket connection [default: %(default)s]")
# Process arguments
args = parser.parse_args()
......@@ -391,18 +398,75 @@ USAGE
'''
#TODO: use readline
'''
if args.socket_port:
PORT = int(args.socket_port) # 8888
else:
PORT = 0
HOST = '' # Symbolic name meaning all available interfaces
socket_conn = None
if PORT:
socket_conn = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
try:
socket_conn.bind((HOST, PORT))
print ('Socket bind complete')
socket_conn.listen(1) # just a single request
print ('Socket now listening to a single request on port %d: send command, receive response, close'%(PORT))
except socket.error as msg:
print ('Bind failed. Error Code : %s Message %s'%( str(msg[0]),msg[1]))
socket_conn = None # do not use sockets
if (args.interactive):
line =""
while True:
line=raw_input('x393%s +%3.3fs--> '%(('','(simulated)')[args.simulated],(time.time()-tim))).strip()
soc_conn = None
prompt = 'x393%s +%3.3fs--> '%(('','(simulated)')[args.simulated],(time.time()-tim))
if socket_conn:
print(prompt , end="")
sys.stdout.flush()
ready_to_read, _, _ = select.select( #ready_to_write, in_error
[socket_conn, sys.stdin], # potential_readers,
[], # potential_writers,
[]) # potential_errs,
if sys.stdin in ready_to_read:
line=raw_input()
# print ("stdin: ", line)
elif socket_conn in ready_to_read:
try:
soc_conn, soc_addr = socket_conn.accept()
print ("Connected with %s"%(soc_addr[0] + ':' + str(soc_addr[1])))
#Sending message to connected client
#soc_conn.send('Welcome to the server. Type something and hit enter\n') #send only takes string
line = soc_conn.recv(4096) # or make it unlimited?
print ('Received from socket: ', line)
except:
continue # socket probably died, wait for the next command
else:
print ("Unexpected result from select: ready_to_read = ",ready_to_read)
continue
else: # No sockets, just command line input
line=raw_input(prompt)
# line=raw_input('x393%s +%3.3fs--> '%(('','(simulated)')[args.simulated],(time.time()-tim))).strip()
line=line.strip() # maybe also remove comment?
# Process command, return result to a socket if it was a socket, not stdin
tim=time.time()
#remove comment from the input line
if line.find("#") > 0:
had_comment=False
if line.find("#") >= 0:
line=line[:line.find("#")]
had_comment=True
lineList=line.split()
if not line:
print ('Use "quit" to exit, "help" - for help')
if not had_comment:
print ('Use "quit" to exit, "help" - for help')
elif (line == 'quit') or (line == 'exit'):
if soc_conn:
soc_conn.send('0\n') # OK\n')
soc_conn.close()
# soc_conn=None
break
elif line== 'help' :
print ("\nAvailable tasks:")
......@@ -412,6 +476,8 @@ USAGE
print ('\n"parameters" and "defines" list known defined parameters and macros')
print ("args.exception=%d, QUIET=%d"%(args.exceptions,QUIET))
print ("Enter 'R' to toggle show/hide command results, now it is %s"%(("OFF","ON")[showResult]))
print ("Use 'socket_port [PORT]' to (re-)open socket on PORT (0 or no PORT - disable socket)")
# print ("Use 'copy <SRC> <DST> to copy files in file the system")
print ("Use 'pydev_predefines' to generate a parameter list to paste to vrlg.py, so Pydev will be happy")
elif lineList[0].upper() == 'R':
if len(lineList)>1:
......@@ -424,9 +490,27 @@ USAGE
else:
showResult = not showResult
print ("Show results mode is now %s"%(("OFF","ON")[showResult]))
# elif (len(line) > len("help")) and (line[:len("help")]=='help'):
elif (lineList[0].upper() == 'SOCKET_PORT') and (not soc_conn): # socket_conn):
if socket_conn : # close old socket (if open)
print ("Closed socket on port %d"%(PORT))
socket_conn.close()
socket_conn = None
if len(lineList) > 1: # port specified
PORT = int(lineList[1])
if PORT:
socket_conn = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
try:
socket_conn.bind((HOST, PORT))
print ('Socket bind complete')
socket_conn.listen(1) # just a single request
print ('Socket now listening to a single request on port %d: send command, receive response, close'%(PORT))
except socket.error as msg:
print ('Bind failed. Error Code : %s Message %s'%( str(msg[0]),msg[1]))
socket_conn = None # do not use sockets
continue
# elif lineList[0] == 'copy':
# shutil.copy2(lineList[1], lineList[2])
elif lineList[0] == 'help':
# helpFilter=line[len('help'):].strip()
helpFilter=lineList[1] # should not fail
try:
re.match(helpFilter,"")
......@@ -506,6 +590,10 @@ USAGE
vrlg_text=vrlg_text[:index+1]+"\n"+predefines
except:
print ("Failed to update %s - it is either missing or does not have a '%s'"%(vrlg_path,magic))
if soc_conn:
soc_conn.send('0\n')
soc_conn.close()
# soc_conn=None
continue
try:
with open (vrlg_path, "w") as vrlg_file:
......@@ -535,7 +623,17 @@ USAGE
# strarg=line[len(lineList[0]):].strip()
rslt= execTask(cmdLine)
if showResult:
print (' Result: '+hx(rslt))
print (' Result: '+hx(rslt))
if soc_conn:
soc_conn.send(str(rslt)+'\n')
soc_conn.close()
# soc_conn=None
continue
if soc_conn:
soc_conn.send('0\n')
soc_conn.close()
# soc_conn=None
#http://stackoverflow.com/questions/11781265/python-using-getattr-to-call-function-with-variable-parameters
#*getattr(foo,bar)(*params)
return 0
......
py393/vrlg.py
View file @ 944ff196
......@@ -177,7 +177,6 @@ CLKFBOUT_PHASE_SENSOR = float
DFLT_REFRESH_PERIOD = int
MCONTR_TOP_0BIT_REFRESH_EN__TYPE = str
NUM_CYCLES_20__TYPE = str
CMPRS_CSAT_CB__RAW = str
SENS_JTAG_PGMEN = int
NUM_CYCLES_03__TYPE = str
CMPRS_CBIT_RUN_BITS__TYPE = str
......@@ -207,14 +206,12 @@ MEMBRIDGE_WIDTH64__RAW = str
LOGGER_CONF_MSG_BITS__RAW = str
SENS_GAMMA_MODE_REPET = int
SENSI2C_TBL_DLY__RAW = str
CLKFBOUT_MULT_REF = int
CMPRS_CBIT_BAYER_BITS__TYPE = str
MCONTR_CMPRS_STATUS_INC = int
MCONTR_PHY_0BIT_CMDA_EN__TYPE = str
MCNTRL_TEST01_STATUS_REG_CHN1_ADDR = int
RTC_SET_STATUS__TYPE = str
CMPRS_CBIT_QBANK_BITS__RAW = str
FFCLK0_IBUF_DELAY_VALUE__RAW = str
DEBUG_READ_REG_ADDR = int
WINDOW_HEIGHT = int
CAMSYNC_TRIG_DELAY0__RAW = str
......@@ -243,13 +240,13 @@ SENSOR_16BIT_BIT__RAW = str
HIST_SAXI_AWCACHE__TYPE = str
SENSI2C_CMD_RUN_PBITS__TYPE = str
LOGGER_CONF_SYN_BITS__TYPE = str
MULTICLK_DIVCLK__RAW = str
GPIO_ADDR__TYPE = str
CAMSYNC_TRIG_SRC = int
SENS_CTRL_GP1__RAW = str
CLKOUT_DIV_PCLK__TYPE = str
LOGGER_PAGE_IMU = int
MEMCLK_IOSTANDARD__RAW = str
CLKFBOUT_MULT_SYNC__TYPE = str
MAX_TILE_HEIGHT__RAW = str
BUF_IPCLK2X_SENS3__TYPE = str
IBUF_LOW_PWR = str
......@@ -257,9 +254,11 @@ DEBUG_CMD_LATENCY = int
CMD_DONE_BIT = int
NUM_CYCLES_31 = int
NUM_CYCLES_30 = int
HISPI_DELAY_CLK0__TYPE = str
CMPRS_CBIT_QBANK__RAW = str
SENS_SYNC_MASK__TYPE = str
MCONTR_BUF0_RD_ADDR__RAW = str
HISPI_MMCM1 = str
SENS_PHASE_WIDTH = int
HIST_SAXI_MODE_ADDR_MASK__TYPE = str
MCONTR_CMPRS_STATUS_BASE__RAW = str
......@@ -267,7 +266,6 @@ SENS_LENS_RADDR__TYPE = str
CAMSYNC_PRE_MAGIC__TYPE = str
MCNTRL_TEST01_CHN3_STATUS_CNTRL__RAW = str
DEBUG_LOAD = int
FFCLK0_DQS_BIAS = str
CMPRS_JP4DIFF__TYPE = str
LOGGER_CONF_DBG__RAW = str
FRAME_START_ADDRESS_INC__TYPE = str
......@@ -275,7 +273,6 @@ DLY_DQS_IDELAY__TYPE = str
CLK_PHASE = float
MCNTRL_TILED_FRAME_PAGE_RESET = int
MCONTR_SENS_STATUS_BASE__TYPE = str
SENSI2C_CMD_TAND__TYPE = str
CMPRS_FORMAT__TYPE = str
DLY_LANE1_DQS_WLV_IDELAY__RAW = str
SENS_LENS_RADDR = int
......@@ -297,10 +294,12 @@ REF_JITTER1__RAW = str
CAMSYNC_MASK__TYPE = str
SENS_JTAG_PGMEN__RAW = str
MCONTR_LINTILE_EXTRAPG_BITS__TYPE = str
SENS_CTRL_RST_MMCM = int
MCONTR_BUF3_RD_ADDR__TYPE = str
LOGGER_CONF_EN_BITS__TYPE = str
CLKIN_PERIOD_PCLK__RAW = str
MAX_TILE_WIDTH__TYPE = str
MULTICLK_DIV_DLYREF__TYPE = str
MULTICLK_MULT = int
SENS_LENS_POST_SCALE_MASK = int
BUF_IPCLK2X_SENS1__RAW = str
SENSOR_MODE_WIDTH__RAW = str
......@@ -338,9 +337,9 @@ CMPRS_CBIT_CMODE_JP46__TYPE = str
NUM_CYCLES_17__RAW = str
DFLT_WBUF_DELAY__RAW = str
CAMSYNC_POST_MAGIC__RAW = str
MCNTRL_TEST01_CHN2_MODE__TYPE = str
NUM_CYCLES_07__RAW = str
NUM_CYCLES_24__RAW = str
SENS_REFCLK_FREQUENCY__TYPE = str
NUM_CYCLES_13__RAW = str
LOGGER_CONF_MSG__RAW = str
MCNTRL_TILED_STATUS_REG_CHN2_ADDR__RAW = str
LAST_FRAME_BITS__RAW = str
......@@ -368,24 +367,23 @@ DIVCLK_DIVIDE = int
CMD_PAUSE_BITS__RAW = str
SENSI2C_TBL_DLY_BITS = int
IDELAY_VALUE__RAW = str
MULTICLK_PHASE_SYNC__TYPE = str
MCONTR_CMPRS_STATUS_BASE = int
BUFFER_DEPTH32 = int
SENS_CTRL_QUADRANTS__TYPE = str
SENS_LENS_BY_MASK__RAW = str
SENS_CTRL_GP0__TYPE = str
DFLT_REFRESH_ADDR = int
SENS_LENS_BX_MASK__TYPE = str
HISPI_FIFO_START__TYPE = str
TEST01_SUSPEND__RAW = str
SENS_GAMMA_HEIGHT01__TYPE = str
CMPRS_HIFREQ_REG_INC = int
STATUS_ADDR_MASK__TYPE = str
MCONTR_TOP_0BIT_ADDR_MASK__RAW = str
NUM_CYCLES_13__RAW = str
TEST01_START_FRAME = int
RTC_SET_USEC__RAW = str
LOGGER_CONF_SYN_BITS__RAW = str
CAMSYNC_ADDR__TYPE = str
DIVCLK_DIVIDE_AXIHP__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFDIV2__TYPE = str
MULT_SAXI_BSLOG1__TYPE = str
LOGGER_CONF_MSG_BITS__TYPE = str
......@@ -408,12 +406,14 @@ NUM_CYCLES_20 = int
NUM_CYCLES_21 = int
FRAME_FULL_WIDTH__TYPE = str
CAMSYNC_TRIG_DELAY2__TYPE = str
MULTICLK_BUF_DLYREF__RAW = str
CMDFRAMESEQ_REL__TYPE = str
MAX_TILE_WIDTH__RAW = str
PICKLE = str
AFI_SIZE64__TYPE = str
NUM_CYCLES_LOW_BIT__TYPE = str
MCONTR_PHY_0BIT_ADDR_MASK = int
SENSI2C_SLEW = str
DFLT_WBUF_DELAY__TYPE = str
MCNTRL_TEST01_CHN1_STATUS_CNTRL = int
SENSI2C_STATUS_REG_INC__TYPE = str
......@@ -421,9 +421,8 @@ CMPRS_FRMT_MBRM1_BITS__RAW = str
SCANLINE_EXTRA_PAGES = int
LD_DLY_LANE1_ODELAY__RAW = str
LOGGER_CONF_EN_BITS__RAW = str
DIVCLK_DIVIDE_SYNC__RAW = str
SENS_CTRL_IGNORE_EMBED__TYPE = str
SENS_LENS_FAT0_IN_MASK__TYPE = str
PHASE_CLK2X_XCLK = float
RSEL = int
CMPRS_CBIT_DCSUB_BITS__TYPE = str
AXI_RD_ADDR_BITS__TYPE = str
......@@ -435,6 +434,7 @@ CONTROL_ADDR__RAW = str
TILED_STARTY__RAW = str
CMPRS_FRMT_MBCM1_BITS__TYPE = str
SENS_CTRL_QUADRANTS_EN__RAW = str
HISPI_DELAY_CLK1__TYPE = str
NUM_CYCLES_14__TYPE = str
MCONTR_CMPRS_INC__TYPE = str
TILED_EXTRA_PAGES = int
......@@ -445,22 +445,22 @@ SENS_JTAG_TDI__RAW = str
MCONTR_SENS_STATUS_BASE = int
AXI_WR_ADDR_BITS__RAW = str
SENSI2C_CMD_RUN__TYPE = str
MULTICLK_DIV_SYNC__RAW = str
CMPRS_CORING_MODE = int
DIVCLK_DIVIDE_SYNC__TYPE = str
LOGGER_STATUS__TYPE = str
DFLT_REFRESH_PERIOD__TYPE = str
FFCLK1_IOSTANDARD = str
SENS_JTAG_TMS__TYPE = str
MCNTRL_TILED_MASK = int
MULTICLK_DIV_AXIHP = int
SENSIO_JTAG__RAW = str
MCONTR_PHY_16BIT_ADDR_MASK__RAW = str
SENSIO_STATUS__TYPE = str
CLKIN_PERIOD_AXIHP__TYPE = str
GPIO_SLEW = str
LOGGER_CONF_SYN__TYPE = str
CAMSYNC_DELAY__RAW = str
LOGGER_CONF_DBG_BITS__RAW = str
FRAME_HEIGHT_BITS__RAW = str
MCONTR_LINTILE_KEEP_OPEN = int
CLKFBOUT_MULT_SYNC = int
SENSI2C_TBL_NBRD_BITS__RAW = str
DLY_CMDA_ODELAY = long
SENS_LENS_C = int
......@@ -472,6 +472,7 @@ TABLE_HUFFMAN_INDEX = int
MCNTRL_TILED_FRAME_LAST = int
MCNTRL_TEST01_CHN2_MODE__RAW = str
CMPRS_AFIMUX_REG_ADDR0__TYPE = str
HISPI_DELAY_CLK1__RAW = str
SENSI2C_TBL_RNWREG__RAW = str
RTC_SEC_USEC_ADDR = int
LOGGER_CONF_DBG = int
......@@ -480,7 +481,6 @@ LD_DLY_LANE0_IDELAY = int
NUM_CYCLES_01__TYPE = str
NUM_CYCLES_24__TYPE = str
MCLK_PHASE__TYPE = str
DIVCLK_DIVIDE_XCLK__RAW = str
SENSI2C_DRIVE__TYPE = str
SENS_CTRL_RST_MMCM__RAW = str
MCONTR_BUF2_WR_ADDR__TYPE = str
......@@ -491,29 +491,29 @@ SENS_REF_JITTER1__RAW = str
MCNTRL_TILED_FRAME_FULL_WIDTH = int
CMDFRAMESEQ_DEPTH = int
SENS_LENS_POST_SCALE__TYPE = str
CMPRS_TABLES__TYPE = str
RTC_MHZ__RAW = str
FRAME_HEIGHT_BITS = int
HIST_SAXI_ADDR_MASK__TYPE = str
SENS_CTRL_LD_DLY = int
CLKOUT_DIV_SYNC__RAW = str
SENS_LENS_FAT0_IN_MASK__RAW = str
SENS_LENS_AY_MASK__RAW = str
MCONTR_TOP_16BIT_REFRESH_ADDRESS__TYPE = str
MCONTR_LINTILE_DIS_NEED__TYPE = str
DFLT_DQS_PATTERN__RAW = str
CMPRS_TABLES__TYPE = str
MCNTRL_PS_STATUS_CNTRL__TYPE = str
MCONTR_PHY_16BIT_ADDR = int
REF_JITTER1__TYPE = str
FFCLK1_DIFF_TERM = str
MULTICLK_PHASE_AXIHP__TYPE = str
FFCLK0_IOSTANDARD__TYPE = str
STATUS_MSB_RSHFT = int
CMPRS_CONTROL_REG__RAW = str
CLKIN_PERIOD__TYPE = str
SENS_GAMMA_CTRL = int
CLKFBOUT_MULT_AXIHP__RAW = str
HISPI_WAIT_ALL_LANES__TYPE = str
SENSIO_RADDR = int
BUF_CLK1X_PCLK__RAW = str
BUF_CLK1X_XCLK2X = str
GPIO_N__TYPE = str
MCONTR_BUF4_RD_ADDR__TYPE = str
NUM_CYCLES_16__RAW = str
......@@ -523,9 +523,10 @@ SENSIO_STATUS = int
HIST_SAXI_MODE_ADDR_REL = int
MCONTR_PHY_0BIT_SDRST_ACT__TYPE = str
BUFFER_DEPTH32__TYPE = str
CLKIN_PERIOD_AXIHP = int
CMPRS_CBIT_CMODE_JPEG18 = int
MCONTR_TOP_16BIT_REFRESH_ADDRESS = int
HISTOGRAM_RADDR0__TYPE = str
HISPI_FIFO_DEPTH__TYPE = str
LOGGER_CONF_SYN_BITS = int
NUM_CYCLES_19 = int
SENS_CTRL_GP1__TYPE = str
......@@ -534,6 +535,7 @@ SENS_CTRL_QUADRANTS_WIDTH__RAW = str
SENSOR_FIFO_DELAY__RAW = str
DLY_SET = int
CMDFRAMESEQ_CTRL__TYPE = str
HISPI_FIFO_DEPTH__RAW = str
NUM_CYCLES_12 = int
MCNTRL_SCANLINE_FRAME_PAGE_RESET__TYPE = str
MCNTRL_TILED_CHN2_ADDR__TYPE = str
......@@ -545,9 +547,9 @@ CMPRS_HIFREQ_REG_BASE__TYPE = str
SENS_HIGH_PERFORMANCE_MODE__RAW = str
MCNTRL_SCANLINE_FRAME_PAGE_RESET__RAW = str
DQTRI_LAST__TYPE = str
MULTICLK_DIVCLK__TYPE = str
DLY_DQ_ODELAY = long
BUF_IPCLK_SENS1__TYPE = str
FFCLK0_IFD_DELAY_VALUE__TYPE = str
MCONTR_TOP_16BIT_ADDR = int
CMPRS_TIMEOUT = int
HISPI_IOSTANDARD__TYPE = str
......@@ -567,7 +569,7 @@ GPIO_PORTEN__RAW = str
SLEW_CLK__TYPE = str
MCONTR_PHY_0BIT_DLY_SET = int
HISPI_DIFF_TERM__TYPE = str
SENSI2C_CMD_ACIVE_EARLY0 = int
CMPRS_CSAT_CB__RAW = str
CMD_PAUSE_BITS = int
CMPRS_CBIT_CMODE_JP4DIFFHDR__RAW = str
HISPI_IOSTANDARD__RAW = str
......@@ -587,7 +589,7 @@ DQSTRI_LAST__RAW = str
WRITELEV_OFFSET__TYPE = str
CMPRS_BASE_INC = int
MULT_SAXI_CNTRL_ADDR = int
FFCLK1_IBUF_LOW_PWR = str
MULTICLK_BUF_SYNC__TYPE = str
HIST_SAXI_ADDR_REL__RAW = str
CMPRS_CBIT_CMODE_MONO4__TYPE = str
HIST_SAXI_MODE_WIDTH__RAW = str
......@@ -610,7 +612,7 @@ CMPRS_AFIMUX_RADDR0__RAW = str
CAMSYNC_EN_BIT = int
MCONTR_PHY_16BIT_PATTERNS__RAW = str
HISTOGRAM_RAM_MODE = str
FFCLK1_DQS_BIAS__TYPE = str
SENS_REFCLK_FREQUENCY__TYPE = str
SENS_GAMMA_MODE_EN__RAW = str
SENSI2C_TBL_SA_BITS__TYPE = str
DEBUG_ADDR = int
......@@ -625,14 +627,13 @@ SENS_LENS_ADDR_MASK__RAW = str
SENS_CTRL_QUADRANTS__RAW = str
RTC_MASK__RAW = str
SENS_LENS_ADDR_MASK__TYPE = str
FFCLK0_IFD_DELAY_VALUE__RAW = str
SENS_LENS_AX__TYPE = str
PXD_DRIVE__TYPE = str
HIST_SAXI_NRESET = int
MULT_SAXI_HALF_BRAM_IN__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFHDR__TYPE = str
SENSI2C_TBL_SA__RAW = str
CMPRS_CBIT_CMODE_JP4__RAW = str
MULTICLK_BUF_AXIHP__RAW = str
DFLT_DQM_PATTERN__RAW = str
GPIO_SET_STATUS__RAW = str
SENS_JTAG_TCK = int
......@@ -641,24 +642,24 @@ REFRESH_OFFSET__TYPE = str
SENS_CTRL_ARST__RAW = str
CMPRS_CBIT_DCSUB__TYPE = str
DFLT_INV_CLK_DIV__TYPE = str
PHASE_CLK2X_XCLK__TYPE = str
MEMBRIDGE_WIDTH64__TYPE = str
SENS_GAMMA_MODE_BAYER__RAW = str
MCNTRL_PS_STATUS_REG_ADDR__TYPE = str
CMPRS_CBIT_FOCUS_BITS__TYPE = str
STATUS_ADDR__RAW = str
NUM_CYCLES_30__TYPE = str
HISPI_MMCM1__TYPE = str
SDCLK_PHASE__RAW = str
SENS_SYNC_RADDR__TYPE = str
BUF_IPCLK_SENS0__TYPE = str
SENSI2C_CMD_RUN__RAW = str
FFCLK1_IFD_DELAY_VALUE__RAW = str
SENS_GAMMA_MODE_WIDTH__TYPE = str
MCNTRL_TILED_STARTADDR__TYPE = str
DLY_LD_MASK = int
MCONTR_LINTILE_BYTE32 = int
NUM_CYCLES_09__RAW = str
SENS_SYNC_LBITS__RAW = str
MEMBRIDGE_SIZE64__TYPE = str
LOGGER_STATUS_MASK__TYPE = str
SENS_GAMMA_HEIGHT2 = int
DLY_LD_MASK__TYPE = str
STATUS_MSB_RSHFT__TYPE = str
......@@ -671,7 +672,6 @@ SENS_JTAG_TMS = int
MCNTRL_TEST01_CHN3_STATUS_CNTRL = int
MCNTRL_PS_EN_RST__TYPE = str
BUF_CLK1X_PCLK2X__TYPE = str
FFCLK1_IFD_DELAY_VALUE__TYPE = str
MCNTRL_TILED_CHN4_ADDR = int
MCONTR_SENS_INC__TYPE = str
CMPRS_CBIT_CMODE_JP46DC__TYPE = str
......@@ -701,7 +701,6 @@ NUM_CYCLES_01 = int
NUM_CYCLES_02 = int
NUM_CYCLES_03 = int
SENSIO_ADDR_MASK__TYPE = str
DIVCLK_DIVIDE_XCLK = int
NUM_CYCLES_08 = int
NUM_CYCLES_09 = int
MCNTRL_TEST01_CHN4_STATUS_CNTRL__TYPE = str
......@@ -725,7 +724,6 @@ CMPRS_CBIT_RUN_ENABLE = int
INITIALIZE_OFFSET = int
MCONTR_TOP_16BIT_CHN_EN__TYPE = str
CMPRS_CSAT_CB = int
CLKFBOUT_MULT_AXIHP__TYPE = str
VERBOSE = int
DLY_LANE1_ODELAY = long
LOGGER_PERIOD__RAW = str
......@@ -734,7 +732,6 @@ SENS_LENS_AX_MASK = int
AXI_RD_ADDR_BITS__RAW = str
RTC_BITC_PREDIV = int
SENS_SS_MOD_PERIOD__TYPE = str
BUF_CLK1X_SYNC__RAW = str
MCONTR_LINTILE_SKIP_LATE__RAW = str
SENS_JTAG_PGMEN__TYPE = str
MEMBRIDGE_LEN64__RAW = str
......@@ -755,6 +752,7 @@ CMPRS_JP4__RAW = str
CMPRS_HIFREQ_REG_BASE__RAW = str
SS_MOD_PERIOD = int
MCONTR_CMPRS_BASE__TYPE = str
FFCLK1_IBUF_LOW_PWR = str
HISPI_CAPACITANCE__TYPE = str
TEST01_SUSPEND__TYPE = str
SENS_LENS_POST_SCALE = int
......@@ -770,16 +768,16 @@ CMPRS_AFIMUX_MASK = int
DLY_PHASE = int
CONTROL_RBACK_DEPTH__RAW = str
MCONTR_LINTILE_NRESET__RAW = str
CLKOUT_DIV_XCLK2X__RAW = str
PHASE_WIDTH = int
DFLT_DQ_TRI_OFF_PATTERN__TYPE = str
MCNTRL_SCANLINE_MASK = int
CLKOUT_DIV_XCLK2X = int
MULTICLK_DIVCLK = int
MCNTRL_TILED_TILE_WHS__TYPE = str
MULT_SAXI_BSLOG3__TYPE = str
CLKFBOUT_MULT__RAW = str
CMPRS_STATUS_REG_INC__RAW = str
HISTOGRAM_RADDR0__RAW = str
HISPI_KEEP_IRST = int
STATUS_ADDR_MASK = int
PXD_CAPACITANCE = str
SENS_LENS_AY = int
......@@ -800,7 +798,7 @@ LD_DLY_LANE0_ODELAY__RAW = str
PXD_CLK_DIV_BITS__RAW = str
CMPRS_FRMT_LMARG_BITS = int
CMDSEQMUX_ADDR = int
CLKOUT_DIV_AXIHP = int
CMPRS_CBIT_CMODE_JP4DIFFHDR__TYPE = str
MCNTRL_SCANLINE_PENDING_CNTR_BITS__TYPE = str
SENSI2C_TBL_NBWR = int
DLY_DQS_IDELAY__RAW = str
......@@ -817,6 +815,7 @@ SENS_LENS_FAT0_OUT__RAW = str
HISTOGRAM_RADDR2__RAW = str
SENSI2C_STATUS = int
CMPRS_CBIT_CMODE_JP4DIFF__TYPE = str
MULTICLK_DIV_XCLK__TYPE = str
SENS_SYNC_LATE_DFLT = int
SENSI2C_STATUS_REG_BASE__RAW = str
AFI_LO_ADDR64__RAW = str
......@@ -827,8 +826,10 @@ DEBUG_LOAD__TYPE = str
MCONTR_PHY_16BIT_WBUF_DELAY = int
DLY_LANE1_DQS_WLV_IDELAY__TYPE = str
TILE_HEIGHT__RAW = str
MULTICLK_PHASE_SYNC = float
MEMBRIDGE_MODE__RAW = str
SENSI2C_TBL_SA_BITS__RAW = str
HISPI_MMCM3__RAW = str
CMPRS_CBIT_RUN_STANDALONE = int
READ_BLOCK_OFFSET__RAW = str
HISTOGRAM_LEFT_TOP__TYPE = str
......@@ -838,6 +839,7 @@ LOGGER_CONF_IMU = int
DLY_DQS_IDELAY = long
HISTOGRAM_WIDTH_HEIGHT__TYPE = str
TEST01_NEXT_PAGE = int
MULTICLK_DIV_XCLK = int
MCNTRL_TEST01_STATUS_REG_CHN4_ADDR__RAW = str
PXD_IBUF_LOW_PWR = str
NUM_CYCLES_17__TYPE = str
......@@ -850,7 +852,6 @@ CMPRS_MASK__TYPE = str
MEMBRIDGE_SIZE64__RAW = str
HISPI_IFD_DELAY_VALUE__RAW = str
MCNTRL_PS_STATUS_CNTRL = int
CLKOUT_DIV_SYNC = int
SS_MODE__TYPE = str
SENSI2C_STATUS__RAW = str
CMPRS_MASK = int
......@@ -863,14 +864,15 @@ SENS_NUM_SUBCHN__RAW = str
CMPRS_CBIT_RUN_ENABLE__RAW = str
BUF_IPCLK_SENS3__RAW = str
CLK_STATUS__RAW = str
MULTICLK_BUF_AXIHP = str
FRAME_WIDTH_BITS = int
READ_PATTERN_OFFSET__TYPE = str
MCONTR_BUF3_RD_ADDR__TYPE = str
SENS_CTRL_RST_MMCM = int
HISPI_DQS_BIAS__TYPE = str
MCONTR_CMD_WR_ADDR = int
SENSI2C_TBL_DLY_BITS__RAW = str
CMPRS_CSAT_CB__TYPE = str
CMDSEQMUX_STATUS = int
HISPI_MMCM0__TYPE = str
TILE_WIDTH = int
GPIO_MASK = int
DLY_LANE0_ODELAY = long
......@@ -893,7 +895,7 @@ MCNTRL_TEST01_STATUS_REG_CHN2_ADDR__RAW = str
CHNBUF_READ_LATENCY__TYPE = str
CMPRS_CBIT_CMODE_BITS__TYPE = str
LOGGER_BIT_DURATION__TYPE = str
RTC_MHZ__RAW = str
HISPI_MMCM1__RAW = str
TEST_INITIAL_BURST__TYPE = str
NUM_CYCLES_19__RAW = str
MCNTRL_PS_MASK__RAW = str
......@@ -909,18 +911,20 @@ SENS_GAMMA_MODE_WIDTH__RAW = str
PHASE_CLK2X_PCLK__TYPE = str
FFCLK1_DIFF_TERM__TYPE = str
MCONTR_PHY_0BIT_ADDR_MASK__TYPE = str
DIVCLK_DIVIDE_AXIHP__TYPE = str
MULT_SAXI_ADV_RD__RAW = str
SENS_SYNC_RADDR = int
T_RFC__RAW = str
WBUF_DLY_DFLT__TYPE = str
HISPI_DELAY_CLK0__RAW = str
PXD_SLEW__TYPE = str
SENSI2C_REL_RADDR__RAW = str
DEBUG_SET_STATUS__RAW = str
MCONTR_RD_MASK__RAW = str
LOGGER_CONF_EN = int
FFCLK0_CAPACITANCE = str
MULTICLK_MULT__TYPE = str
SS_EN__TYPE = str
CMDSEQMUX_STATUS = int
SENSI2C_TBL_RNWREG__TYPE = str
FRAME_START_ADDRESS_INC = int
TILED_STARTY = int
......@@ -932,11 +936,9 @@ CAMSYNC_PRE_MAGIC__RAW = str
PXD_CLK_DIV_BITS = int
SENSOR_CHN_EN_BIT = int
LD_DLY_LANE0_ODELAY = int
FFCLK1_IBUF_DELAY_VALUE__RAW = str
CMPRS_MONO16__TYPE = str
READ_PATTERN_OFFSET__RAW = str
SENSI2C_TBL_DLY__TYPE = str
SENSI2C_CMD_TAND = int
MEMBRIDGE_SIZE64 = int
MCONTR_PHY_0BIT_CKE_EN__TYPE = str
CMPRS_FRMT_MBCM1_BITS = int
......@@ -950,9 +952,9 @@ CAMSYNC_MASTER_BIT__TYPE = str
HISTOGRAM_ADDR_MASK = int
MCONTR_BUF2_RD_ADDR__RAW = str
MCONTR_TOP_16BIT_ADDR_MASK__RAW = str
MULTICLK_DIV_DLYREF__RAW = str
VERBOSE__TYPE = str
BUF_CLK1X_PCLK__TYPE = str
BUF_CLK1X_AXIHP__TYPE = str
MULT_SAXI_BSLOG1__RAW = str
CLKFBOUT_MULT_PCLK__RAW = str
MCONTR_SENS_STATUS_INC__TYPE = str
......@@ -964,6 +966,7 @@ MCNTRL_TILED_WINDOW_WH = int
CMDFRAMESEQ_MASK = int
CLK_ADDR = int
MCNTRL_TILED_WINDOW_X0Y0__TYPE = str
MULTICLK_PHASE_FB = float
NUM_XFER_BITS__RAW = str
MCNTRL_TILED_WINDOW_STARTXY__RAW = str
CMPRS_CSAT_CB_BITS__RAW = str
......@@ -977,6 +980,8 @@ GPIO_SET_PINS__RAW = str
SENS_CTRL_RST_MMCM__TYPE = str
AFI_MUX_BUF_LATENCY__RAW = str
CMPRS_CBIT_CMODE_JP46__RAW = str
MULTICLK_DIV_SYNC__TYPE = str
MULTICLK_BUF_DLYREF__TYPE = str
GPIO_DRIVE__RAW = str
GPIO_IBUF_LOW_PWR__TYPE = str
SENS_SYNC_FBITS__RAW = str
......@@ -992,7 +997,8 @@ NUM_CYCLES_02__TYPE = str
MCNTRL_TILED_STARTADDR = int
TILE_HEIGHT__TYPE = str
MCNTRL_TILED_CHN4_ADDR__TYPE = str
CMPRS_JP4 = int
HISPI_NUMLANES__TYPE = str
HISPI_FIFO_START = int
TILED_STARTX__TYPE = str
FFCLK0_DIFF_TERM__RAW = str
MCNTRL_PS_STATUS_CNTRL__RAW = str
......@@ -1003,10 +1009,11 @@ SLEW_CMDA = str
MCNTRL_SCANLINE_MODE__TYPE = str
GPIO_N__RAW = str
TEST01_NEXT_PAGE__TYPE = str
CMPRS_CBIT_CMODE_JPEG18 = int
CONTROL_RBACK_ADDR = int
T_REFI__RAW = str
MULTICLK_PHASE_SYNC__RAW = str
CLKFBOUT_MULT_SENSOR = int
HISPI_MMCM2__RAW = str
CMPRS_AFIMUX_EN = int
COLADDR_NUMBER = int
MCNTRL_TILED_STARTADDR__RAW = str
......@@ -1014,10 +1021,14 @@ TABLE_FOCUS_INDEX__TYPE = str
CAMSYNC_DELAY = int
BUF_IPCLK2X_SENS2__TYPE = str
MCNTRL_TEST01_CHN1_MODE__RAW = str
MULTICLK_PHASE_AXIHP__RAW = str
FFCLK0_IOSTANDARD__RAW = str
MULTICLK_DIV_XCLK__RAW = str
DFLT_DQS_TRI_ON_PATTERN__TYPE = str
MCONTR_PHY_0BIT_DLY_RST__TYPE = str
TILED_KEEP_OPEN__RAW = str
MULTICLK_BUF_XCLK__RAW = str
MULTICLK_BUF_XCLK__TYPE = str
MCONTR_TOP_0BIT_ADDR__TYPE = str
CLKFBOUT_PHASE_SENSOR__RAW = str
MCONTR_SENS_BASE = int
......@@ -1028,7 +1039,6 @@ STATUS_DEPTH = int
NUM_CYCLES_20__RAW = str
MCNTRL_SCANLINE_WINDOW_STARTXY__RAW = str
CAMSYNC_EXTERNAL_BIT__RAW = str
BUF_CLK1X_XCLK2X__RAW = str
MCNTRL_SCANLINE_WINDOW_X0Y0__TYPE = str
HISPI_IBUF_LOW_PWR__RAW = str
SENSI2C_TBL_NBRD__TYPE = str
......@@ -1060,7 +1070,6 @@ SENSI2C_CMD_TABLE__RAW = str
SENSIO_DELAYS__TYPE = str
ADDRESS_NUMBER__TYPE = str
WSEL__TYPE = str
FFCLK1_IBUF_DELAY_VALUE = str
CMPRS_AFIMUX_CYCBITS__RAW = str
MAX_TILE_WIDTH = int
NUM_CYCLES_09__TYPE = str
......@@ -1071,6 +1080,7 @@ NUM_CYCLES_25__RAW = str
SENSOR_NUM_HISTOGRAM__RAW = str
CMPRS_CBIT_CMODE = int
HIST_SAXI_ADDR_MASK__RAW = str
HISPI_WAIT_ALL_LANES__RAW = str
MEMBRIDGE_STATUS_REG__TYPE = str
CLKIN_PERIOD__RAW = str
SENS_SYNC_MULT__RAW = str
......@@ -1087,6 +1097,7 @@ NUM_CYCLES_08__TYPE = str
NUM_CYCLES_LOW_BIT__RAW = str
SENSI2C_TBL_NBRD_BITS__TYPE = str
SENS_SYNC_MINBITS = int
MULTICLK_BUF_DLYREF = str
MCNTRL_SCANLINE_WINDOW_STARTXY = int
BUF_IPCLK_SENS2__RAW = str
CMPRS_STATUS_CNTRL__TYPE = str
......@@ -1094,6 +1105,7 @@ MCONTR_RD_MASK = int
CMPRS_COLOR_SATURATION = int
NUM_CYCLES_21__RAW = str
NEWPAR__RAW = str
MULTICLK_PHASE_DLYREF__RAW = str
SENSIO_DELAYS__RAW = str
CMDFRAMESEQ_RUN_BIT = int
SENS_SYNC_MINPER = int
......@@ -1117,7 +1129,6 @@ CMDFRAMESEQ_ABS = int
CMPRS_MONO8 = int
MULT_SAXI_ADDR__RAW = str
DEBUG_CMD_LATENCY__TYPE = str
FFCLK1_IBUF_DELAY_VALUE__TYPE = str
TILED_KEEP_OPEN = int
MCNTRL_SCANLINE_MASK__RAW = str
MULT_SAXI_STATUS_REG__RAW = str
......@@ -1133,12 +1144,13 @@ MEMBRIDGE_CTRL__TYPE = str
TILED_KEEP_OPEN__TYPE = str
CMPRS_CBIT_RUN_RST__TYPE = str
LOGGER_CONF_GPS_BITS__RAW = str
MULTICLK_DIV_SYNC = int
CLK_STATUS_REG_ADDR = int
CLK_DIV_PHASE__TYPE = str
MULT_SAXI_BSLOG0__RAW = str
PXD_DRIVE__RAW = str
CLKFBOUT_USE_FINE_PS__RAW = str
GPIO_SET_PINS = int
CMPRS_FRMT_LMARG__RAW = str
SENSOR_CHN_EN_BIT__TYPE = str
LOGGER_BIT_DURATION = int
CAMSYNC_MODE__TYPE = str
......@@ -1157,7 +1169,6 @@ PXD_IBUF_LOW_PWR__RAW = str
PXD_DRIVE = int
MULT_SAXI_BSLOG2__RAW = str
CLK_CNTRL__TYPE = str
HISPI_NUMLANES__TYPE = str
GPIO_MASK__RAW = str
DFLT_REFRESH_ADDR__TYPE = str
SENS_GAMMA_MODE_REPET__TYPE = str
......@@ -1168,7 +1179,7 @@ MCNTRL_TEST01_STATUS_REG_CHN4_ADDR = int
LOGGER_PERIOD__TYPE = str
WSEL = int
SENS_REFCLK_FREQUENCY__RAW = str
LOGGER_STATUS_MASK__TYPE = str
MEMBRIDGE_SIZE64__TYPE = str
HISPI_IOSTANDARD = str
LOGGER_CONF_IMU__RAW = str
CMPRS_CBIT_CMODE_JP4DC__RAW = str
......@@ -1186,7 +1197,6 @@ RTC_SET_CORR__TYPE = str
PHASE_WIDTH__RAW = str
SLEW_DQ__RAW = str
CMPRS_CBIT_CMODE_JPEG20__RAW = str
FFCLK0_IBUF_DELAY_VALUE = str
CLK_STATUS = int
GPIO_ADDR__RAW = str
MEMBRIDGE_START64__TYPE = str
......@@ -1209,6 +1219,7 @@ HIST_SAXI_NRESET__RAW = str
CMPRS_COLOR18 = int
LOGGER_CONF_MSG__TYPE = str
MCNTRL_TILED_MASK__RAW = str
MULTICLK_DIV_AXIHP__RAW = str
MCNTRL_TILED_STATUS_REG_CHN2_ADDR = int
SENSI2C_STATUS_REG_BASE = int
MCNTRL_TILED_STATUS_CNTRL__RAW = str
......@@ -1250,7 +1261,6 @@ SENS_GAMMA_MODE_REPET__RAW = str
SENSOR_DATA_WIDTH = int
MCONTR_PHY_16BIT_PATTERNS_TRI__TYPE = str
SLEW_DQS__TYPE = str
DIVCLK_DIVIDE_AXIHP = int
SENSIO_ADDR_MASK = int
SCANLINE_STARTY = int
SCANLINE_STARTX = int
......@@ -1273,7 +1283,6 @@ CMPRS_CBIT_RUN_STANDALONE__TYPE = str
TILED_STARTX__RAW = str
WRITE_BLOCK_OFFSET__TYPE = str
SENS_SYNC_LATE_DFLT__TYPE = str
BUF_CLK1X_SYNC__TYPE = str
CAMSYNC_MODE = int
CLK_MASK__TYPE = str
MCNTRL_SCANLINE_STARTADDR = int
......@@ -1283,12 +1292,10 @@ MULT_SAXI_HALF_BRAM_IN__TYPE = str
DEBUG_SET_STATUS = int
MCNTRL_SCANLINE_WINDOW_X0Y0 = int
STATUS_ADDR = int
CLKOUT_DIV_XCLK = int
WINDOW_X0__RAW = str
FRAME_START_ADDRESS = int
CONTROL_ADDR__TYPE = str
CLKFBOUT_MULT_PCLK = int
DIVCLK_DIVIDE_SYNC = int
CMPRS_GROUP_ADDR = int
LOGGER_CONF_GPS_BITS__TYPE = str
SENS_LENS_AX_MASK__TYPE = str
......@@ -1308,7 +1315,8 @@ MCNTRL_TEST01_CHN2_MODE = int
MCNTRL_TILED_WINDOW_WH__TYPE = str
SS_MOD_PERIOD__RAW = str
CMPRS_NUM_AFI_CHN__RAW = str
MEMBRIDGE_WIDTH64__TYPE = str
MULTICLK_DIV_AXIHP__TYPE = str
HISPI_DELAY_CLK2__TYPE = str
MULT_SAXI_ADV_RD = int
MCNTRL_SCANLINE_FRAME_FULL_WIDTH__RAW = str
DLY_PHASE__TYPE = str
......@@ -1318,16 +1326,17 @@ BUF_IPCLK_SENS2 = str
BUF_IPCLK_SENS3 = str
BUF_IPCLK_SENS0 = str
BUF_IPCLK_SENS1 = str
FFCLK0_IFD_DELAY_VALUE = str
SENSI2C_TBL_NABRD = int
SLEW_CMDA__TYPE = str
NUM_CYCLES_19__TYPE = str
CMPRS_CORING_MODE__RAW = str
MEMBRIDGE_ADDR = int
CMPRS_CSAT_CR_BITS__RAW = str
MULTICLK_IN_PERIOD__RAW = str
CMPRS_CBIT_FOCUS = int
FFCLK1_CAPACITANCE__TYPE = str
SENSOR_FIFO_DELAY = int
MULTICLK_PHASE_AXIHP = float
MCNTRL_TEST01_CHN1_STATUS_CNTRL__TYPE = str
WBUF_DLY_DFLT = int
SENS_JTAG_PROG = int
......@@ -1337,16 +1346,17 @@ SENS_GAMMA_ADDR_MASK__RAW = str
DLY_LANE1_IDELAY__TYPE = str
SENS_LENS_BY_MASK = int
DEBUG_MASK__RAW = str
MCNTRL_TEST01_CHN2_MODE__TYPE = str
MEMBRIDGE_ADDR__RAW = str
CMPRS_COLOR_SATURATION__RAW = str
AXI_RD_ADDR_BITS = int
MULTICLK_IN_PERIOD__TYPE = str
LD_DLY_LANE1_ODELAY__TYPE = str
CMPRS_STATUS_CNTRL__RAW = str
MCONTR_LINTILE_SKIP_LATE = int
SENS_CTRL_ARO = int
LOGGER_CONF_DBG_BITS__TYPE = str
RTC_SEC_USEC_ADDR__TYPE = str
BUF_CLK1X_XCLK__RAW = str
WINDOW_X0__TYPE = str
CMPRS_CBIT_QBANK_BITS = int
MCNTRL_TEST01_CHN1_MODE = int
......@@ -1360,7 +1370,6 @@ CMPRS_CBIT_RUN_RST__RAW = str
TABLE_QUANTIZATION_INDEX = int
NUM_CYCLES_04__TYPE = str
WSEL__RAW = str
CLKOUT_DIV_XCLK__TYPE = str
SENS_CTRL_IGNORE_EMBED = int
RTC_MASK__TYPE = str
MCNTRL_TILED_PENDING_CNTR_BITS = int
......@@ -1376,7 +1385,6 @@ MCNTRL_TEST01_CHN4_STATUS_CNTRL = int
DFLT_DQM_PATTERN = int
HISPI_NUMLANES = int
SENSI2C_CMD_RUN = int
CLKOUT_DIV_AXIHP__TYPE = str
CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2__TYPE = str
NUM_CYCLES_04 = int
SENS_LENS_C__TYPE = str
......@@ -1404,12 +1412,11 @@ MEMBRIDGE_STATUS_CNTRL__TYPE = str
GPIO_IOSTANDARD__TYPE = str
CLKFBOUT_USE_FINE_PS__TYPE = str
CMPRS_FRMT_LMARG = int
FFCLK0_IBUF_DELAY_VALUE__TYPE = str
CMPRS_AFIMUX_EN__RAW = str
CMPRS_TIMEOUT__RAW = str
MEMCLK_IBUF_LOW_PWR__RAW = str
SENS_LENS_FAT0_OUT_MASK__RAW = str
SENSI2C_CMD_FIFO_RD__RAW = str
CMPRS_STATUS_REG_INC__TYPE = str
RTC_ADDR__TYPE = str
SENSI2C_ABS_RADDR = int
PXD_IOSTANDARD__RAW = str
......@@ -1423,7 +1430,6 @@ DLY_DM_ODELAY__TYPE = str
SENSIO_CTRL = int
MULT_SAXI_MASK__TYPE = str
SENSI2C_CMD_ACIVE_SDA__TYPE = str
CLKIN_PERIOD_SYNC__RAW = str
SCANLINE_STARTY__RAW = str
GPIO_ADDR = int
SENS_SYNC_MINBITS__RAW = str
......@@ -1444,7 +1450,6 @@ TABLE_FOCUS_INDEX__RAW = str
SENSOR_MODE_WIDTH__TYPE = str
MCONTR_LINTILE_WRITE__RAW = str
MCNTRL_TILED_CHN2_ADDR__RAW = str
CLKFBOUT_MULT_XCLK__RAW = str
CMPRS_CONTROL_REG__TYPE = str
SENS_CTRL_ARST__TYPE = str
CMPRS_CBIT_FOCUS__RAW = str
......@@ -1452,15 +1457,14 @@ CMPRS_MONO8__TYPE = str
NUM_CYCLES_00__RAW = str
IPCLK_PHASE__RAW = str
SENSI2C_CTRL = int
MEMCLK_IBUF_DELAY_VALUE__RAW = str
SENS_SYNC_MULT = int
CLK_ADDR__RAW = str
SENSIO_CTRL__RAW = str
MCNTRL_TILED_TILE_WHS = int
CLKOUT_DIV_XCLK__RAW = str
NUM_CYCLES_03__RAW = str
MULT_SAXI_HALF_BRAM = int
DLY_LANE1_DQS_WLV_IDELAY = long
MULTICLK_PHASE_DLYREF = float
HIST_SAXI_ADDR_REL = int
CMDFRAMESEQ_ADDR_BASE = int
CMPRS_AFIMUX_RADDR1 = int
......@@ -1472,13 +1476,10 @@ MCONTR_TOP_0BIT_ADDR = int
NUM_CYCLES_05__RAW = str
MEMBRIDGE_MODE = int
MCNTRL_TILED_FRAME_LAST__TYPE = str
MCONTR_LINTILE_DIS_NEED = int
MCONTR_CMPRS_STATUS_INC__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFHDR = int
BUF_CLK1X_SYNC = str
TABLE_CORING_INDEX__RAW = str
SENSI2C_CMD_RESET__TYPE = str
CMPRS_CBIT_CMODE_JP4DIFFDIV2__RAW = str
MCONTR_ARBIT_ADDR__TYPE = str
CAMSYNC_TRIG_DELAY1__RAW = str
ADDRESS_NUMBER = int
......@@ -1513,11 +1514,14 @@ BUFFER_DEPTH32__RAW = str
DIVCLK_DIVIDE__RAW = str
MCNTRL_PS_CMD__RAW = str
CAMSYNC_ADDR__RAW = str
CLKFBOUT_MULT_SYNC__RAW = str
MCONTR_BUF3_WR_ADDR = int
SENS_NUM_SUBCHN__TYPE = str
REFRESH_OFFSET__RAW = str
HISPI_MMCM0 = str
HISPI_MMCM3 = str
HISPI_MMCM2 = str
MULT_SAXI_CNTRL_ADDR__TYPE = str
HISPI_KEEP_IRST__TYPE = str
MULT_SAXI_STATUS_REG__TYPE = str
MEMCLK_IOSTANDARD__TYPE = str
NUM_CYCLES_27__TYPE = str
......@@ -1526,7 +1530,6 @@ CMPRS_CBIT_BAYER_BITS = int
PXD_SLEW__RAW = str
MULT_SAXI_STATUS_REG = int
CLKIN_PERIOD_SENSOR__TYPE = str
MEMCLK_IFD_DELAY_VALUE__RAW = str
SENS_LENS_BY__RAW = str
MCNTRL_PS_CMD__TYPE = str
SENS_SYNC_MASK__RAW = str
......@@ -1535,7 +1538,10 @@ SENS_CTRL_QUADRANTS_WIDTH__TYPE = str
SENSI2C_DRIVE = int
NUM_CYCLES_04__RAW = str
SENS_GAMMA_HEIGHT2__RAW = str
SENSI2C_SLEW = str
HISPI_DELAY_CLK0 = str
HISPI_DELAY_CLK1 = str
HISPI_DELAY_CLK2 = str
HISPI_DELAY_CLK3 = str
MULT_SAXI_BSLOG0__TYPE = str
DQTRI_FIRST__RAW = str
DIVCLK_DIVIDE__TYPE = str
......@@ -1543,6 +1549,7 @@ WBUF_DLY_WLV = int
MCONTR_BUF3_WR_ADDR__RAW = str
MEMBRIDGE_WIDTH64 = int
MCNTRL_TEST01_CHN3_MODE = int
MULTICLK_DIV_DLYREF = int
TABLE_HUFFMAN_INDEX__RAW = str
LD_DLY_PHASE__RAW = str
TEST_INITIAL_BURST__RAW = str
......@@ -1562,11 +1569,11 @@ DEFAULT_STATUS_MODE__TYPE = str
HISTOGRAM_LEFT_TOP = int
PHASE_CLK2X_PCLK = float
GPIO_SLEW__RAW = str
MULTICLK_PHASE_DLYREF__TYPE = str
TEST01_START_FRAME__RAW = str
CMDFRAMESEQ_ABS__RAW = str
CMPRS_AFIMUX_SA_LEN__RAW = str
BUF_IPCLK2X_SENS0__RAW = str
CLKIN_PERIOD_SYNC = int
MCONTR_BUF4_WR_ADDR__RAW = str
CLK_STATUS__TYPE = str
CMPRS_COLOR20__TYPE = str
......@@ -1579,7 +1586,7 @@ LOGGER_CONFIG__TYPE = str
MCNTRL_TEST01_MASK = int
TEST01_NEXT_PAGE__RAW = str
HIST_SAXI_MODE_ADDR_MASK__RAW = str
CMPRS_AFIMUX_EN__RAW = str
FFCLK1_IBUF_LOW_PWR__TYPE = str
MCONTR_LINTILE_EXTRAPG__TYPE = str
NUM_CYCLES_06__TYPE = str
SCANLINE_STARTX__RAW = str
......@@ -1591,7 +1598,6 @@ MCONTR_PHY_16BIT_EXTRA__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN2_ADDR__TYPE = str
MAX_TILE_HEIGHT__TYPE = str
MCONTR_TOP_16BIT_CHN_EN__RAW = str
FFCLK0_DQS_BIAS__TYPE = str
HISTOGRAM_WIDTH_HEIGHT__RAW = str
WRITELEV_OFFSET__RAW = str
READ_PATTERN_OFFSET = int
......@@ -1613,7 +1619,6 @@ MCNTRL_TILED_STATUS_REG_CHN4_ADDR__RAW = str
MCONTR_TOP_16BIT_STATUS_CNTRL__RAW = str
MCONTR_PHY_0BIT_ADDR_MASK__RAW = str
CAMSYNC_MASTER_BIT = int
CLKFBOUT_MULT_REF__RAW = str
DLY_LD_MASK__RAW = str
CMDFRAMESEQ_RST_BIT__TYPE = str
LD_DLY_LANE1_ODELAY = int
......@@ -1621,13 +1626,13 @@ CMPRS_AFIMUX_MASK__RAW = str
MCNTRL_TILED_WINDOW_X0Y0__RAW = str
SENS_GAMMA_MODE_PAGE__TYPE = str
CMPRS_COLOR_SATURATION__TYPE = str
CLKIN_PERIOD_SYNC__TYPE = str
CLKFBOUT_DIV_REF = int
SENSI2C_CMD_TAND = int
CMPRS_AFIMUX_SA_LEN = int
SENS_CTRL_QUADRANTS_EN__TYPE = str
MCNTRL_PS_EN_RST__RAW = str
HISPI_IFD_DELAY_VALUE__TYPE = str
CMPRS_CBIT_BAYER_BITS__RAW = str
MULTICLK_BUF_AXIHP__TYPE = str
GPIO_IOSTANDARD__RAW = str
MEMBRIDGE_MASK__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFDIV2 = int
......@@ -1637,7 +1642,6 @@ TILED_STARTY__TYPE = str
HIGH_PERFORMANCE_MODE__RAW = str
DFLT_DQM_PATTERN__TYPE = str
STATUS_ADDR__TYPE = str
MEMCLK_IFD_DELAY_VALUE__TYPE = str
MCONTR_PHY_0BIT_CMDA_EN = int
CMPRS_AFIMUX_WIDTH__RAW = str
BUF_CLK1X_PCLK2X = str
......@@ -1655,16 +1659,15 @@ CMD_DONE_BIT__RAW = str
DEBUG_STATUS_REG_ADDR__RAW = str
CMPRS_AFIMUX_RST__RAW = str
CAMSYNC_TRIG_DST__RAW = str
CLKIN_PERIOD_XCLK__TYPE = str
MCONTR_TOP_16BIT_REFRESH_PERIOD__TYPE = str
CAMSYNC_TRIG_DELAY3__TYPE = str
FRAME_START_ADDRESS__RAW = str
IPCLK_PHASE = float
SENSI2C_CTRL_RADDR = int
HIST_SAXI_MODE_ADDR_REL__RAW = str
CLKOUT_DIV_XCLK2X__TYPE = str
SENS_CTRL_QUADRANTS_EN = int
MCNTRL_SCANLINE_WINDOW_WH__RAW = str
MULTICLK_PHASE_FB__TYPE = str
SENSI2C_TBL_NBWR_BITS = int
BUF_IPCLK2X_SENS2 = str
BUF_IPCLK2X_SENS3 = str
......@@ -1672,6 +1675,7 @@ BUF_IPCLK2X_SENS0 = str
BUF_IPCLK2X_SENS1 = str
LOGGER_CONFIG = int
DLY_LD__RAW = str
HISPI_MMCM3__TYPE = str
NUM_CYCLES_12__TYPE = str
MCONTR_LINTILE_EXTRAPG = int
MEMCLK_IOSTANDARD = str
......@@ -1681,7 +1685,6 @@ SENSI2C_STATUS_REG_REL = int
MULT_SAXI_HALF_BRAM__TYPE = str
SENSOR_CTRL_ADDR_MASK = int
NUM_CYCLES_16__TYPE = str
DIVCLK_DIVIDE_XCLK__TYPE = str
MEMBRIDGE_LO_ADDR64__TYPE = str
CMDFRAMESEQ_MASK__RAW = str
SENS_CTRL_LD_DLY__TYPE = str
......@@ -1705,14 +1708,15 @@ CMPRS_CBIT_FRAMES_SINGLE = int
SENS_SYNC_LATE = int
CMDFRAMESEQ_CTRL__RAW = str
SENSIO_DELAYS = int
MULTICLK_BUF_SYNC = str
MCONTR_BUF0_RD_ADDR__TYPE = str
CLKIN_PERIOD_XCLK__RAW = str
CMPRS_STATUS_REG_INC__TYPE = str
DLY_LANE0_IDELAY__TYPE = str
MCNTRL_PS_ADDR__TYPE = str
WINDOW_WIDTH__RAW = str
MULTICLK_MULT__RAW = str
MCONTR_PHY_16BIT_ADDR__RAW = str
SENS_CTRL_MRST__RAW = str
BUF_CLK1X_XCLK = str
SENS_GAMMA_HEIGHT2__TYPE = str
IPCLK2X_PHASE__TYPE = str
MCNTRL_SCANLINE_CHN1_ADDR = int
......@@ -1738,6 +1742,7 @@ CAMSYNC_SNDEN_BIT__TYPE = str
DEBUG_CMD_LATENCY__RAW = str
CMPRS_CBIT_CMODE__TYPE = str
LOGGER_STATUS_MASK = int
MULTICLK_PHASE_XCLK__TYPE = str
DFLT_DQ_TRI_ON_PATTERN__RAW = str
HISPI_CAPACITANCE = str
CONTROL_ADDR_MASK = int
......@@ -1809,6 +1814,7 @@ SENS_JTAG_TCK__TYPE = str
MCNTRL_TILED_FRAME_SIZE__TYPE = str
CMPRS_AFIMUX_REG_ADDR1__RAW = str
SENS_LENS_COEFF = int
MULTICLK_PHASE_XCLK__RAW = str
LOGGER_BIT_DURATION__RAW = str
MCONTR_WR_MASK__TYPE = str
SENS_LENS_C__RAW = str
......@@ -1817,12 +1823,10 @@ SENS_GAMMA_HEIGHT01 = int
RTC_SET_SEC__RAW = str
MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__TYPE = str
SS_MODE__RAW = str
SENS_CTRL_IGNORE_EMBED__TYPE = str
MCNTRL_SCANLINE_CHN3_ADDR = int
NUM_CYCLES_26__RAW = str
DEFAULT_STATUS_MODE__RAW = str
MCONTR_LINTILE_KEEP_OPEN__RAW = str
CLKOUT_DIV_SYNC__TYPE = str
MCONTR_PHY_16BIT_ADDR__TYPE = str
CMDFRAMESEQ_RST_BIT__RAW = str
SENSIO_RADDR__RAW = str
......@@ -1832,7 +1836,6 @@ MCLK_PHASE = float
SENSI2C_SLEW__RAW = str
MCONTR_PHY_16BIT_PATTERNS_TRI__RAW = str
CMDSEQMUX_MASK = int
BUF_CLK1X_XCLK__TYPE = str
MEMCLK_CAPACITANCE__RAW = str
DQTRI_FIRST = int
DLY_LANE0_DQS_WLV_IDELAY__TYPE = str
......@@ -1856,12 +1859,13 @@ LOGGER_PAGE_MSG__RAW = str
MCONTR_TOP_16BIT_STATUS_CNTRL = int
CMPRS_CBIT_CMODE_MONO4__RAW = str
MULT_SAXI_MASK = int
SENS_LENS_BX_MASK__TYPE = str
MCNTRL_SCANLINE_WINDOW_STARTXY__TYPE = str
CMDFRAMESEQ_DEPTH__TYPE = str
DLY_LANE0_IDELAY__RAW = str
TABLE_CORING_INDEX__TYPE = str
HISTOGRAM_RADDR1__RAW = str
CLKFBOUT_DIV_REF__TYPE = str
SENSI2C_CMD_TAND__TYPE = str
MCONTR_LINTILE_EXTRAPG_BITS__RAW = str
MCNTRL_SCANLINE_MODE__RAW = str
LOGGER_BIT_HALF_PERIOD__TYPE = str
......@@ -1870,11 +1874,11 @@ MCONTR_BUF3_RD_ADDR__RAW = str
CLKIN_PERIOD = int
RSEL__TYPE = str
CMDFRAMESEQ_ADDR_INC__TYPE = str
BUF_CLK1X_XCLK2X__TYPE = str
LOGGER_CONF_GPS_BITS = int
NUM_CYCLES_07__RAW = str
HISPI_FIFO_DEPTH = int
CLKFBOUT_PHASE = float
SENS_GAMMA_ADDR_DATA = int
HISPI_WAIT_ALL_LANES = int
SENS_GAMMA_ADDR_DATA__TYPE = str
CAMSYNC_DELAY__TYPE = str
DFLT_REFRESH_PERIOD__RAW = str
......@@ -1882,7 +1886,6 @@ SENS_REF_JITTER1__TYPE = str
SENS_LENS_RADDR__RAW = str
MCONTR_PHY_0BIT_DCI_RST__TYPE = str
HISPI_DQS_BIAS__RAW = str
FFCLK1_DQS_BIAS = str
MCONTR_LINTILE_WRITE = int
TILE_VSTEP__TYPE = str
MCONTR_PHY_STATUS_CNTRL__RAW = str
......@@ -1900,6 +1903,7 @@ PHASE_CLK2X_PCLK__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN1_ADDR__TYPE = str
MCONTR_TOP_0BIT_ADDR__RAW = str
HISPI_IBUF_LOW_PWR = str
HISPI_KEEP_IRST__RAW = str
LOGGER_CONF_DBG__TYPE = str
AFI_SIZE64__RAW = str
SENSI2C_TBL_RNWREG = int
......@@ -1907,7 +1911,7 @@ STATUS_PSHIFTER_RDY_MASK = int
SENSI2C_CMD_FIFO_RD__TYPE = str
SENS_LENS_C_MASK__TYPE = str
MCNTRL_SCANLINE_FRAME_LAST__RAW = str
CLKFBOUT_DIV_REF__RAW = str
SENSI2C_CMD_ACIVE_EARLY0 = int
SENS_PHASE_WIDTH__RAW = str
SENS_REF_JITTER2__TYPE = str
FFCLK0_IBUF_LOW_PWR = str
......@@ -1932,7 +1936,6 @@ SENS_JTAG_PROG__TYPE = str
TILE_VSTEP = int
DFLT_DQS_TRI_OFF_PATTERN__TYPE = str
CAMSYNC_EN_BIT__RAW = str
BUF_CLK1X_AXIHP = str
SENSIO_WIDTH = int
MCONTR_PHY_0BIT_DLY_RST__RAW = str
BUF_CLK1X_PCLK2X__RAW = str
......@@ -1948,11 +1951,11 @@ MCNTRL_TEST01_ADDR__TYPE = str
CMPRS_STATUS_REG_BASE = int
MCONTR_LINTILE_NRESET = int
CMPRS_CBIT_RUN_BITS = int
MEMCLK_IFD_DELAY_VALUE = str
SENS_LENS_AY_MASK = int
BUF_IPCLK2X_SENS3__RAW = str
MCNTRL_SCANLINE_CHN1_ADDR__RAW = str
MEMBRIDGE_LEN64 = int
HISPI_MMCM2__TYPE = str
SENSOR_NUM_HISTOGRAM__TYPE = str
HIST_SAXI_EN = int
RTC_SET_SEC = int
......@@ -1963,20 +1966,20 @@ CMPRS_MONO16 = int
REF_JITTER1 = float
SENSI2C_TBL_DLY = int
SENSIO_STATUS__RAW = str
CLKIN_PERIOD_AXIHP__RAW = str
MCONTR_LINTILE_DIS_NEED = int
SENS_LENS_BX_MASK = int
HISPI_FIFO_START__RAW = str
DLY_DQ_ODELAY__RAW = str
MCNTRL_TILED_PENDING_CNTR_BITS__RAW = str
CMPRS_CORING_BITS = int
CMDFRAMESEQ_MASK__TYPE = str
SENS_JTAG_TMS__TYPE = str
FFCLK1_IOSTANDARD = str
CLK_PHASE__RAW = str
MCONTR_PHY_0BIT_DLY_RST = int
GPIO_MASK__TYPE = str
MULT_SAXI_BSLOG2__TYPE = str
TILED_STARTX = int
MEMBRIDGE_MASK__TYPE = str
FFCLK1_DQS_BIAS__RAW = str
SENS_GAMMA_MODE_EN = int
MCONTR_BUF3_RD_ADDR = int
NUM_CYCLES_28__TYPE = str
......@@ -1989,9 +1992,10 @@ SENS_GAMMA_BUFFER = int
CMDFRAMESEQ_ABS__TYPE = str
NUM_CYCLES_06__RAW = str
SENS_JTAG_TDI = int
CLKFBOUT_MULT_AXIHP = int
CMPRS_JP4 = int
CAMSYNC_CHN_EN_BIT = int
SENSIO_STATUS_REG_REL__TYPE = str
MULTICLK_BUF_XCLK = str
MCNTRL_SCANLINE_MODE = int
DLY_LANE0_IDELAY = long
MCNTRL_PS_CMD = int
......@@ -2000,8 +2004,8 @@ MCNTRL_SCANLINE_CHN3_ADDR__TYPE = str
STATUS_2LSB_SHFT__RAW = str
STATUS_MSB_RSHFT__RAW = str
SLEW_CMDA__RAW = str
HISPI_MMCM0__RAW = str
MCONTR_PHY_16BIT_PATTERNS_TRI = int
GPIO_SLEW = str
MCONTR_TOP_STATUS_REG_ADDR__RAW = str
DFLT_DQS_TRI_ON_PATTERN = int
SENSI2C_REL_RADDR = int
......@@ -2015,20 +2019,18 @@ CAMSYNC_TRIG_SRC__TYPE = str
SENSI2C_CMD_FIFO_RD = int
LOGGER_CONF_IMU__TYPE = str
DEBUG_READ_REG_ADDR__RAW = str
PHASE_CLK2X_XCLK__RAW = str
SENS_LENS_AY__RAW = str
SS_EN = str
CLKFBOUT_MULT_XCLK = int
SENSI2C_CMD_TAND__RAW = str
WINDOW_HEIGHT__TYPE = str
IBUF_LOW_PWR__TYPE = str
FFCLK1_IBUF_LOW_PWR__TYPE = str
CLK_DIV_PHASE = float
MCNTRL_TEST01_CHN4_STATUS_CNTRL__RAW = str
MCONTR_PHY_16BIT_ADDR_MASK__TYPE = str
SENS_CTRL_ARO__RAW = str
BUF_IPCLK2X_SENS0__TYPE = str
MULTICLK_BUF_SYNC__RAW = str
MCONTR_PHY_0BIT_DLY_SET__RAW = str
CLKIN_PERIOD_XCLK = int
NUM_CYCLES_11__RAW = str
FFCLK1_CAPACITANCE__RAW = str
SENSI2C_DRIVE__RAW = str
......@@ -2055,24 +2057,24 @@ CMPRS_BASE_INC__TYPE = str
SENSI2C_CMD_ACIVE__TYPE = str
NUM_FRAME_BITS__TYPE = str
CLKFBOUT_MULT_SENSOR__TYPE = str
CLKFBOUT_MULT_REF__TYPE = str
SENSI2C_TBL_SA = int
SENSI2C_CTRL_MASK__RAW = str
CLK_CNTRL = int
SENSI2C_TBL_NABRD__RAW = str
BUF_CLK1X_AXIHP__RAW = str
MULTICLK_PHASE_XCLK = float
LOGGER_ADDR__TYPE = str
NUM_CYCLES_15__TYPE = str
MCNTRL_TILED_MODE__RAW = str
CLKOUT_DIV_AXIHP__RAW = str
NUM_CYCLES_23__TYPE = str
MCNTRL_TILED_MODE__TYPE = str
MULTICLK_IN_PERIOD = int
MCONTR_TOP_0BIT_MCONTR_EN__RAW = str
MULTICLK_PHASE_FB__RAW = str
TABLE_HUFFMAN_INDEX__TYPE = str
RTC_SET_STATUS__RAW = str
SENS_CTRL_QUADRANTS = int
LD_DLY_PHASE__TYPE = str
MEMCLK_IBUF_DELAY_VALUE = str
CMPRS_CBIT_CMODE_JP4DIFFDIV2__RAW = str
MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR__TYPE = str
CMDSEQMUX_MASK__RAW = str
DFLT_WBUF_DELAY = int
......@@ -2083,7 +2085,7 @@ MULT_SAXI_ADV_WR__TYPE = str
CMPRS_AFIMUX_STATUS_CNTRL__RAW = str
FRAME_FULL_WIDTH = int
CMPRS_AFIMUX_REG_ADDR0__RAW = str
CMPRS_FRMT_LMARG__RAW = str
GPIO_SET_PINS = int
NUM_CYCLES_22__TYPE = str
DLY_PHASE__RAW = str
MCONTR_SENS_INC__RAW = str
......@@ -2092,7 +2094,6 @@ TILE_WIDTH__RAW = str
CMPRS_FORMAT__RAW = str
RTC_MASK = int
CLKIN_PERIOD_SENSOR = float
MEMCLK_IBUF_DELAY_VALUE__TYPE = str
SENS_GAMMA_CTRL__TYPE = str
HIST_CONFIRM_WRITE__RAW = str
SENS_CTRL_ARST = int
......@@ -2102,7 +2103,6 @@ CMDFRAMESEQ_DEPTH__RAW = str
SENS_LENS_BX_MASK__RAW = str
SENSI2C_TBL_NBWR_BITS__RAW = str
WRITE_BLOCK_OFFSET__RAW = str
FFCLK0_DQS_BIAS__RAW = str
MCONTR_LINTILE_SINGLE__RAW = str
MCNTRL_TILED_FRAME_PAGE_RESET__RAW = str
SENS_GAMMA_BUFFER__TYPE = str
......@@ -2110,8 +2110,8 @@ SLEW_DQ__TYPE = str
MCONTR_BUF4_RD_ADDR = int
MCNTRL_PS_MASK__TYPE = str
DIVCLK_DIVIDE_PCLK__RAW = str
HISPI_DELAY_CLK3__TYPE = str
MCONTR_LINTILE_BYTE32__TYPE = str
FFCLK1_IFD_DELAY_VALUE = str
CMPRS_TABLES__RAW = str
SENS_GAMMA_MODE_EN__TYPE = str
FRAME_START_ADDRESS__TYPE = str
......@@ -2127,7 +2127,6 @@ NUM_CYCLES_05__TYPE = str
MCNTRL_TILED_PENDING_CNTR_BITS__TYPE = str
SENSI2C_TBL_NBWR__TYPE = str
AXI_WR_ADDR_BITS = int
CLKFBOUT_MULT_XCLK__TYPE = str
FFCLK1_IBUF_LOW_PWR__RAW = str
MCONTR_LINTILE_REPEAT__RAW = str
MCONTR_TOP_16BIT_REFRESH_PERIOD = int
......@@ -2140,10 +2139,10 @@ RTC_SEC_USEC_ADDR__RAW = str
MCNTRL_PS_ADDR = int
SENS_BANDWIDTH = str
MEMCLK_IBUF_LOW_PWR = str
HISPI_DELAY_CLK3__RAW = str
CAMSYNC_TRIG_DST__TYPE = str
CMPRS_AFIMUX_RADDR1__TYPE = str
MCONTR_PHY_STATUS_CNTRL__TYPE = str
SENS_LENS_AY__RAW = str
MULT_SAXI_WLOG = int
DLY_CMDA_ODELAY__RAW = str
SENSOR_GROUP_ADDR__TYPE = str
......@@ -2173,6 +2172,7 @@ CMPRS_CBIT_CMODE_MONO1 = int
CMPRS_CBIT_CMODE_MONO6 = int
SENS_SS_EN = str
CMPRS_CBIT_CMODE_MONO4 = int
HISPI_DELAY_CLK2__RAW = str
SS_MOD_PERIOD__TYPE = str
TILE_HEIGHT = int
MULT_SAXI_MASK__RAW = str
......
py393/x393_axi_control_status.py
View file @ 944ff196
......@@ -173,6 +173,9 @@ class X393AxiControlStatus(object):
{FILE:"vccint", ITEM:"VCCint", UNITS:"V", SCALE: 0.001},
{FILE:"vccbram", ITEM:"VCCbram", UNITS:"V", SCALE: 0.001}]
print("hwmon:")
if self.DRY_MODE:
print ("Not defined for simulation mode")
return
for par in HWMON_ITEMS:
with open(HWMON_PATH + par[FILE]) as f:
d=int(f.read())
......
py393/x393_cmprs.py
View file @ 944ff196
......@@ -279,6 +279,8 @@ class X393Cmprs(object):
window_top,
byte32,
tile_width,
tile_vstep, # = 16
tile_height, #= 18
extra_pages,
disable_need):
"""
......@@ -294,13 +296,16 @@ class X393Cmprs(object):
@param window_top - 16-bit window top margin (in scan lines
@param byte32 - 32-byte columns
@param tile_width tile width,
@param tile_vstep tile vertical step in pixel rows (JPEG18/jp4 = 16)
@param tile_height tile height: 18 for color JPEG, 16 fore JP$ flavors,
@param extra_pages extra pages needed (1)
@param disable_need disable need (preference to sensor channels - they can not wait
"""
tile_vstep = 16
tile_height= 18
# tile_vstep = 16
# tile_height= 18
base_addr = vrlg.MCONTR_CMPRS_BASE + vrlg.MCONTR_CMPRS_INC * num_sensor;
mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = False,
disable_need = disable_need,
repetitive= True,
single = False,
......@@ -351,7 +356,7 @@ class X393Cmprs(object):
# run_mode = run_mode) #0 - reset, 2 - run single from memory, 3 - run repetitive
def setup_compressor_channel (self,
num_sensor,
chn,
qbank,
dc_sub,
cmode,
......@@ -366,7 +371,7 @@ class X393Cmprs(object):
coring,
verbose=0):
"""
@param num_sensor - sensor port number (0..3)
@param chn - compressor channel (0..3)
@param qbank - quantization table page (0..15)
@param dc_sub - True - subtract DC before running DCT, False - no subtraction, convert as is,
@param cmode - color mode:
......@@ -396,7 +401,7 @@ class X393Cmprs(object):
"""
if verbose > 0:
print("COMPRESSOR_SETUP")
print ( "num_sensor = ",num_sensor)
print ( "num_sensor = ",chn)
print ( "qbank = ",qbank)
print ( "dc_sub = ",dc_sub)
print ( "cmode = ",cmode)
......@@ -404,27 +409,27 @@ class X393Cmprs(object):
print ( "bayer = ",bayer)
print ( "focus_mode = ",focus_mode)
self.compressor_control(
chn = num_sensor, # sensor channel number (0..3)
chn = chn, # compressor channel number (0..3)
qbank = qbank, # [6:3] quantization table page
dc_sub = dc_sub, # [8:7] subtract DC
cmode = cmode, # [13:9] color mode:
multi_frame = multi_frame, # [15:14] 0 - single-frame buffer, 1 - multiframe video memory buffer
bayer = bayer, # [20:18] # Bayer shift
focus_mode = focus_mode) # [23:21] Set focus mode
focus_mode = focus_mode) # [23:21] Set focus mode
self.compressor_format(
chn = num_sensor, # sensor channel number (0..3)
chn = chn, # compressor channel number (0..3)
num_macro_cols_m1 = num_macro_cols_m1, # number of macroblock colums minus 1
num_macro_rows_m1 = num_macro_rows_m1, # number of macroblock rows minus 1
left_margin = left_margin) # left margin of the first pixel (0..31) for 32-pixel wide colums in memory access
self.compressor_color_saturation(
chn = num_sensor, # sensor channel number (0..3)
chn = chn, # compressor channel number (0..3)
colorsat_blue = colorsat_blue, # color saturation for blue (10 bits) #'h90 for 100%
colorsat_red = colorsat_red) # color saturation for red (10 bits) # 'b6 for 100%
colorsat_red = colorsat_red) # color saturation for red (10 bits) # 'b6 for 100%
self.compressor_coring(
chn = num_sensor, # sensor channel number (0..3)
chn = chn, # compressor channel number (0..3)
coring = coring); # coring value
py393/x393_cmprs_afi.py
View file @ 944ff196
......@@ -110,8 +110,9 @@ class X393CmprsAfi(object):
@param channel - AFI input channel (0..3) - with 2 AFIs - 0..1 only
@return - memory segments (1 or two) with image data, timestamp in numeric and string format
"""
print ("\n------------ channel %d --------------"%(channel))
print ("x393_sens_cmprs.GLBL_WINDOW = ", x393_sens_cmprs.GLBL_WINDOW)
if verbose >0:
print ("\n------------ channel %d --------------"%(channel))
print ("x393_sens_cmprs.GLBL_WINDOW = ", x393_sens_cmprs.GLBL_WINDOW)
if (self.DRY_MODE):
return None
CCAM_MMAP_META = 12 # extra bytes included at the end of each frame (last aligned to 32 bytes)
......@@ -123,14 +124,37 @@ class X393CmprsAfi(object):
# offs_len32 = 0x20 - CCAM_MMAP_META_LENGTH # 0x1c #from last image 32-byte chunk to lower of 3-byte image length (MSB == 0xff)
next_image = self.afi_mux_get_image_pointer(port_afi = port_afi,
channel = channel)
# Bug - got 0x20 more than start of the new image
last_image_chunk = next_image - 0x40
if last_image_chunk < 0:
last_image_chunk += circbuf_len
len32 = self.x393_mem.read_mem(cirbuf_start + last_image_chunk + (0x20 - CCAM_MMAP_META_LENGTH))
markerFF = len32 >> 24
if (markerFF != 0xff):
print ("Failed to get 0xff marker at offset 0x%08x - length word = 0x%08x)"%(cirbuf_start + last_image_chunk + (0x20 - CCAM_MMAP_META_LENGTH) + 3,len32))
return None
print ("Failed to get 0xff marker at offset 0x%08x - length word = 0x%08x, next_image = 0x%08x)"%
(cirbuf_start + last_image_chunk + (0x20 - CCAM_MMAP_META_LENGTH) + 3,len32,next_image))
if verbose >0:
for a in range ( next_image - (0x10 * num_lines_print), next_image + (0x10 * num_lines_print), 4):
d = self.x393_mem.read_mem(cirbuf_start + a)
if (a % 16) == 0:
print ("\n%08x: "%(a),end ="" )
print("%02x %02x %02x %02x "%(d & 0xff, (d >> 8) & 0xff, (d >> 16) & 0xff, (d >> 24) & 0xff), end = "")
#Try noticed (but not yet identified) bug - reduce afi_mux_get_image_pointer result by 1
next_image -= 0x20
if next_image < 0:
next_image += circbuf_len
last_image_chunk = next_image - 0x40
if last_image_chunk < 0:
last_image_chunk += circbuf_len
len32 = self.x393_mem.read_mem(cirbuf_start + last_image_chunk + (0x20 - CCAM_MMAP_META_LENGTH))
markerFF = len32 >> 24
if (markerFF != 0xff):
print ("**** Failed to get 0xff marker at CORRECTED offset 0x%08x - length word = 0x%08x, next_image = 0x%08x)"%
(cirbuf_start + last_image_chunk + (0x20 - CCAM_MMAP_META_LENGTH) + 3,len32,next_image))
return None
if verbose >0:
print ("\n-----------reduced next frame byte pointer by 0x20 -------------")
len32 &= 0xffffff
# inserted_bytes = (32 - (((len32 % 32) + CCAM_MMAP_META) % 32)) % 32
#adjusting to actual...
......@@ -174,10 +198,10 @@ class X393CmprsAfi(object):
"segments":segments}
if verbose >0 :
print ("Inserted bytes after image before meta = 0x%x"%(inserted_bytes))
print ("Image start (relative to cirbuf) = 0x%x"%(img_start))
print ("Image start (relative to cirbuf) = 0x%x, image length = 0x%x"%(img_start, len32 ))
print ("Image time stamp = %s (%f)"%(tstr, fsec))
for s in segments:
print ("start_address = 0x%x, length = 0x%x"%(s[0],s[1]))
for i,s in enumerate(segments):
print ("segment %d: start_address = 0x%x, length = 0x%x"%(i, s[0],s[1]))
return result
......
py393/x393_jpeg.py
View file @ 944ff196
......@@ -39,8 +39,11 @@ import x393_axi_control_status
import x393_utils
#import time
import x393_sens_cmprs
import x393_sensor
import x393_cmprs
import x393_cmprs_afi
import vrlg
import time
STD_QUANT_TBLS = {
"Y_landscape":( 16, 11, 10, 16, 24, 40, 51, 61,
12, 12, 14, 19, 26, 58, 60, 55,
......@@ -162,7 +165,8 @@ class X393Jpeg(object):
x393_utils=None
x393_cmprs_afi = None
x393_sens_cmprs = None
x393Sensor = None
x393Cmprs = None
verbose=1
def __init__(self, debug_mode=1,dry_mode=True, saveFileName=None):
self.DEBUG_MODE= debug_mode
......@@ -173,6 +177,8 @@ class X393Jpeg(object):
self.x393_cmprs_afi = x393_cmprs_afi.X393CmprsAfi(debug_mode,dry_mode)
self.x393_utils= x393_utils.X393Utils(debug_mode,dry_mode, saveFileName) # should not overwrite save file path
self.x393_sens_cmprs = x393_sens_cmprs.X393SensCmprs(debug_mode,dry_mode, saveFileName)
self.x393Sensor = x393_sensor.X393Sensor(debug_mode,dry_mode, saveFileName)
self.x393Cmprs = x393_cmprs.X393Cmprs(debug_mode,dry_mode, saveFileName)
try:
self.verbose=vrlg.VERBOSE
......@@ -416,7 +422,7 @@ class X393Jpeg(object):
portrait = False,
height = 1936,
width = 2592,
color_mode = 0,
color_mode = vrlg.CMPRS_CBIT_CMODE_JPEG18,
byrshift = 0,
verbose = 1):
"""
......@@ -627,13 +633,142 @@ class X393Jpeg(object):
return {"header":buf,
"quantization":qtables["fpga"],
"huffman": self.huff_tables[FPGA_HUFFMAN_TABLE]}
def jpeg_acquire_write(self,
file_path = "img.jpeg",
channel = 0,
cmode = None, # vrlg.CMPRS_CBIT_CMODE_JPEG18, # read it from the saved
bayer = None,
y_quality = None,
c_quality = None,
portrait = None,
gamma = None, # 0.57,
black = None, # 0.04,
colorsat_blue = None, # 2.0, colorsat_blue, #0x180 # 0x90 for 1x
colorsat_red = None, # 2.0, colorsat_red, #0x16c, # 0xb6 for x1
server_root = "/www/pages/",
verbose = 1):
"""
Acquire JPEG/JP4 image(s), wait completion, create file(s)
@param file_path - camera file system path (starts with "/") or relative to web server root
@param channel - compressor channel
@param cmode - 0: color JPEG, 5 - JP4
@param bayer - Bayer shift
@param y_quality - 1..100 - quantization quality for Y component
@param c_quality - 1..100 - quantization quality for color components ("same" - use y_quality)
@param portrait - False - use normal order, True - transpose for portrait mode images
@param gamma - gamma value (1.0 - linear)
@param black - black level, 1.0 corresponds to 256 for 8bit values
@param colorsat_blue - color saturation for blue (10 bits), 0x90 for 100%
@param colorsat_red - color saturation for red (10 bits), 0xb6 for 100%
@param server_root - files ystem path to the web server root directory
@param verbose - verbose level
"""
window = self.x393_sens_cmprs.specify_window(verbose = verbose) # will be updated if more parameters are specified
#First update quality/portrait/compression mode
if (y_quality is not None) or (c_quality is not None) or (portrait is not None):
window = self.x393_sens_cmprs.specify_window(y_quality= y_quality,
c_quality = c_quality,
portrait = portrait,
verbose = verbose)
self.set_qtables(chn = channel,
index = 0, # index of a table pair
y_quality = window["y_quality"],
c_quality = window["c_quality"],
portrait = window["portrait"],
verbose = verbose)
# recalculate gamma if needed with program_gamma
if (gamma is not None) or (black is not None):
window = self.x393_sens_cmprs.specify_window(gamma= gamma,
black = black)
self.x393Sensor.program_gamma (num_sensor = channel,
sub_channel = 0,
gamma = window["gamma"],
black = window["black"],
page = 0)
# Update compressor settings if needed setup_compressor
if (cmode is not None) or (bayer is not None) or (colorsat_blue is not None) or (colorsat_red is not None):
window = self.x393_sens_cmprs.specify_window(cmode= cmode,
bayer = bayer,
colorsat_blue = colorsat_blue,
colorsat_red = colorsat_red,
verbose = verbose)
self.x393_sens_cmprs.setup_compressor(chn = channel, # All
cmode = window["cmode"],
bayer = window["bayer"],
qbank = 0,
dc_sub = 1,
multi_frame = 1,
focus_mode = 0,
coring = 0,
window_width = window["width"], #None, # 2592, # 2592
window_height = window["height"], #None, # 1944, # 1944
window_left = window["left"], #None, # 0, # 0
window_top = window["top"], #None, # 0, # 0? 1?
last_buf_frame = 1, # - just 2-frame buffer
colorsat_blue = min(int(round(window["colorsat_blue"]*0x90)),1023),
colorsat_red = min(int(round(window["colorsat_red"]*0xb6)),1023),
verbose = verbose)
# read and save image pointer for each channel (report mode/status should be configured appropriately) afi_mux_get_image_pointer
old_pointers=[]
for i in range(4):
old_pointers.append(self.x393_cmprs_afi.afi_mux_get_image_pointer(
port_afi= 0,
channel = i))
#start single-frame acquisition (on each channel)
self.x393Cmprs.compressor_control(chn = channel,
run_mode = 2)
#Wait with timeout for all enabled images
channel_mask = [False, False, False, False]
try:
if (channel == all) or (channel[0].upper() == "A"): #all is a built-in function
for i in range(4):
channel_mask[i]=True
else:
channel_mask[int(channel)]=True
except:
channel_mask[int(channel)]=True
now = time.time()
timeout_time = now + 1.0 #seconds
#print("channel_mask = ",channel_mask, "channel = ",channel )
while time.time() < timeout_time:
allNew = True;
for i, en in enumerate(channel_mask):
if en:
if self.x393_cmprs_afi.afi_mux_get_image_pointer(port_afi= 0, channel = i) == old_pointers[i]: # frame pointer is not updated
allNew = False;
break;
if allNew: # all selected channels have updated frame pointers
break
numChannels=0;
for en in channel_mask:
if en:
numChannels+=1
#Now generate JPEG/JP4 file
self.jpeg_write(file_path = file_path,
channel = channel,
y_quality = window["y_quality"],
c_quality = window["c_quality"],
portrait = window["portrait"],
byrshift = window["bayer"],
server_root = server_root,
verbose = verbose)
if verbose > 0:
self.x393_sens_cmprs.specify_window(verbose = 2)
return numChannels
def jpeg_write(self,
file_path = "img.jpeg",
channel = 0,
y_quality = 100, #80,
c_quality = None,
portrait = False,
color_mode = 0,
# color_mode = None, # vrlg.CMPRS_CBIT_CMODE_JPEG18, # read it from the saved
byrshift = 0,
server_root = "/www/pages/",
verbose = 1):
......@@ -644,7 +779,6 @@ class X393Jpeg(object):
@param y_quality - 1..100 - quantization quality for Y component
@param c_quality - 1..100 - quantization quality for color components (None - use y_quality)
@param portrait - False - use normal order, True - transpose for portrait mode images
@param color_mode - one of the image formats (jpeg, jp4,)
@param byrshift - Bayer shift
@param server_root - files ystem path to the web server root directory
@param verbose - verbose level
......@@ -657,6 +791,11 @@ class X393Jpeg(object):
allFiles = True
except:
pass
window = self.x393_sens_cmprs.specify_window(verbose = verbose)
if window["cmode"] == vrlg.CMPRS_CBIT_CMODE_JP4:
file_path = file_path.replace(".jpeg",".jp4")
elif window["cmode"] == vrlg.CMPRS_CBIT_CMODE_JP46:
file_path = file_path.replace(".jpeg",".jp46")
if allFiles:
html_text = """
<html>
......@@ -689,7 +828,7 @@ class X393Jpeg(object):
y_quality = y_quality, #80,
c_quality = c_quality,
portrait = portrait,
color_mode = color_mode,
color_mode = window["cmode"], #
byrshift = byrshift,
verbose = verbose)
html_text += html_text_finish
......@@ -705,14 +844,18 @@ class X393Jpeg(object):
with open (server_root+html_name, "w+b") as bf:
bf.write(html_text)
return
if verbose > 0 :
print ("window[height]",window["height"])
print ("window[width]",window["width"])
print ("window[cmode]",window["cmode"])
print ("window=",window)
jpeg_data = self.jpegheader_create (
y_quality = y_quality,
c_quality = c_quality,
portrait = portrait,
height = x393_sens_cmprs.GLBL_WINDOW["height"] & 0xfff0,
width = x393_sens_cmprs.GLBL_WINDOW["width"] & 0xfff0,
color_mode = color_mode,
height = window["height"] & 0xfff0, # x393_sens_cmprs.GLBL_WINDOW["height"] & 0xfff0,
width = window["width"] & 0xfff0, # x393_sens_cmprs.GLBL_WINDOW["width"] & 0xfff0,
color_mode = window["cmode"], #color_mode,
byrshift = byrshift,
verbose = verbose - 1)
meta = self.x393_cmprs_afi.afi_mux_get_image_meta(
......@@ -720,14 +863,17 @@ class X393Jpeg(object):
channel = channel,
cirbuf_start = x393_sens_cmprs.GLBL_CIRCBUF_STARTS[channel],
circbuf_len = x393_sens_cmprs.GLBL_CIRCBUF_CHN_SIZE,
verbose = 1)
print ("meta = ",meta)
for s in meta["segments"]:
print ("start_address = 0x%x, length = 0x%x"%(s[0],s[1]))
verbose = verbose)
if verbose > 0 :
print ("meta = ",meta)
if verbose > 1 :
for s in meta["segments"]:
print ("start_address = 0x%x, length = 0x%x"%(s[0],s[1]))
with open (server_root+file_path, "w+b") as bf:
bf.write(jpeg_data["header"])
for s in meta["segments"]:
print ("start_address = 0x%x, length = 0x%x"%(s[0],s[1]))
if verbose > 1 :
print ("start_address = 0x%x, length = 0x%x"%(s[0],s[1]))
self.x393_mem._mem_write_to_file (bf = bf,
start_addr = s[0],
length = s[1])
......@@ -819,6 +965,75 @@ class X393Jpeg(object):
ff d9
"""
"""
JP46: demuxing...
Corrupt JPEG data: bad Huffman code
Corrupt JPEG data: bad Huffman code
Corrupt JPEG data: bad Huffman code
#should be no MSB first (0x31c68400)
cd /usr/local/verilog/; test_mcntrl.py @hargs
measure_all "*DI"
setup_all_sensors True None 0xf
#compressor_control all None None None None None 3
#set_sensor_hispi_lanes 0 1 2 3 0
compressor_control all None None None None None 2
program_gamma all 0 0.57 0.04
write_sensor_i2c 0 1 0 0x030600b4
print_sensor_i2c 0 0x306 0xff 0x10 0
print_sensor_i2c 0 0x303a 0xff 0x10 0
print_sensor_i2c 0 0x301a 0xff 0x10 0
print_sensor_i2c 0 0x31c6 0xff 0x10 0
write_sensor_i2c 0 1 0 0x31c68400
print_sensor_i2c 0 0x31c6 0xff 0x10 0
print_sensor_i2c 0 0x306e 0xff 0x10 0
write_sensor_i2c 0 1 0 0x306e9280
#test pattern - 100% color bars
write_sensor_i2c 0 1 0 0x30700002
#test pattern - fading color bars
write_sensor_i2c 0 1 0 0x30700003
print_sensor_i2c 0 0x3070 0xff 0x10 0
#test - running 8, 8-bit
write_sensor_i2c 0 1 0 0x30700101
#default gain = 0xa, set red and blue (outdoors)
write_sensor_i2c 0 1 0 0x3028000a
write_sensor_i2c 0 1 0 0x302c000d
write_sensor_i2c 0 1 0 0x302e0010
#default gain = 0xa, set red and blue (indoors)
write_sensor_i2c 0 1 0 0x3028000a
write_sensor_i2c 0 1 0 0x302c000b
write_sensor_i2c 0 1 0 0x302e0010
#Exposure 0x800 lines
write_sensor_i2c 0 1 0 0x30120800
write_sensor_i2c 0 1 0 0x301a001c
print_sensor_i2c 0 0x31c6 0xff 0x10 0
compressor_control 0 2
jpeg_write "img.jpeg" 0
#setup JP4
setup_compressor 0 5 2 0 1 1 0 0 None None None None 1 384 364 2
#setup JPEG
setup_compressor 0 0 2 0 1 1 0 0 None None None None 1 384 364 2
#default gain = 0xa, set red and blue (outdoors)
write_sensor_i2c 0 1 0 0x30280014
write_sensor_i2c 0 1 0 0x302c001a
write_sensor_i2c 0 1 0 0x302e0020
write_sensor_i2c 0 1 0 0x3028001e
write_sensor_i2c 0 1 0 0x302c0021
write_sensor_i2c 0 1 0 0x302e0030
Camera compressors testing sequence
cd /usr/local/verilog/; test_mcntrl.py @hargs
#or (for debug)
......@@ -1001,6 +1216,10 @@ jpeg_write "img.jpeg" all
write_sensor_i2c 0 1 0 0x91900004
print_sensor_i2c 0
print_debug 0x8 0xb
#Set "MSB first"and packet mode
write_sensor_i2c 0 1 0 0x31c60402
#r
add hwmon:
......@@ -1019,5 +1238,15 @@ root@elphel393:/sys/devices/amba.0/f8007100.ps7-xadc# cat /sys/devices/amba.0/f8
root@elphel393:/sys/devices/amba.0/f8007100.ps7-xadc# cat /sys/devices/amba.0/f8007100.ps7-xadc/vccint
966
write_sensor_i2c 0 1 0 0xff200000
print_sensor_i2c 0
#set JP46
compressor_control all None None None 2
#JP4
compressor_control all None None None 5
#JPEG
compressor_control all None None None 0
"""
py393/x393_mcntrl.py
View file @ 944ff196
......@@ -40,7 +40,8 @@ __status__ = "Development"
#import time
import vrlg
def func_encode_mode_scan_tiled (disable_need = False,
def func_encode_mode_scan_tiled (skip_too_late = False,
disable_need = False,
repetitive= True,
single = False,
reset_frame = False,
......@@ -52,6 +53,7 @@ def func_encode_mode_scan_tiled (disable_need = False,
chn_reset = False):
"""
Combines arguments to create a 12-bit encoded data for scanline mode memory R/W
@param skip_too_late - Skip over missed blocks to preserve frame structure (increment pointers),
@param disable_need - disable 'need' generation, only 'want' (compressor channels),
@param repetitive - run repetitive frames (add this to older 'master' tests)
@param single - run single frame
......@@ -66,17 +68,18 @@ def func_encode_mode_scan_tiled (disable_need = False,
"""
rslt = 0;
rslt |= (1,0)[chn_reset] << vrlg.MCONTR_LINTILE_EN # inverted
rslt |= (0,1)[enable] << vrlg.MCONTR_LINTILE_NRESET
rslt |= (0,1)[write_mem] << vrlg.MCONTR_LINTILE_WRITE
rslt |= (extra_pages & ((1 << vrlg.MCONTR_LINTILE_EXTRAPG_BITS) - 1)) << vrlg.MCONTR_LINTILE_EXTRAPG
rslt |= (0,1)[keep_open] << vrlg.MCONTR_LINTILE_KEEP_OPEN
rslt |= (0,1)[byte32] << vrlg.MCONTR_LINTILE_BYTE32
rslt |= (0,1)[reset_frame] << vrlg.MCONTR_LINTILE_RST_FRAME
rslt |= (1,0)[chn_reset] << vrlg.MCONTR_LINTILE_EN # inverted
rslt |= (0,1)[enable] << vrlg.MCONTR_LINTILE_NRESET
rslt |= (0,1)[write_mem] << vrlg.MCONTR_LINTILE_WRITE
rslt |= (extra_pages & ((1 << vrlg.MCONTR_LINTILE_EXTRAPG_BITS) - 1)) << vrlg.MCONTR_LINTILE_EXTRAPG
rslt |= (0,1)[keep_open] << vrlg.MCONTR_LINTILE_KEEP_OPEN
rslt |= (0,1)[byte32] << vrlg.MCONTR_LINTILE_BYTE32
rslt |= (0,1)[reset_frame] << vrlg.MCONTR_LINTILE_RST_FRAME
rslt |= (0,1)[single] << vrlg.MCONTR_LINTILE_SINGLE
rslt |= (0,1)[repetitive] << vrlg.MCONTR_LINTILE_REPEAT
rslt |= (0,1)[disable_need] << vrlg.MCONTR_LINTILE_DIS_NEED
rslt |= (0,1)[single] << vrlg.MCONTR_LINTILE_SINGLE
rslt |= (0,1)[repetitive] << vrlg.MCONTR_LINTILE_REPEAT
rslt |= (0,1)[disable_need] << vrlg.MCONTR_LINTILE_DIS_NEED
rslt |= (0,1)[skip_too_late] << vrlg.MCONTR_LINTILE_SKIP_LATE
return rslt
'''
......
py393/x393_mcntrl_membridge.py
View file @ 944ff196
......@@ -308,6 +308,7 @@ class X393McntrlMembridge(object):
0) # chn_reset
'''
mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = False,
disable_need = False,
repetitive= True,
single = False,
......
py393/x393_mcntrl_tests.py
View file @ 944ff196
......@@ -290,6 +290,7 @@ class X393McntrlTests(object):
0) # chn_reset
'''
mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = False,
disable_need = False,
repetitive= True,
single = False,
......@@ -442,6 +443,7 @@ class X393McntrlTests(object):
0) # chn_reset
'''
mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = False,
disable_need = False,
repetitive= True,
single = False,
......@@ -556,6 +558,7 @@ class X393McntrlTests(object):
0) # chn_reset
'''
mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = False,
disable_need = False,
repetitive= True,
single = False,
......@@ -698,6 +701,7 @@ class X393McntrlTests(object):
0) # chn_reset
'''
mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = False,
disable_need = False,
repetitive= True,
single = False,
......
py393/x393_mcntrl_timing.py
View file @ 944ff196
......@@ -64,7 +64,8 @@ class X393McntrlTiming(object):
fSDCLK=fVCO/CLKOUT1_DIVIDE
tSDCLK=1000.0/fSDCLK # in ns
phaseStep=1000.0/(fVCO*56.0) # 1 unit of phase shift (now 112 for the full period
fREF=fCLK_IN*vrlg.CLKFBOUT_MULT_REF/vrlg.CLKFBOUT_DIV_REF
# fREF=fCLK_IN*vrlg.CLKFBOUT_MULT_REF/vrlg.CLKFBOUT_DIV_REF
fREF=fCLK_IN*vrlg.MULTICLK_MULT/vrlg.MULTICLK_DIV_DLYREF/vrlg.MULTICLK_DIVCLK
dlyStep=1000.0/fREF/32/2 # Approximate, depending on calibration
dlyFStep=0.01 # fine step
return{"SDCLK_PERIOD":tSDCLK,
......
py393/x393_sens_cmprs.py
View file @ 944ff196
......@@ -68,6 +68,16 @@ GLBL_MEMBRIDGE_END = None
GLBL_BUFFER_END = None
GLBL_WINDOW = None
#SENSOR_INTERFACE_PARALLEL = "PAR12"
#SENSOR_INTERFACE_HISPI = "HISPI"
# for now - single sensor type per interface
SENSOR_INTERFACES={x393_sensor.SENSOR_INTERFACE_PARALLEL: {"mv":2800, "freq":24.0, "iface":"2V5_LVDS"},
x393_sensor.SENSOR_INTERFACE_HISPI: {"mv":1820, "freq":24.444, "iface":"1V8_LVDS"}}
SENSOR_DEFAULTS= {x393_sensor.SENSOR_INTERFACE_PARALLEL: {"width":2592, "height":1944, "top":0, "left":0, "slave":0x48, "i2c_delay":100, "bayer":3},
# SENSOR_INTERFACE_HISPI: {"width":4608, "height":3288, "top":0, "left":0, "slave":0x10, "i2c_delay":100}}
x393_sensor.SENSOR_INTERFACE_HISPI: {"width":4384, "height":3288, "top":0, "left":0, "slave":0x10, "i2c_delay":100, "bayer":2}}
class X393SensCmprs(object):
DRY_MODE = True # True
DEBUG_MODE = 1
......@@ -132,33 +142,102 @@ class X393SensCmprs(object):
global BUFFER_ADDRESS, BUFFER_LEN
return BUFFER_ADDRESS + BUFFER_LEN
def setSensorClock(self, freq_MHz = 24.0):
def setSensorClock(self, freq_MHz = 24.0, iface = "2V5_LVDS", quiet = 0):
"""
Set up external clock for sensor-synchronous circuitry (and sensor(s) themselves.
Currently required clock frequency is 1/4 of the sensor clock, so it is 24MHz for 96MHz sensor
@param freq_MHz - input clock frequency (MHz). Currently for 96MHZ sensor clock it should be 24.0
@param freq_MHz - input clock frequency (MHz). Currently for 96MHZ sensor clock it should be 24.0
@param iface - one of the supported interfaces
(see ls /sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070/output_drivers)
@param quiet - reduce output
"""
with open ( SI5338_PATH + "/output_drivers/2V5_LVDS", "w") as f:
if self.DRY_MODE:
print ("Not defined for simulation mode")
return
with open ( SI5338_PATH + "/output_drivers/" + iface, "w") as f:
print("2", file = f)
with open ( SI5338_PATH + "/output_clocks/out2_freq_fract","w") as f:
print("%d"%(round(1000000*freq_MHz)), file = f )
def setSensorPower(self, sub_pair=0, power_on=0):
if quiet == 0:
print ("Set sensor clock to %f MHz, driver type \"%s\""%(freq_MHz,iface))
def setSensorPower(self, sub_pair=0, power_on=0, quiet=0):
"""
@param sub_pair - pair of the sensors: 0 - sensors 1 and 2, 1 - sensors 3 and 4
@param power_on - 1 - power on, 0 - power off (both sensor power and interface/FPGA bank voltage)
@param quiet - reduce output
"""
if quiet == 0:
print (("vcc_sens01 vp33sens01", "vcc_sens23 vp33sens23")[sub_pair]+" -> "+POWER393_PATH + "/channels_"+ ("dis","en")[power_on])
with open (POWER393_PATH + "/channels_"+ ("dis","en")[power_on],"w") as f:
print(("vcc_sens01 vp33sens01", "vcc_sens23 vp33sens23")[sub_pair], file = f)
def setSensorIfaceVoltage(self, sub_pair, voltage_mv, quiet = 0):
"""
Set interface voltage (should be done before power is on)
@param sub_pair - pair of the sensors: 0 - sensors 1 and 2, 1 - sensors 3 and 4
@param voltage_mv - desired interface voltage (1800..2800 mv)
@param quiet - reduce output
"""
with open (POWER393_PATH + "/voltages_mv/"+ ("vcc_sens01", "vcc_sens23")[sub_pair],"w") as f:
print(voltage_mv, file = f)
if quiet == 0:
print ("Set sensors %s interface voltage to %d mV"%(("0, 1","2, 3")[sub_pair],voltage_mv))
# time.sleep(0.1)
def setSensorIfaceVoltagePower(self, sub_pair, voltage_mv, quiet=0):
"""
Set interface voltage and turn on power for interface and the sensors
@param sub_pair - pair of the sensors: 0 - sensors 1 and 2, 1 - sensors 3 and 4
@param voltage_mv - desired interface voltage (1800..2800 mv)
@param quiet - reduce output
"""
self.setSensorPower(sub_pair = sub_pair, power_on = 0)
time.sleep(0.2)
self.setSensorIfaceVoltage(sub_pair=sub_pair, voltage_mv = voltage_mv)
time.sleep(0.2)
if self.DRY_MODE:
print ("Not defined for simulation mode")
return
with open (POWER393_PATH + "/channels_en","w") as f:
print(("vcc_sens01", "vcc_sens23")[sub_pair], file = f)
if quiet == 0:
print ("Turned on interface power %f V for sensors %s"%(voltage_mv*0.001,("0, 1","2, 3")[sub_pair]))
# time.sleep(0.1)
with open (POWER393_PATH + "/channels_en","w") as f:
print(("vp33sens01", "vp33sens23")[sub_pair], file = f)
if quiet == 0:
print ("Turned on +3.3V power for sensors %s"%(("0, 1","2, 3")[sub_pair]))
# time.sleep(0.1)
# def getSensorInterfaceType(self):
# """
# Get sensor interface type by reading status register 0xfe that is set to 0 for parallel and 1 for HiSPi
# @return "PAR12" or "HISPI"
# """
# return (SENSOR_INTERFACE_PARALLEL, SENSOR_INTERFACE_HISPI)[self.x393_axi_tasks.read_status(address=0xfe)] # "PAR12" , "HISPI"
def setupSensorsPowerClock(self,quiet=0):
"""
Set interface voltage for all sensors, clock for frequency and sensor power
for the interface matching bitstream file
"""
ifaceType = self.x393Sensor.getSensorInterfaceType();
if quiet == 0:
print ("Configuring sensor ports for interface type: \"%s\""%(ifaceType))
for sub_pair in (0,1):
self.setSensorIfaceVoltagePower(sub_pair, SENSOR_INTERFACES[ifaceType]["mv"])
self.setSensorClock(freq_MHz = SENSOR_INTERFACES[ifaceType]["freq"], iface = SENSOR_INTERFACES[ifaceType]["iface"])
# def setSensorClock(self, freq_MHz = 24.0, iface = "2V5_LVDS"):
def setup_sensor_channel (self,
exit_step = None,
num_sensor = 0,
# histogram_start_phys_page, # Calculate from?
# frame_full_width, # 13-bit Padded line length (8-row increment), in 8-bursts (16 bytes)
window_width = 2592, # 2592
window_height = 1944, # 1944
window_left = 0, # 0
window_top = 0, # 0? 1?
window_width = None, # 2592, # 2592
window_height = None, # 1944, # 1944
window_left = None, # 0, # 0
window_top = None, # 0, # 0? 1?
# compressor_left_margin = 0, #0?`1?
# frame_start_address, # calculate through num_sensor, num frames, frame size and start addr?
# frame_start_address_inc,
......@@ -166,10 +245,10 @@ class X393SensCmprs(object):
colorsat_blue = 0x180, # 0x90 fo 1x
colorsat_red = 0x16c, # 0xb6 for x1
clk_sel = 1, # 1
histogram_left = 0,
histogram_top = 0,
histogram_width_m1 = 2559, #0,
histogram_height_m1 = 1935, #0,
histogram_left = None, # 0,
histogram_top = None, # 0,
histogram_width_m1 = None, # 2559, #0,
histogram_height_m1 = None, # 1935, #0,
verbose = 1):
"""
Setup one sensor+compressor channel (for one sub-channel only)
......@@ -203,6 +282,42 @@ class X393SensCmprs(object):
@return True if all done, False if exited prematurely through exit_step
"""
# @param compressor_left_margin - 0..31 - left margin for compressor (to the nearest 32-byte column)
sensorType = self.x393Sensor.getSensorInterfaceType()
if verbose > 0 :
print ("Sensor port %d interface type: %s"%(num_sensor, sensorType))
window = self.specify_window (window_width = window_width,
window_height = window_height,
window_left = window_left,
window_top = window_top,
cmode = None, # will use 0
verbose = 0)
window_width = window["width"]
window_height = window["height"]
window_left = window["left"]
window_top = window["top"]
"""
cmode = window["cmode"]
if window_width is None:
window_width = SENSOR_DEFAULTS[sensorType]["width"]
if window_height is None:
window_height = SENSOR_DEFAULTS[sensorType]["height"]
if window_left is None:
window_left = SENSOR_DEFAULTS[sensorType]["left"]
if window_top is None:
window_top = SENSOR_DEFAULTS[sensorType]["top"]
"""
#setting up histogram window, same for parallel, similar for serial
if histogram_left is None:
histogram_left = 0
if histogram_top is None:
histogram_top = 0
if histogram_width_m1 is None:
histogram_width_m1 = window_width - 33
if histogram_height_m1 is None:
histogram_height_m1 = window_height - 9
align_to_bursts = 64 # align full width to multiple of align_to_bursts. 64 is the size of memory access
width_in_bursts = window_width >> 4
......@@ -290,7 +405,7 @@ class X393SensCmprs(object):
run_mode = 0) # reset compressor
#TODO: Calculate from the image size?
self.x393Cmprs.setup_compressor_channel (
num_sensor = num_sensor,
chn = num_sensor,
qbank = 0,
dc_sub = True,
cmode = vrlg.CMPRS_CBIT_CMODE_JPEG18,
......@@ -321,10 +436,12 @@ class X393SensCmprs(object):
print ("frame_full_width = 0x%x"%(frame_full_width))
print ("window_width = 0x%x"%(width32 * 2 )) # window_width >> 4)) # width in 16 - bursts, made evem
print ("window_height = 0x%x"%(window_height & 0xfffffff0))
print ("window_left = 0x%x"%(left_tiles32 * 2)) # window_left >> 4)) # lext in 16-byte bursts, made even
print ("window_left = 0x%x"%(left_tiles32 * 2)) # window_left >> 4)) # left in 16-byte bursts, made even
print ("window_top = 0x%x"%(window_top))
print ("byte32 = 1")
print ("tile_width = 2")
print ("tile_vstep = 16")
print ("tile_height = 18")
print ("extra_pages = 1")
print ("disable_need = 1")
......@@ -340,6 +457,8 @@ class X393SensCmprs(object):
window_top = window_top, # input [31:0] window_top;
byte32 = 1,
tile_width = 2,
tile_vstep = 16,
tile_height = 18,
extra_pages = 1,
disable_need = 1)
......@@ -478,17 +597,125 @@ class X393SensCmprs(object):
repet_mode = True, # Normal mode, single trigger - just for debugging TODO: re-assign?
trig = False)
return True
def specify_window (self,
window_width = 2592, # 2592
window_height = 1944, # 1944
window_left = 0, # 0
window_top = 0, # 0? 1?
window_width = None, # 2592
window_height = None, # 1944
window_left = None, # 0
window_top = None, # 0? 1?
cmode = None,
bayer = None,
y_quality = None,
c_quality = None, # use "same" to save None
portrait = None,
gamma = None,
black = None, # 0.04
colorsat_blue = None, # colorsat_blue, #0x180 # 0x90 for 1x
colorsat_red = None, # colorsat_red, #0x16c, # 0xb6 for x1
verbose = 1
):
global GLBL_WINDOW
GLBL_WINDOW = {"width": window_width,
"height": window_height,
"left": window_left,
"top": window_top}
if GLBL_WINDOW is None:
GLBL_WINDOW = {}
sensorType = self.x393Sensor.getSensorInterfaceType()
if verbose > 0 :
print ("Sensor interface type: %s"%(sensorType))
if window_width is None:
try:
window_width = GLBL_WINDOW["width"]
except:
window_width = SENSOR_DEFAULTS[sensorType]["width"]
if window_height is None:
try:
window_height = GLBL_WINDOW["height"]
except:
window_height = SENSOR_DEFAULTS[sensorType]["height"]
if window_left is None:
try:
window_left = GLBL_WINDOW["left"]
except:
window_left = SENSOR_DEFAULTS[sensorType]["left"]
if window_top is None:
try:
window_top = GLBL_WINDOW["top"]
except:
window_top = SENSOR_DEFAULTS[sensorType]["top"]
if cmode is None:
try:
cmode = GLBL_WINDOW["cmode"]
except:
cmode = 0
if bayer is None:
try:
bayer = GLBL_WINDOW["bayer"]
except:
bayer = SENSOR_DEFAULTS[sensorType]["bayer"]
if y_quality is None:
try:
y_quality = GLBL_WINDOW["y_quality"]
except:
y_quality = 100
if c_quality is None:
try:
c_quality = GLBL_WINDOW["c_quality"]
except:
c_quality = "same"
if c_quality == "same": # to save as None, not to not save
c_quality = None
if portrait is None:
try:
portrait = GLBL_WINDOW["portrait"]
except:
portrait = False
if gamma is None:
try:
gamma = GLBL_WINDOW["gamma"]
except:
gamma = 0.57
if black is None:
try:
black = GLBL_WINDOW["black"]
except:
black = 0.04
if colorsat_blue is None:
try:
colorsat_blue = GLBL_WINDOW["colorsat_blue"]
except:
colorsat_blue = 2.0 # *0x90
if colorsat_red is None:
try:
colorsat_red = GLBL_WINDOW["colorsat_red"]
except:
colorsat_red = 2.0 # *0xb6
GLBL_WINDOW = {"width": window_width,
"height": window_height,
"left": window_left,
"top": window_top,
"cmode": cmode,
"bayer": bayer,
"y_quality": y_quality,
"c_quality": c_quality,
"portrait": portrait,
"gamma": gamma,
"black": black,
"colorsat_blue": colorsat_blue,
"colorsat_red": colorsat_red,
}
if verbose > 1:
print("GLBL_WINDOW:")
for k in GLBL_WINDOW.keys():
print ("%15s:%s"%(k,str(GLBL_WINDOW[k])))
return GLBL_WINDOW
def specify_phys_memory(self,
......@@ -519,30 +746,276 @@ class X393SensCmprs(object):
print ("membridge end = 0x%x"%(GLBL_MEMBRIDGE_END))
print ("membridge size = %d bytes"%(GLBL_MEMBRIDGE_END - GLBL_MEMBRIDGE_START))
print ("memory buffer end = 0x%x"%(GLBL_BUFFER_END))
def setup_cmdmux (self):
#Will report frame number for each channel
"""
Configure status report for command sequencer to report 4 LSB of each channel frame number
with get_frame_numbers()
"""
self.x393_axi_tasks.program_status( # also takes snapshot
base_addr = vrlg.CMDSEQMUX_ADDR,
reg_addr = 0,
mode = 3, # input [1:0] mode;
seq_number = 0) #input [5:0] seq_num;
def get_frame_numbers(self):
"""
@return list of 4-bit frame numbers, per channel
"""
status = self.x393_axi_tasks.read_status(address = vrlg.CMDSEQMUX_STATUS)
frames = []
for i in range(4):
frames.append (int((status >> (4*i)) & 0xf))
return frames
def get_frame_number_i2c(self,
channel=0):
"""
@return frame number of the i2c sequencer for the specified channel
"""
try:
if (channel == all) or (channel[0].upper() == "A"): #all is a built-in function
frames=[]
for channel in range(4):
frames.append(self.get_frame_number_i2c(channel = channel))
return frames
except:
pass
status = self.x393_axi_tasks.read_status(
address = vrlg.SENSI2C_STATUS_REG_BASE + channel * vrlg.SENSI2C_STATUS_REG_INC + vrlg.SENSI2C_STATUS_REG_REL)
return int((status >> 12) & 0xf)
def skip_frame(self,
channel_mask,
loop_delay = 0.01,
timeout = 2.0):
old_frames = self.get_frame_numbers()
timeout_time = time.time() + timeout
frameno = -1
while time.time() < timeout_time :
new_frames = self.get_frame_numbers()
all_new=True
for chn in range(4):
if ((channel_mask >> chn) & 1):
if (old_frames[chn] == new_frames[chn]):
all_new = False
break
else:
frameno = new_frames[chn]
if all_new:
break;
return frameno # Frame number of the last new frame checked
def skip_frame_i2c(self,
channel_mask,
loop_delay = 0.01,
timeout = 2.0):
old_frames = self.get_frame_number_i2c("all")
timeout_time = time.time() + timeout
frameno = -1
while time.time() < timeout_time :
new_frames = self.get_frame_number_i2c("all")
all_new=True
for chn in range(4):
if ((channel_mask >> chn) & 1):
if (old_frames[chn] == new_frames[chn]):
all_new = False
break
else:
frameno = new_frames[chn]
if all_new:
break;
return frameno # Frame number of the last new frame checked
def setup_compressor(self,
chn,
cmode = vrlg.CMPRS_CBIT_CMODE_JPEG18,
bayer = 0,
qbank = 0,
dc_sub = 1,
multi_frame = 1,
focus_mode = 0,
coring = 0,
window_width = None, # 2592, # 2592
window_height = None, # 1944, # 1944
window_left = None, # 0, # 0
window_top = None, # 0, # 0? 1?
last_buf_frame = 1, # - just 2-frame buffer
colorsat_blue = 0x180, # 0x90 for 1x
colorsat_red = 0x16c, # 0xb6 for x1
verbose = 1):
"""
@param chn - compressor channel (0..3)
@param cmode - color mode:
CMPRS_CBIT_CMODE_JPEG18 = 0 - color 4:2:0
CMPRS_CBIT_CMODE_MONO6 = 1 - mono 4:2:0 (6 blocks)
CMPRS_CBIT_CMODE_JP46 = 2 - jp4, 6 blocks, original
CMPRS_CBIT_CMODE_JP46DC = 3 - jp4, 6 blocks, dc -improved
CMPRS_CBIT_CMODE_JPEG20 = 4 - mono, 4 blocks (but still not actual monochrome JPEG as the blocks are scanned in 2x2 macroblocks)
CMPRS_CBIT_CMODE_JP4 = 5 - jp4, 4 blocks, dc-improved
CMPRS_CBIT_CMODE_JP4DC = 6 - jp4, 4 blocks, dc-improved
CMPRS_CBIT_CMODE_JP4DIFF = 7 - jp4, 4 blocks, differential
CMPRS_CBIT_CMODE_JP4DIFFHDR = 8 - jp4, 4 blocks, differential, hdr
CMPRS_CBIT_CMODE_JP4DIFFDIV2 = 9 - jp4, 4 blocks, differential, divide by 2
CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = 10 - jp4, 4 blocks, differential, hdr,divide by 2
CMPRS_CBIT_CMODE_MONO1 = 11 - mono JPEG (not yet implemented)
CMPRS_CBIT_CMODE_MONO4 = 14 - mono 4 blocks
@param qbank - quantization table page (0..15)
@param dc_sub - True - subtract DC before running DCT, False - no subtraction, convert as is,
@param multi_frame - False - single-frame buffer, True - multi-frame video memory buffer,
@param bayer - Bayer shift (0..3)
@param focus_mode - focus mode - how to combine image with "focus quality" in the result image
@param coring - coring value
@param window_width - (here - in pixels)
@param window_height - 16-bit window height in scan lines
@param window_left - left margin of the window (here - in pixels)
@param window_top - top margin of the window (16 bit)
@param last_buf_frame) - 16-bit number of the last frame in a buffer
@param colorsat_blue - color saturation for blue (10 bits), 0x90 for 100%
@param colorsat_red - color saturation for red (10 bits), 0xb6 for 100%
@param verbose - verbose level
"""
try:
if (chn == all) or (chn[0].upper() == "A"): #all is a built-in function
for chn in range(4):
self. setup_compressor(self,
chn = chn,
cmode = cmode,
qbank = qbank,
dc_sub = dc_sub,
multi_frame = multi_frame,
bayer = bayer,
focus_mode = focus_mode,
coring = coring,
window_width = None, # 2592, # 2592
window_height = None, # 1944, # 1944
window_left = None, # 0, # 0
window_top = None, # 0, # 0? 1?
last_buf_frame = last_buf_frame, # - just 2-frame buffer
colorsat_blue = colorsat_blue, #0x180 # 0x90 for 1x
colorsat_red = colorsat_red, #0x16c, # 0xb6 for x1
verbose = verbose)
return
except:
pass
window = self.specify_window (window_width = window_width,
window_height = window_height,
window_left = window_left,
window_top = window_top,
cmode = cmode, # will use 0
verbose = 0)
window_width = window["width"]
window_height = window["height"]
window_left = window["left"]
window_top = window["top"]
cmode = window["cmode"]
num_sensor = chn # 1:1 sensor - compressor
align_to_bursts = 64 # align full width to multiple of align_to_bursts. 64 is the size of memory access
width_in_bursts = window_width >> 4
if (window_width & 0xf):
width_in_bursts += 1
compressor_left_margin = window_left % 32
num_burst_in_line = (window_left >> 4) + width_in_bursts
num_pages_in_line = num_burst_in_line // align_to_bursts;
if num_burst_in_line % align_to_bursts:
num_pages_in_line += 1
frame_full_width = num_pages_in_line * align_to_bursts
num8rows= (window_top + window_height) // 8
if (window_top + window_height) % 8:
num8rows += 1
frame_start_address_inc = num8rows * frame_full_width
num_macro_cols_m1 = (window_width >> 4) - 1
num_macro_rows_m1 = (window_height >> 4) - 1
frame_start_address = (last_buf_frame + 1) * frame_start_address_inc * num_sensor
self.x393Cmprs.setup_compressor_channel (
chn = chn,
qbank = qbank,
dc_sub = dc_sub,
cmode = cmode, # vrlg.CMPRS_CBIT_CMODE_JPEG18,
multi_frame = True,
bayer = bayer,
focus_mode = focus_mode,
num_macro_cols_m1 = num_macro_cols_m1,
num_macro_rows_m1 = num_macro_rows_m1,
left_margin = compressor_left_margin,
colorsat_blue = colorsat_blue,
colorsat_red = colorsat_red,
coring = 0,
verbose = verbose)
# TODO: calculate widths correctly!
if cmode == vrlg.CMPRS_CBIT_CMODE_JPEG18:
tile_margin = 2 # 18x18 instead of 16x16
tile_width = 2
extra_pages = 1
else: # actually other modes should be parsed here, now considering just JP4 flavors
tile_margin = 0 # 18x18 instead of 16x16
tile_width = 4
# extra_pages = (0,1)[(compressor_left_margin % 16) != 0] # memory access block border does not cut macroblocks
extra_pages = 1 # just testing
tile_vstep = 16
tile_height = tile_vstep + tile_margin
left_tiles32 = window_left // 32
last_tile32 = (window_left + ((num_macro_cols_m1 + 1) * 16) + tile_margin - 1) // 32
width32 = last_tile32 - left_tiles32 + 1 # number of 32-wide tiles needed in each row
if (verbose > 0) :
print ("setup_compressor_memory:")
print ("num_sensor = ", num_sensor)
print ("frame_sa = 0x%x"%(frame_start_address))
print ("frame_sa_inc = 0x%x"%(frame_start_address_inc))
print ("last_frame_num = 0x%x"%(last_buf_frame))
print ("frame_full_width = 0x%x"%(frame_full_width))
print ("window_width = 0x%x"%(width32 * 2 )) # window_width >> 4)) # width in 16 - bursts, made evem
print ("window_height = 0x%x"%(window_height & 0xfffffff0))
print ("window_left = 0x%x"%(left_tiles32 * 2)) # window_left >> 4)) # left in 16-byte bursts, made even
print ("window_top = 0x%x"%(window_top))
print ("byte32 = 1")
print ("tile_width = 0x%x"%(tile_width))
print ("tile_vstep = 0x%x"%(tile_vstep))
print ("tile_height = 0x%x"%(tile_height))
print ("extra_pages = 0x%x"%(extra_pages))
print ("disable_need = 1")
self.x393Cmprs.setup_compressor_memory (
num_sensor = num_sensor,
frame_sa = frame_start_address, # input [31:0] frame_sa; # 22-bit frame start address ((3 CA LSBs==0. BA==0)
frame_sa_inc = frame_start_address_inc, # input [31:0] frame_sa_inc; # 22-bit frame start address increment ((3 CA LSBs==0. BA==0)
last_frame_num = last_buf_frame, # input [31:0] last_frame_num; # 16-bit number of the last frame in a buffer
frame_full_width = frame_full_width, # input [31:0] frame_full_width; # 13-bit Padded line length (8-row increment), in 8-bursts (16 bytes)
window_width = (width32 * 2 ), # input [31:0] window_width; # 13 bit - in 8*16=128 bit bursts
window_height = window_height & 0xfffffff0, # input [31:0] window_height; # 16 bit
window_left = left_tiles32 * 2, # input [31:0] window_left;
window_top = window_top, # input [31:0] window_top;
byte32 = 1,
tile_width = tile_width,
tile_vstep = tile_vstep,
tile_height = tile_height,
extra_pages = extra_pages,
disable_need = 1)
def setup_all_sensors (self,
setup_membridge = False,
exit_step = None,
sensor_mask = 0x1, # channel 0 only
gamma_load = False,
# histogram_start_phys_page, # Calculate from?
# frame_full_width, # 13-bit Padded line length (8-row increment), in 8-bursts (16 bytes)
window_width = 2592, # 2592
window_height = 1944, # 1944
window_left = 0, # 0
window_top = 0, # 0? 1?
window_width = None, # 2592, # 2592
window_height = None, # 1944, # 1944
window_left = None, # 0, # 0
window_top = None, # 0, # 0? 1?
compressor_left_margin = 0, #0?`1?
# frame_start_address, # calculate through num_sensor, num frames, frame size and start addr?
# frame_start_address_inc,
last_buf_frame = 1, # - just 2-frame buffer
colorsat_blue = 0x180, # 0x90 fo 1x
colorsat_red = 0x16c, # 0xb6 for x1
clk_sel = 1, # 1
histogram_left = 0,
histogram_top = 0,
histogram_width_m1 = 2559, #0,
histogram_height_m1 = 799, #0,
histogram_left = None,
histogram_top = None,
histogram_width_m1 = None, # 2559, #0,
histogram_height_m1 = None, # 799, #0,
circbuf_chn_size= 0x1000000, #16777216
verbose = 1):
"""
......@@ -574,26 +1047,60 @@ class X393SensCmprs(object):
@param last_buf_frame) - 16-bit number of the last frame in a buffer
@param colorsat_blue - color saturation for blue (10 bits), 0x90 for 100%
@param colorsat_red - color saturation for red (10 bits), 0xb6 for 100%
@param clk_sel - True - use pixel clock from the sensor, False - use internal clock (provided to the sensor), None - no chnage
@param clk_sel - True - use pixel clock from the sensor, False - use internal clock (provided to the sensor), None - no change
@param histogram_left - histogram window left margin
@param histogram_top - histogram window top margin
@param histogram_width_m1 - one less than window width. If 0 - use frame right margin (end of HACT)
@param histogram_height_m1 - one less than window height. If 0 - use frame bottom margin (end of VACT)
@param circbuf_chn_size - circular buffer size for each channel, in bytes
@parame verbose - verbose level
@param verbose - verbose level
@return True if all done, False if exited prematurely by exit_step
"""
global GLBL_CIRCBUF_CHN_SIZE, GLBL_CIRCBUF_STARTS, GLBL_CIRCBUF_END, GLBL_MEMBRIDGE_START, GLBL_MEMBRIDGE_END, GLBL_BUFFER_END, GLBL_WINDOW
# camsync_setup (
# 4'hf ); # sensor_mask); #
sensorType = self.x393Sensor.getSensorInterfaceType()
if verbose > 0 :
print ("Sensor interface type: %s"%(sensorType))
window = self.specify_window (window_width = window_width,
window_height = window_height,
window_left = window_left,
window_top = window_top,
cmode = None, # will use 0
verbose = 0)
window_width = window["width"]
window_height = window["height"]
window_left = window["left"]
window_top = window["top"]
"""
if window_width is None:
window_width = SENSOR_DEFAULTS[sensorType]["width"]
if window_height is None:
window_height = SENSOR_DEFAULTS[sensorType]["height"]
if window_left is None:
window_left = SENSOR_DEFAULTS[sensorType]["left"]
if window_top is None:
window_top = SENSOR_DEFAULTS[sensorType]["top"]
"""
#setting up histogram window, same for parallel, similar for serial
if histogram_left is None:
histogram_left = 0
if histogram_top is None:
histogram_top = 0
if histogram_width_m1 is None:
histogram_width_m1 = window_width - 33
if histogram_height_m1 is None:
histogram_height_m1 = window_height - 1145
self.specify_phys_memory(circbuf_chn_size = circbuf_chn_size)
"""
self.specify_window (window_width = window_width,
window_height = window_height,
window_left = window_left,
window_top = window_top)
window_top = window_top,
cmode = None, # will use 0
verbose = 0)
"""
#TODO: calculate addresses/lengths
"""
AFI mux is programmed in 32-byte chunks
......@@ -628,7 +1135,11 @@ class X393SensCmprs(object):
membridge_start = GLBL_MEMBRIDGE_START,
membridge_end = GLBL_MEMBRIDGE_END,
verbose = verbose)
# if verbose >0 :
# print ("===================== Sensor power setup: sensor ports 0 and 1 =========================")
# self.setSensorPower(sub_pair=0, power_on=0)
"""
if sensor_mask & 3: # Need power for sens1 and sens 2
if verbose >0 :
print ("===================== Sensor power setup: sensor ports 0 and 1 =========================")
......@@ -640,6 +1151,10 @@ class X393SensCmprs(object):
if verbose >0 :
print ("===================== Sensor clock setup 24MHz (will output 96MHz) =========================")
self.setSensorClock(freq_MHz = 24.0)
"""
if verbose >0 :
print ("===================== Set up sensor and interface power, clock generator =========================")
self.setupSensorsPowerClock(quiet = (verbose >0))
if exit_step == 1: return False
if verbose >0 :
print ("===================== GPIO_SETUP =========================")
......@@ -648,6 +1163,11 @@ class X393SensCmprs(object):
mode = 3, # input [1:0] mode;
seq_num = 0) # input [5:0] seq_num;
if verbose >0 :
print ("===================== CMDSEQMUX_SETUP =========================")
#Will report frame number for each channel
self.setup_cmdmux()
if exit_step == 2: return False
if verbose >0 :
print ("===================== RTC_SETUP =========================")
......@@ -735,6 +1255,9 @@ class X393SensCmprs(object):
if verbose >0 :
print ("===================== I2C_SETUP =========================")
slave_addr = SENSOR_DEFAULTS[sensorType]["slave"]
i2c_delay= SENSOR_DEFAULTS[sensorType]["i2c_delay"]
self.x393Sensor.set_sensor_i2c_command (
num_sensor = num_sensor,
rst_cmd = True,
......@@ -745,40 +1268,75 @@ class X393SensCmprs(object):
active_sda = True,
early_release_0 = True,
verbose = verbose)
if sensorType == x393_sensor.SENSOR_INTERFACE_PARALLEL:
self.x393Sensor.set_sensor_i2c_table_reg_wr (
num_sensor = num_sensor,
page = 0,
slave_addr = slave_addr,
rah = 0,
num_bytes = 3,
bit_delay = i2c_delay,
verbose = verbose)
self.x393Sensor.set_sensor_i2c_table_reg_rd (
num_sensor = num_sensor,
page = 1,
two_byte_addr = 0,
num_bytes_rd = 2,
bit_delay = i2c_delay,
verbose = verbose)
# aliases for indices 0x90 and 0x91
self.x393Sensor.set_sensor_i2c_table_reg_wr (
num_sensor = num_sensor,
page = 0x90,
slave_addr = slave_addr,
rah = 0,
num_bytes = 3,
bit_delay = i2c_delay,
verbose = verbose)
self.x393Sensor.set_sensor_i2c_table_reg_rd (
num_sensor = num_sensor,
page = 0x91,
two_byte_addr = 0,
num_bytes_rd = 2,
bit_delay = 100,
verbose = verbose)
self.x393Sensor.set_sensor_i2c_table_reg_rd ( #for compatibility with HiSPi mode, last page for read
num_sensor = num_sensor,
page = 0xff,
two_byte_addr = 0,
num_bytes_rd = 2,
bit_delay = i2c_delay,
verbose = verbose)
self.x393Sensor.set_sensor_i2c_table_reg_wr (
num_sensor = num_sensor,
page = 0,
slave_addr = 0x48,
rah = 0,
num_bytes = 3,
bit_delay = 100,
verbose = verbose)
self.x393Sensor.set_sensor_i2c_table_reg_rd (
num_sensor = num_sensor,
page = 1,
two_byte_addr = 0,
num_bytes_rd = 2,
bit_delay = 100,
verbose = verbose)
# aliases for indices 0x90 and 0x91
self.x393Sensor.set_sensor_i2c_table_reg_wr (
num_sensor = num_sensor,
page = 0x90,
slave_addr = 0x48,
rah = 0,
num_bytes = 3,
bit_delay = 100,
verbose = verbose)
self.x393Sensor.set_sensor_i2c_table_reg_rd (
num_sensor = num_sensor,
page = 0x91,
two_byte_addr = 0,
num_bytes_rd = 2,
bit_delay = 100,
verbose = verbose)
elif sensorType == x393_sensor.SENSOR_INTERFACE_HISPI:
for page in (0,1,2,3,4,5,6, # SMIA configuration registers
0x10,0x11,0x12,0x13,0x14, # SMIA limit registers
0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37, # Manufacturer registers
0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e):
self.x393Sensor.set_sensor_i2c_table_reg_wr (
num_sensor = num_sensor,
page = page,
slave_addr = slave_addr,
rah = page,
num_bytes = 4,
bit_delay = i2c_delay,
verbose = verbose)
self.x393Sensor.set_sensor_i2c_table_reg_rd ( # last page used for read
num_sensor = num_sensor,
page = 0xff,
two_byte_addr = 1,
num_bytes_rd = 2,
bit_delay = i2c_delay,
verbose = verbose)
else:
raise ("Unknown sensor type: %s"%(sensorType))
# Turn off reset (is it needed?)
self.x393Sensor.set_sensor_i2c_command (
num_sensor = num_sensor,
......@@ -953,6 +1511,7 @@ class X393SensCmprs(object):
Setup video memory
"""
mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = False,
disable_need = False,
repetitive= True,
single = False,
......@@ -1023,9 +1582,9 @@ class X393SensCmprs(object):
("sensor_channel3_i", "sensor_channel"),
("histogram_saxi_i", "histogram_saxi")),
"sensor_channel":(("sens_histogram0_i", "sens_histogram"),
("sens_histogram1_i", "sens_histogram"),
("sens_histogram2_i", "sens_histogram"),
("sens_histogram3_i", "sens_histogram"),
# ("sens_histogram1_i", "sens_histogram"),
# ("sens_histogram2_i", "sens_histogram"),
# ("sens_histogram3_i", "sens_histogram"),
("debug_line_cntr", 16),
("debug_lines", 16),
......
py393/x393_sensor.py
View file @ 944ff196
......@@ -40,6 +40,9 @@ import x393_utils
import time
import vrlg
import x393_mcntrl
#import x393_sens_cmprs
SENSOR_INTERFACE_PARALLEL = "PAR12"
SENSOR_INTERFACE_HISPI = "HISPI"
class X393Sensor(object):
DRY_MODE= True # True
......@@ -47,6 +50,7 @@ class X393Sensor(object):
x393_mem=None
x393_axi_tasks=None #x393X393AxiControlStatus
x393_utils=None
verbose=1
def __init__(self, debug_mode=1,dry_mode=True, saveFileName=None):
self.DEBUG_MODE= debug_mode
......@@ -54,10 +58,18 @@ class X393Sensor(object):
self.x393_mem= X393Mem(debug_mode,dry_mode)
self.x393_axi_tasks= x393_axi_control_status.X393AxiControlStatus(debug_mode,dry_mode)
self.x393_utils= x393_utils.X393Utils(debug_mode,dry_mode, saveFileName) # should not overwrite save file path
try:
self.verbose=vrlg.VERBOSE
except:
pass
def getSensorInterfaceType(self):
"""
Get sensor interface type by reading status register 0xfe that is set to 0 for parallel and 1 for HiSPi
@return "PAR12" or "HISPI"
"""
return (SENSOR_INTERFACE_PARALLEL, SENSOR_INTERFACE_HISPI)[self.x393_axi_tasks.read_status(address=0xfe)] # "PAR12" , "HISPI"
def program_status_sensor_i2c( self,
num_sensor,
mode, # input [1:0] mode;
......@@ -262,7 +274,7 @@ class X393Sensor(object):
rslt |= 1 << vrlg.SENSI2C_TBL_RNWREG # this is read register command (0 - write register)
if two_byte_addr > 1:
two_byte_addr = 1
rslt |= (0,1)[two_byte_addr] << vrlg.SENSI2C_TBL_SA
rslt |= (0,1)[two_byte_addr] << vrlg.SENSI2C_TBL_NABRD
rslt |= (num_bytes_rd & ((1 << vrlg.SENSI2C_TBL_NBRD_BITS) - 1)) << vrlg.SENSI2C_TBL_NBRD
rslt |= (bit_delay & ((1 << vrlg.SENSI2C_TBL_DLY_BITS) - 1)) << vrlg.SENSI2C_TBL_DLY
return rslt
......@@ -474,6 +486,23 @@ class X393Sensor(object):
verbose = verbose)
self.x393_axi_tasks.write_control_register(vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC + vrlg.SENSI2C_CTRL_RADDR, ta)
self.x393_axi_tasks.write_control_register(vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC + vrlg.SENSI2C_CTRL_RADDR, td)
if verbose > 1:
print ("ta= 0x%x, td = 0x%x"%(ta,td))
def write_sensor_reg16(self,
num_sensor,
reg_addr16,
reg_data16):
"""
Write i2c register in immediate mode
@param num_sensor - sensor port number (0..3), or "all" - same to all sensors
@param reg_addr16 - 16-bit register address (page+low byte, for MT9F006 high byte is an 8-bit slave address = 0x90)
@param reg_data16 - 16-bit data to write to sesnor register
"""
self.write_sensor_i2c (num_sensor = num_sensor,
rel_addr = True,
addr = 0,
data = ((reg_addr16 & 0xffff) << 16) | (reg_data16 & 0xffff) )
def write_sensor_i2c (self,
num_sensor,
......@@ -495,7 +524,7 @@ class X393Sensor(object):
sent for such extra word, only the lower bytes are sent.
2 - register read: index page, slave address (8-bit, with lower bit 0) and one or 2 address bytes (as programmed
in the table. Slave address is always in byte 2 (bits 23:16), byte1 (high register address) is skipped if
read address in teh table is programmed to be a single-byte one
read address in the table is programmed to be a single-byte one
"""
try:
if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
......@@ -562,7 +591,7 @@ class X393Sensor(object):
reg_addr,
indx = 1,
sa7 = 0x48,
verbose = 0):
verbose = 1):
"""
Read sequence of bytes available and print the result as a single hex number
@param num_sensor - sensor port number (0..3), or "all" - same to all sensors
......@@ -599,10 +628,107 @@ class X393Sensor(object):
d = 0
for b in dl:
d = (d << 8) | (b & 0xff)
fmt="i2c data[0x%02x:0x%x] = 0x%%0%dx"%(sa7,reg_addr,len(dl)*2)
print (fmt%(d))
if verbose > 0:
fmt="i2c data[0x%02x:0x%x] = 0x%%0%dx"%(sa7,reg_addr,len(dl)*2)
print (fmt%(d))
return d
def set_sensor_flipXY(self,
num_sensor,
flip_x = False,
flip_y = False,
verbose = 1):
"""
Set sensor horizontal and vertical mirror (flip)
@param num_sensor - sensor number or "all"
@param flip_x - mirror image around vertical axis
@param flip_y - mirror image around horizontal axis
@param verbose - verbose level
"""
sensorType = self.getSensorInterfaceType()
if flip_x is None:
flip_x = False
if flip_y is None:
flip_y = False
if sensorType == "PAR12":
data = (0,0x8000)[flip_y] | (0,0x4000)[flip_x]
self.write_sensor_reg16 (num_sensor = num_sensor,
reg_addr16 = 0x9020,
reg_data16 = data)
elif sensorType == "HISPI":
data = (0,0x8000)[flip_y] | (0,0x4000)[flip_x] | 0x41
self.write_sensor_reg16 (num_sensor = num_sensor,
reg_addr16 = 0x3040,
reg_data16 = data)
else:
raise ("Unknown sensor type: %s"%(sensorType))
def set_sensor_gains_exposure(self,
num_sensor,
gain_r = None,
gain_gr = None,
gain_gb = None,
gain_b = None,
exposure = None,
verbose = 1):
"""
Set sensor analog gains (raw register values) and
exposure (in scan lines)
@param num_sensor - sensor number or "all"
@param gain_r - RED gain
@param gain_gr - GREEN in red row gain
@param gain_gb - GREEN in blue row gain
@param gain_b - BLUE gain
@param exposure - exposure time in scan lines
@param verbose - verbose level
"""
sensorType = self.getSensorInterfaceType()
if sensorType == "PAR12":
if not gain_r is None:
self.write_sensor_reg16 (num_sensor = num_sensor,
reg_addr16 = 0x902c,
reg_data16 = gain_r)
if not gain_gr is None:
self.write_sensor_reg16 (num_sensor = num_sensor,
reg_addr16 = 0x902b,
reg_data16 = gain_gr)
if not gain_gb is None:
self.write_sensor_reg16 (num_sensor = num_sensor,
reg_addr16 = 0x902e,
reg_data16 = gain_gb)
if not gain_b is None:
self.write_sensor_reg16 (num_sensor = num_sensor,
reg_addr16 = 0x902d,
reg_data16 = gain_b)
if not exposure is None:
self.write_sensor_reg16 (num_sensor = num_sensor,
reg_addr16 = 0x9009,
reg_data16 = exposure)
elif sensorType == "HISPI":
if not gain_r is None:
self.write_sensor_reg16 (num_sensor = num_sensor,
reg_addr16 = 0x208,
reg_data16 = gain_r)
if not gain_gr is None:
self.write_sensor_reg16 (num_sensor = num_sensor,
reg_addr16 = 0x206, # SMIA register
reg_data16 = gain_gr)
if not gain_gb is None:
self.write_sensor_reg16 (num_sensor = num_sensor,
reg_addr16 = 0x20c, # SMIA register
reg_data16 = gain_gb)
if not gain_b is None:
self.write_sensor_reg16 (num_sensor = num_sensor,
reg_addr16 = 0x20a, # SMIA register
reg_data16 = gain_b)
if not exposure is None:
self.write_sensor_reg16 (num_sensor = num_sensor,
reg_addr16 = 0x202, # SMIA register
reg_data16 = exposure)
else:
raise ("Unknown sensor type: %s"%(sensorType))
def set_sensor_io_ctl (self,
num_sensor,
mrst = None,
......@@ -633,14 +759,14 @@ class X393Sensor(object):
quadrants = quadrants)
reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + vrlg.SENSIO_RADDR + vrlg.SENSIO_CTRL;
self.x393_axi_tasks.write_control_register(reg_addr, data)
def set_sensor_io_dly (self,
num_sensor,
mmcm_phase,
iclk_dly,
vact_dly,
hact_dly,
pxd_dly):
# TODO: Make one for HiSPi (it is different)
def set_sensor_io_dly_parallel (self,
num_sensor,
mmcm_phase,
iclk_dly,
vact_dly,
hact_dly,
pxd_dly):
"""
Set sensor port input delays and mmcm phase
@param num_sensor - sensor port number (0..3)
......@@ -661,6 +787,35 @@ class X393Sensor(object):
self.x393_axi_tasks.write_control_register(reg_addr + 3, dlys[3]) # {mmcm_phase, bpf, vact, hact}
self.set_sensor_io_ctl (num_sensor = num_sensor,
set_delays = True)
def set_sensor_hispi_lanes(self,
num_sensor,
lane0 = 0,
lane1 = 1,
lane2 = 2,
lane3 = 3):
"""
Set HiSPi sensor lane map (physical lane for each logical lane)
@param num_sensor - sensor port number (0..3)
@param lane0 - physical (input) lane number for logical (internal) lane 0
@param lane1 - physical (input) lane number for logical (internal) lane 1
@param lane2 - physical (input) lane number for logical (internal) lane 2
@param lane3 - physical (input) lane number for logical (internal) lane 3
"""
data = ((lane0 & 3) << 0 ) | ((lane1 & 3) << 2 ) | ((lane2 & 3) << 4 ) | ((lane3 & 3) << 6 )
reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + vrlg.SENSIO_RADDR + vrlg.SENSIO_DELAYS;
self.x393_axi_tasks.write_control_register(reg_addr + 1, data)
def set_sensor_fifo_lag(self,
num_sensor,
fifo_lag = 7):
"""
Set HiSPi sensor FIFO lag (when to start line output, ~= 1/2 FIFO size)
@param num_sensor - sensor port number (0..3)
@param fifo_lag - number of pixels to write to FIFO before starting output
"""
reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + vrlg.SENSIO_RADDR + vrlg.SENSIO_DELAYS;
self.x393_axi_tasks.write_control_register(reg_addr + 0, fifo_lag)
def set_sensor_io_jtag (self,
num_sensor,
......@@ -1057,6 +1212,7 @@ class X393Sensor(object):
"""
base_addr = vrlg.MCONTR_SENS_BASE + vrlg.MCONTR_SENS_INC * num_sensor;
mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = True,
disable_need = False,
repetitive= True,
single = False,
......
py393/x393_utils.py
View file @ 944ff196
......@@ -38,7 +38,7 @@ from x393_mem import X393Mem
from time import sleep
import vrlg # global parameters
import x393_axi_control_status
import shutil
DEFAULT_BITFILE="/usr/local/verilog/x393.bit"
FPGA_RST_CTRL= 0xf8000240
FPGA0_THR_CTRL=0xf8000178
......@@ -96,6 +96,10 @@ class X393Utils(object):
"""
if bitfile is None:
bitfile=DEFAULT_BITFILE
print ("Sensor ports power off")
POWER393_PATH = '/sys/devices/elphel393-pwr.1'
with open (POWER393_PATH + "/channels_dis","w") as f:
print("vcc_sens01 vp33sens01 vcc_sens23 vp33sens23", file = f)
print ("FPGA clock OFF")
self.x393_mem.write_mem(FPGA0_THR_CTRL,1)
print ("Reset ON")
......@@ -286,4 +290,13 @@ class X393Utils(object):
print ("Failed to write to %s"%(os.path.abspath(fileName)))
else:
print(txt)
def copy (self,
src,
dst):
"""
Copy files in the file system
@param src - source path
@param dst - destination path/directory
"""
shutil.copy2(src, dst)
sensor/sens_10398.v
View file @ 944ff196
......@@ -41,7 +41,7 @@ module sens_10398 #(
parameter SENSIO_JTAG = 'h2,
// parameter SENSIO_WIDTH = 'h3, // set line width (1.. 2^16) if 0 - use HACT
parameter SENSIO_DELAYS = 'h4, // 'h4..'h7 - each address sets 4 delays through 4 bytes of 32-bit data
// 6 - delays, 7 - phase
// 5, swap lanes 6 - delays, 7 - phase
parameter SENSIO_STATUS_REG = 'h21,
parameter SENS_JTAG_PGMEN = 8,
......@@ -91,6 +91,10 @@ module sens_10398 #(
parameter HISPI_NUMLANES = 4,
parameter HISPI_DELAY_CLK = "FALSE",
parameter HISPI_MMCM = "TRUE",
parameter HISPI_KEEP_IRST = 5, // number of cycles to keep irst on after release of prst (small number - use 1 hot)
parameter HISPI_WAIT_ALL_LANES = 4'h8, // number of output pixel cycles to wait after the earliest lane
parameter HISPI_FIFO_DEPTH = 4,
parameter HISPI_FIFO_START = 7,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
......@@ -157,7 +161,8 @@ module sens_10398 #(
reg [31:0] data_r;
// reg [3:0] set_idelay;
reg set_lanes_map; // set sequence of lanes im the composite pixel line
reg set_fifo_dly; // set how long to wait after strating to fill FIFOs (in items) ~= 1/2 2^FIFO_DEPTH
reg set_idelays;
reg set_iclk_phase;
reg set_ctrl_r;
......@@ -213,6 +218,12 @@ module sens_10398 #(
if (mrst) data_r <= 0;
else if (cmd_we) data_r <= cmd_data;
if (mrst) set_fifo_dly <= 0;
else set_fifo_dly <= cmd_we & (cmd_a==(SENSIO_DELAYS+0)); // TODO - add Symbolic names
if (mrst) set_lanes_map <= 0;
else set_lanes_map <= cmd_we & (cmd_a==(SENSIO_DELAYS+1));
if (mrst) set_idelays <= 0;
else set_idelays <= cmd_we & (cmd_a==(SENSIO_DELAYS+2));
......@@ -271,7 +282,7 @@ module sens_10398 #(
// generate (slow) clock for the sensor - it will be multiplied by the sensor VCO
always @(posedge pclk) begin
if (prst || (pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] == 0)) pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] <= (PXD_CLK_DIV / 2);
if (prst || (pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] == 0)) pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] <= (PXD_CLK_DIV / 2) -1;
else pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] <= pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] - 1;
// treat MSB separately to make 50% duty cycle
if (prst) pxd_clk_cntr[PXD_CLK_DIV_BITS-1] <= 0;
......@@ -342,6 +353,10 @@ module sens_10398 #(
.HISPI_NUMLANES (HISPI_NUMLANES),
.HISPI_DELAY_CLK (HISPI_DELAY_CLK),
.HISPI_MMCM (HISPI_MMCM),
.HISPI_KEEP_IRST (HISPI_KEEP_IRST),
.HISPI_WAIT_ALL_LANES (HISPI_WAIT_ALL_LANES),
.HISPI_FIFO_DEPTH (HISPI_FIFO_DEPTH),
.HISPI_FIFO_START (HISPI_FIFO_START),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
......@@ -349,6 +364,7 @@ module sens_10398 #(
.HISPI_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
.HISPI_IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.HISPI_IOSTANDARD (HISPI_IOSTANDARD)
) sens_hispi12l4_i (
.pclk (pclk), // input
.prst (prsts), //prst), // input
......@@ -362,7 +378,9 @@ module sens_10398 #(
.eof (eof), // output reg
.mclk (mclk), // input
.mrst (mrst), // input
.dly_data (data_r), // input[31:0]
.dly_data (data_r), // input[31:0]
.set_lanes_map (set_lanes_map), // input
.set_fifo_dly (set_fifo_dly), // input
.set_idelay ({4{set_idelays}}), // input[3:0]
.ld_idelay (ld_idelay), // input
.set_clk_phase (set_iclk_phase), // input
......
sensor/sens_hispi12l4.v
View file @ 944ff196
......@@ -57,18 +57,22 @@ module sens_hispi12l4#(
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
parameter DEFAULT_LANE_MAP = 8'b11100100, // one-to-one map (or make it 8'b00111001 ?)
parameter HISPI_MSB_FIRST = 0,
parameter HISPI_NUMLANES = 4,
parameter HISPI_DELAY_CLK = "FALSE",
parameter HISPI_MMCM = "TRUE",
parameter HISPI_KEEP_IRST = 5, // number of cycles to keep irst on after release of prst (small number - use 1 hot)
parameter HISPI_WAIT_ALL_LANES = 4'h8, // number of output pixel cycles to wait after the earliest lane
parameter HISPI_FIFO_DEPTH = 4,
parameter HISPI_FIFO_START = 7,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA),
parameter HISPI_KEEP_IRST = 5 // number of cycles to keep irst on after release of prst (small number - use 1 hot)
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I" //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA),
)(
input pclk, // global clock input, pixel rate (220MHz for MT9F002)
input prst, // reset @pclk (add sensor reset here)
......@@ -89,6 +93,8 @@ module sens_hispi12l4#(
input mclk,
input mrst,
input [HISPI_NUMLANES * 8-1:0] dly_data, // delay value (3 LSB - fine delay) - @posedge mclk
input set_lanes_map, // set number of physical lane for each logical one
input set_fifo_dly,
input [HISPI_NUMLANES-1:0] set_idelay, // mclk synchronous load idelay value
input ld_idelay, // mclk synchronous set idealy value
input set_clk_phase, // mclk synchronous set idealy value
......@@ -106,10 +112,33 @@ module sens_hispi12l4#(
wire ipclk; // re-generated half HiSPi clock (165 MHz)
wire ipclk2x;// re-generated HiSPi clock (330 MHz)
wire [HISPI_NUMLANES * 4-1:0] sns_d;
localparam WAIT_ALL_LANES = 4'h8; // number of output pixel cycles to wait after the earliest lane
localparam FIFO_DEPTH = 4;
// localparam WAIT_ALL_LANES = 4'h8; // number of output pixel cycles to wait after the earliest lane
// localparam FIFO_DEPTH = 4;
reg [HISPI_KEEP_IRST-1:0] irst_r;
wire irst = irst_r[0];
wire irst = irst_r[0];
reg [HISPI_NUMLANES * 2-1:0] lanes_map;
reg [HISPI_NUMLANES * 4-1:0] logical_lanes4;
reg [HISPI_FIFO_DEPTH-1:0] fifo_out_dly_mclk;
reg [HISPI_FIFO_DEPTH-1:0] fifo_out_dly;
always @ (posedge mclk) begin
if (mrst) lanes_map <= DEFAULT_LANE_MAP; //{2'h3,2'h2,2'h1,2'h0}; // 1-to-1 default map
else if (set_lanes_map) lanes_map <= dly_data[HISPI_NUMLANES * 2-1:0];
if (mrst) fifo_out_dly_mclk <= HISPI_FIFO_START;
else if (set_fifo_dly) fifo_out_dly_mclk <= dly_data[HISPI_FIFO_DEPTH-1:0];
end
//non-parametrized lane switch (4x4)
always @(posedge ipclk) begin
logical_lanes4[ 3: 0] <= sns_d[{lanes_map[1:0],2'b0} +:4];
logical_lanes4[ 7: 4] <= sns_d[{lanes_map[3:2],2'b0} +:4];
logical_lanes4[11: 8] <= sns_d[{lanes_map[5:4],2'b0} +:4];
logical_lanes4[15:12] <= sns_d[{lanes_map[7:6],2'b0} +:4];
end
always @(posedge ipclk) begin
fifo_out_dly <= fifo_out_dly_mclk;
end
sens_hispi_clock #(
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
......@@ -182,8 +211,13 @@ module sens_hispi12l4#(
.ipclk (ipclk), // input
.ipclk2x (ipclk2x), // input
.irst (irst), // input
//`ifdef REVERSE_LANES
// .din_p ({sns_dp[0],sns_dp[1],sns_dp[2],sns_dp[3]}), // input[3:0]
// .din_n ({sns_dn[0],sns_dn[1],sns_dn[2],sns_dn[3]}), // input[3:0]
//`else
.din_p (sns_dp), // input[3:0]
.din_n (sns_dn), // input[3:0]
//`endif
.dout (sns_d) // output[15:0]
);
......@@ -209,6 +243,7 @@ module sens_hispi12l4#(
reg sof_pclk;
// wire [HISPI_NUMLANES-1:0] sol_pclk = rd_run & ~rd_run_d;
wire sol_pclk = |(rd_run & ~rd_run_d); // possibly multi-cycle
reg start_fifo_re; // start reading FIFO - single-cycle
reg [HISPI_NUMLANES-1:0] good_lanes; // lanes that started active line OK
reg [HISPI_NUMLANES-1:0] fifo_re;
reg [HISPI_NUMLANES-1:0] fifo_re_r;
......@@ -222,6 +257,7 @@ module sens_hispi12l4#(
({12 {fifo_re_r[1] & rd_run[1]}} & fifo_out[1 * 12 +:12]) |
({12 {fifo_re_r[2] & rd_run[2]}} & fifo_out[2 * 12 +:12]) |
({12 {fifo_re_r[3] & rd_run[3]}} & fifo_out[3 * 12 +:12]);
......@@ -246,10 +282,12 @@ module sens_hispi12l4#(
end
always @(posedge pclk) begin
if (prst || !vact_ipclk) vact_pclk_strt <= 0;
else vact_pclk_strt <= {vact_pclk_strt[0], 1'b1};
if (prst || !vact_ipclk) vact_pclk_strt <= 0;
else vact_pclk_strt <= {vact_pclk_strt[0], 1'b1};
rd_run_d <= rd_run;
start_fifo_re <= sol_pclk && !rd_line; // sol_pclk may be multi-cycle
sof_pclk <= vact_pclk_strt[0] && ! vact_pclk_strt[1];
......@@ -270,9 +308,10 @@ module sens_hispi12l4#(
({12 {fifo_re_r[2] & rd_run[2]}} & fifo_out[2 * 12 +:12]) |
({12 {fifo_re_r[3] & rd_run[3]}} & fifo_out[3 * 12 +:12]); */
if (prst) fifo_re <= 0;
else if (sol_pclk || (rd_line && fifo_re[HISPI_NUMLANES - 1])) fifo_re <= 1;
else fifo_re <= fifo_re << 1;
if (prst) fifo_re <= 0;
// else if (sol_pclk || (rd_line && fifo_re[HISPI_NUMLANES - 1])) fifo_re <= 1;
else if (start_fifo_re || (rd_line && fifo_re[HISPI_NUMLANES - 1])) fifo_re <= 1;
else fifo_re <= fifo_re << 1;
// if (prst || (hact_off && (|(good_lanes & ~rd_run)))) hact_r <= 0;
if (prst || (hact_off && (!rd_line || (good_lanes[3] & ~rd_run[3])))) hact_r <= 0;
......@@ -288,7 +327,7 @@ module sens_hispi12l4#(
) dly_16_start_line_i (
.clk (pclk), // input
.rst (1'b0), // input
.dly (WAIT_ALL_LANES), // input[3:0]
.dly (HISPI_WAIT_ALL_LANES), // input[3:0]
.din (rd_line && !rd_line_r), // input[0:0]
.dout (sol_all_dly) // output[0:0]
);
......@@ -298,10 +337,10 @@ module sens_hispi12l4#(
) dly_16_hact_on_i (
.clk (pclk), // input
.rst (1'b0), // input
// .dly (4'h2), // input[3:0]
// .dly (4'h3), // input[3:0]
// .dly (4'h2), // input[3:0]
// .dly (4'h3), // input[3:0]
.dly (4'h1), // input[3:0]
// .dly (4'h2), // input[3:0]
// .dly (4'h2), // input[3:0]
.din (sol_pclk), // input[0:0]
.dout (hact_on) // output[0:0]
);
......@@ -339,7 +378,7 @@ module sens_hispi12l4#(
) sens_hispi_lane_i (
.ipclk (ipclk), // input
.irst (irst), // input
.din (sns_d[4*i +: 4]), // input[3:0]
.din (logical_lanes4[4*i +: 4]), // input[3:0]
.dout (hispi_aligned[12*i +: 12]), // output[3:0] reg
.dv (hispi_dv[i]), // output reg
.embed (hispi_embed[i]), // output reg
......@@ -349,16 +388,17 @@ module sens_hispi12l4#(
.eol (hispi_eol[i]) // output reg
);
sens_hispi_fifo #(
.COUNT_START (7),
// .COUNT_START (HISPI_FIFO_START),
.DATA_WIDTH (12),
.DATA_DEPTH (FIFO_DEPTH)
.DATA_DEPTH (HISPI_FIFO_DEPTH)
) sens_hispi_fifo_i (
.ipclk (ipclk), // input
.irst (irst), // input
.we (hispi_dv[i]), // input
.sol (hispi_sol[i] && !(hispi_embed[i] && ignore_embedded_ipclk)), // input
.eol (hispi_eol[i]), // input
.din (hispi_aligned[12*i +: 12]), // input[11:0]
.din (hispi_aligned[12*i +: 12]), // input[11:0]
.out_dly (fifo_out_dly), // input[3:0]
.pclk (pclk), // input
.prst (prst), // input
.re (fifo_re[i]), // input
......
sensor/sens_hispi_fifo.v
View file @ 944ff196
......@@ -34,7 +34,7 @@
`timescale 1ns/1ps
module sens_hispi_fifo#(
parameter COUNT_START = 7, // wait these many samples input before starting output
// parameter COUNT_START = 7, // wait these many samples input before starting output
parameter DATA_WIDTH = 12,
parameter DATA_DEPTH = 4 // >=3
) (
......@@ -44,6 +44,7 @@ module sens_hispi_fifo#(
input sol, // start of line - 1 cycle before dv
input eol, // end of line - last dv
input [DATA_WIDTH-1:0] din,
input [DATA_DEPTH-1:0] out_dly, // wait these many samples input before starting output
input pclk,
input prst,
input re,
......@@ -55,8 +56,11 @@ module sens_hispi_fifo#(
reg [DATA_DEPTH:0] ra;
wire line_start_pclk;
reg line_run_ipclk;
reg line_run_ipclk_d; // to generate start for very short lines (may just use small out_dly value)
reg line_run_pclk;
reg run_r;
reg start_sent;
reg start_out_ipclk;
assign run = run_r;
// TODO: generate early done by comparing ra with (wa-1) - separate counter
......@@ -69,6 +73,15 @@ module sens_hispi_fifo#(
if (irst || eol) line_run_ipclk <= 0;
else if (sol) line_run_ipclk <= 1;
if (!line_run_ipclk) start_sent <= 0;
else if (start_out_ipclk) start_sent <= 1;
line_run_ipclk_d <= line_run_ipclk;
if (irst) start_out_ipclk <= 0;
else start_out_ipclk <= line_run_ipclk? (!start_sent && we && (wa[DATA_DEPTH-1:0] == out_dly)) : (line_run_ipclk_d && !start_sent);
end
always @(posedge pclk) begin
......@@ -91,7 +104,8 @@ module sens_hispi_fifo#(
.rst (irst), // input
.src_clk (ipclk), // input
.dst_clk (pclk), // input
.in_pulse (we && (wa == COUNT_START)), // input
// .in_pulse (we && (wa == COUNT_START)), // input
.in_pulse (start_out_ipclk), // input
.out_pulse (line_start_pclk), // output
.busy() // output
);
......
sensor/sensor_channel.v
View file @ 944ff196
......@@ -257,6 +257,10 @@ module sensor_channel#(
parameter HISPI_NUMLANES = 4,
parameter HISPI_DELAY_CLK = "FALSE",
parameter HISPI_MMCM = "TRUE",
parameter HISPI_KEEP_IRST = 5, // number of cycles to keep irst on after release of prst (small number - use 1 hot)
parameter HISPI_WAIT_ALL_LANES = 4'h8, // number of output pixel cycles to wait after the earliest lane
parameter HISPI_FIFO_DEPTH = 4,
parameter HISPI_FIFO_START = 7,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_DQS_BIAS = "TRUE",
......@@ -462,13 +466,30 @@ module sensor_channel#(
`ifdef DEBUG_RING
reg vact_to_fifo_r;
// reg vact_to_fifo_r;
reg hact_to_fifo_r;
reg [15:0] debug_line_cntr;
reg [15:0] debug_lines;
reg [15:0] hact_cntr;
reg [15:0] vact_cntr;
`ifdef HISPI
always @(posedge pclk) begin
// vact_to_fifo_r <= vact_to_fifo;
hact_to_fifo_r <= hact;
if (sof) debug_line_cntr <= 0;
else if (hact && !hact_to_fifo_r) debug_line_cntr <= debug_line_cntr + 1;
if (sof) debug_lines <= debug_line_cntr;
if (prst) hact_cntr <= 0;
else if (hact && !hact_to_fifo_r) hact_cntr <= hact_cntr + 1;
if (prst) vact_cntr <= 0;
else if (sof) vact_cntr <= vact_cntr + 1;
end
`else
always @(posedge ipclk) begin
vact_to_fifo_r <= vact_to_fifo;
hact_to_fifo_r <= hact_to_fifo;
......@@ -485,6 +506,7 @@ module sensor_channel#(
else if (vact_to_fifo && !vact_to_fifo_r) vact_cntr <= vact_cntr + 1;
end
`endif
debug_slave #(
.SHIFT_WIDTH (128),
.READ_WIDTH (128),
......@@ -501,7 +523,12 @@ module sensor_channel#(
// .rd_data ({6'b0,hist_grant,hist_request, hist_gr[3:0], hist_rq[3:0], hact_cntr[15:0], debug_lines[15:0], debug_line_cntr[15:0]}), // input[31:0]
.rd_data ({
lens_pxd_in, gamma_pxd_in[15:0],
pxd_to_fifo[11:0],pxd[11:0],gamma_pxd_out[7:0],
`ifdef HISPI
12'b0,
`else
pxd_to_fifo[11:0],
`endif
pxd[11:0],gamma_pxd_out[7:0],
6'b0,hist_grant,hist_request, hist_gr[3:0], hist_rq[3:0], hact_cntr[15:0],
debug_lines[15:0], debug_line_cntr[15:0]}), // input[31:0]
......@@ -755,6 +782,10 @@ module sensor_channel#(
.HISPI_NUMLANES (HISPI_NUMLANES),
.HISPI_DELAY_CLK (HISPI_DELAY_CLK),
.HISPI_MMCM (HISPI_MMCM),
.HISPI_KEEP_IRST (HISPI_KEEP_IRST),
.HISPI_WAIT_ALL_LANES (HISPI_WAIT_ALL_LANES),
.HISPI_FIFO_DEPTH (HISPI_FIFO_DEPTH),
.HISPI_FIFO_START (HISPI_FIFO_START),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
......
sensor/sensors393.v
View file @ 944ff196
......@@ -289,6 +289,10 @@ module sensors393 #(
parameter HISPI_MMCM1 = "TRUE",
parameter HISPI_MMCM2 = "TRUE",
parameter HISPI_MMCM3 = "TRUE",
parameter HISPI_KEEP_IRST = 5, // number of cycles to keep irst on after release of prst (small number - use 1 hot)
parameter HISPI_WAIT_ALL_LANES = 4'h8, // number of output pixel cycles to wait after the earliest lane
parameter HISPI_FIFO_DEPTH = 4,
parameter HISPI_FIFO_START = 7,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_DQS_BIAS = "TRUE",
......@@ -610,7 +614,10 @@ module sensors393 #(
.HISPI_DELAY_CLK ((i & 2) ? ((i & 1) ? HISPI_DELAY_CLK3 : HISPI_DELAY_CLK2) : ((i & 1) ?HISPI_DELAY_CLK1 : HISPI_DELAY_CLK0 )),
.HISPI_MMCM ((i & 2) ? ((i & 1) ? HISPI_MMCM3 : HISPI_MMCM2) : ((i & 1) ?HISPI_MMCM1 : HISPI_MMCM0 )),
.HISPI_KEEP_IRST (HISPI_KEEP_IRST),
.HISPI_WAIT_ALL_LANES (HISPI_WAIT_ALL_LANES),
.HISPI_FIFO_DEPTH (HISPI_FIFO_DEPTH),
.HISPI_FIFO_START (HISPI_FIFO_START),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
......
status_read.v
View file @ 944ff196
......@@ -94,7 +94,10 @@ module status_read#(
assign axird_rdata=axi_status_rdata_r;
assign axird_selected = select_r;
initial begin
ram [DATA_2DEPTH] = FPGA_VERSION;
ram [DATA_2DEPTH] = FPGA_VERSION;
`ifdef HISPI
ram [DATA_2DEPTH-1] = 1; //0 - parallel sensor, 1 - HiSPi sensor
`endif
end
always @ (posedge axi_clk) begin
if (arst) select_r <= 0;
......
system_defines.vh
View file @ 944ff196
......@@ -41,7 +41,8 @@
// `define USE_OLD_XDCT393
// `define USE_PCLK2X
// `define USE_XCLK2X
// `define DEBUG_RING 1
`define REVERSE_LANES 1
`define DEBUG_RING 1
// `define MCLK_VCO_MULT 16
// DDR3 memory speed grade and density
`define sg25 1
......
util_modules/debug_master.v
View file @ 944ff196
......@@ -67,6 +67,7 @@ module debug_master #(
reg ld_r;
reg cmd; //command stae (0 - idle)
reg [DEBUG_CMD_LATENCY : 0] cmd_reg;
wire [3:0] debug_latency_plus1 = DEBUG_CMD_LATENCY+1;
wire set_status_w = cmd_we && (cmd_a == DEBUG_SET_STATUS);
wire shift32_w = cmd_we && (cmd_a == DEBUG_SHIFT_DATA);
......@@ -104,7 +105,7 @@ module debug_master #(
) dly_16_i (
.clk (mclk), // input
.rst (1'b0), // input
.dly (DEBUG_CMD_LATENCY+1), // input[3:0]
.dly (debug_latency_plus1), // DEBUG_CMD_LATENCY+1), // input[3:0]
.din (&cntr), // input[0:0]
.dout (shift_done) // output[0:0]
);
......
util_modules/resync_data.v 0 → 100644
View file @ 944ff196
/*******************************************************************************
* Module: resync_data
* Date:2015-12-22
* Author: Andrey Filippov
* Description: Resynchronize data between clock domains. No over/underruns
* are checker, start with half FIFO full. Async reset sets
* specifies output values regardless of the clocks
*
* Copyright (c) 2014 Elphel, Inc.
* resync_data.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* resync_data.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module resync_data
#(
parameter integer DATA_WIDTH=16,
parameter integer DATA_DEPTH=4, // >= 2
parameter INITIAL_VALUE = 0
) (
input arst, // async reset, active high (global)
input srst, // same as arst, but relies on the clocks
input wclk, // write clock - positive edge
input rclk, // read clock - positive edge
input we, // write enable
input re, // read enable
input [DATA_WIDTH-1:0] data_in, // input data
output reg [DATA_WIDTH-1:0] data_out, // output data
output reg valid // data valid @ rclk
);
localparam integer DATA_2DEPTH=(1<<DATA_DEPTH)-1;
reg [DATA_WIDTH-1:0] ram [0:DATA_2DEPTH];
reg [DATA_DEPTH-1:0] raddr;
reg [DATA_DEPTH-1:0] waddr;
reg [1:0] rrst = 3;
always @ (posedge rclk or posedge arst) begin
if (arst) valid <= 0;
else if (srst) valid <= 0;
else if (&waddr[DATA_DEPTH-2:0] && we) valid <= 1; // just once set and stays until reset
end
always @ (posedge wclk or posedge arst) begin
if (arst) waddr <= 0;
else if (srst) waddr <= 0;
else if (we) waddr <= waddr + 1;
end
always @ (posedge rclk or posedge arst) begin
if (arst) rrst <= 3;
else if (srst) rrst <= 3; // resync to rclk
else rrst <= rrst << 1;
if (arst) raddr <= 0;
else if (rrst[0]) raddr <= 0;
else if (re || rrst[1]) raddr <= raddr + 1;
if (arst) data_out <= INITIAL_VALUE;
else if (rrst[0]) data_out <= INITIAL_VALUE;
else if (re || rrst[1]) data_out <= ram[raddr];
end
always @ (posedge wclk) begin
if (we) ram[waddr] <= data_in;
end
endmodule
x393.v
View file @ 944ff196
......@@ -1647,7 +1647,10 @@ assign axi_grst = axi_rst_pre;
.HISPI_MMCM1 (HISPI_MMCM1),
.HISPI_MMCM2 (HISPI_MMCM2),
.HISPI_MMCM3 (HISPI_MMCM3),
.HISPI_KEEP_IRST (HISPI_KEEP_IRST),
.HISPI_WAIT_ALL_LANES (HISPI_WAIT_ALL_LANES),
.HISPI_FIFO_DEPTH (HISPI_FIFO_DEPTH),
.HISPI_FIFO_START (HISPI_FIFO_START),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
......
x393_testbench03.sav
View file @ 944ff196
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Sun Nov 8 07:30:39 2015
[*] Wed Nov 18 00:58:20 2015
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20151107210810890.fst"
[dumpfile_mtime] "Sun Nov 8 04:40:36 2015"
[dumpfile_size] 202201184
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20151115142219571.fst"
[dumpfile_mtime] "Sun Nov 15 22:02:48 2015"
[dumpfile_size] 287600988
[savefile] "/home/andrey/git/x393/x393_testbench03.sav"
[timestart] 0
[size] 1823 1180
[pos] 1920 0
*-25.279701 81782497 108390000 148070000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[pos] 0 0
*-25.097748 69667459 107947388 109212388 108561548 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench03.
[treeopen] x393_testbench03.par12_hispi_psp4l0_i.
[treeopen] x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[0].
......@@ -20,27 +20,39 @@
[treeopen] x393_testbench03.simul_sensor12bits_2_i.
[treeopen] x393_testbench03.x393_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.huffman_merge_code_literal_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_macroblock_buf_iface_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.csconvert_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.csconvert_i.i_csconvert_jp4.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.genblk3.
[treeopen] x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].
[treeopen] x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[2].
[treeopen] x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.
......@@ -63,8 +75,8 @@
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.
[sst_width] 445
[signals_width] 348
[sst_width] 340
[signals_width] 321
[sst_expanded] 1
[sst_vpaned_height] 514
@820
......@@ -78,7 +90,7 @@ x393_testbench03.x393_i.pclk
-
@1000200
-x393_top
@800200
@c00200
-sens_10398
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.pclk
......@@ -86,7 +98,18 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.ipclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sns_mrst
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.rst_mmcm
@c00200
@800022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.pxd_clk_cntr[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.pxd_clk_cntr[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.pxd_clk_cntr[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.pxd_clk_cntr[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.pxd_clk_cntr[3:0]
@1001200
-group_end
@200
-
@800200
-sens_hispi12l4
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sns_mrst
......@@ -635,13 +658,14 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.zero_after_ones_w
@1000200
-sens_hispi_lane0
@1401200
-sens_hispi12l4
@28
x393_testbench03.ffclk0p
@200
-
@1000200
@1401200
-sens_10398
@800200
@c00200
-sensor_channel_0
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.mclk
......@@ -905,9 +929,8 @@ x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i
-
@1401200
-mcntr_linear_rw_sensor0
@1000200
-sensor_channel_0
@800200
@c00200
-DDR3
@28
x393_testbench03.ddr3_i.SDCLK
......@@ -916,13 +939,11 @@ x393_testbench03.ddr3_i.SDCAS
x393_testbench03.ddr3_i.SDWE
@22
x393_testbench03.ddr3_i.SDA[14:0]
@28
x393_testbench03.ddr3_i.SDBA[2:0]
@22
x393_testbench03.ddr3_i.SDD_D[15:0]
@200
-
@1000200
@1401200
-DDR3
@c00200
-simul_sensor_0
......@@ -974,7 +995,7 @@ x393_testbench03.simul_sensor12bits_2_i.stopped
x393_testbench03.simul_sensor12bits_2_i.stoppedd
@1401200
-simul_sensor_0
@800200
@c00200
-PX1
@28
x393_testbench03.PX1_MCLK_PRE
......@@ -1008,9 +1029,9 @@ x393_testbench03.PX1_MRST
x393_testbench03.PX1_OFST
x393_testbench03.PX1_SHUTTER
x393_testbench03.PX1_VACT
@1000200
@1401200
-PX1
@800200
@c00200
-SENSOR0
@28
x393_testbench03.simul_sensor12bits_i.MCLK
......@@ -1026,13 +1047,13 @@ x393_testbench03.simul_sensor12bits_i.c
x393_testbench03.simul_sensor12bits_i.state[3:0]
@28
x393_testbench03.simul_sensor12bits_i.stoppedd
@23
@22
x393_testbench03.simul_sensor12bits_i.cntrd[15:0]
@200
-
@1000200
@1401200
-SENSOR0
@800200
@c00200
-par_hispi_sel
@28
x393_testbench03.par12_hispi_psp4l0_i.pclk
......@@ -1092,9 +1113,152 @@ x393_testbench03.par12_hispi_psp4l0_i.simul_clk_div_mult_i.clk_out
x393_testbench03.par12_hispi_psp4l0_i.simul_clk_div_mult_i.en
@1401200
-clk_mult_div
@1000200
-par_hispi_sel
@c00200
-sens_hispi_12l4
-lane0
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.ipclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.ipclk2x
@800022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_dp[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_dp[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_dp[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_dp[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_dp[3:0]
@1001200
-group_end
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_clkp
@c00022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(4)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(5)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(6)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(7)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(8)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(9)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(10)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(11)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(12)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(13)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(14)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(15)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
@1401200
-group_end
@800022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din[3:0]
@1001200
-group_end
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.dout[11:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.dv
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sof
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.eof
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sol
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.eol
@800022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sync_decode[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sync_decode[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sync_decode[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sync_decode[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sync_decode[3:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.got_sync
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.barrel[3:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.shift_val[1:0]
@1001200
-group_end
@1401200
-lane0
@800200
-fifo0
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.out_dly[3:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.ipclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.we
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.wa[4:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.din[11:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.start_out_ipclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.start_sent
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.line_run_ipclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.line_run_ipclk_d
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.pclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.re
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.run
@200
-
@1000200
-fifo0
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.set_lanes_map
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.set_fifo_dly
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.lanes_map[7:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_out_dly_mclk[3:0]
@200
-other
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.pclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_line
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_line_r
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sol_all_dly
@800022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_run[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_run[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_run[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_run[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_run[3:0]
@1001200
-group_end
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.good_lanes[3:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sol_pclk
@800022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re[3:0]
@800022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re_r[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re_r[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re_r[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re_r[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re_r[3:0]
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.pxd_out_pre[11:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.pxd_out[11:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hact_out
@1001200
-group_end
-group_end
@200
-
@1401200
-sens_hispi_12l4
@c00200
-par_hspi_0
@28
x393_testbench03.par12_hispi_psp4l0_i.clk_n
......@@ -1202,9 +1366,9 @@ x393_testbench03.par12_hispi_psp4l0_i.sdata_dly[3:0]
x393_testbench03.par12_hispi_psp4l0_i.sof_sol_sent
x393_testbench03.par12_hispi_psp4l0_i.vact
x393_testbench03.par12_hispi_psp4l0_i.vact_d
@1000200
@1401200
-par_hspi_0
@800200
@c00200
-scheduler16
@22
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.pri_reg[255:0]
......@@ -1567,9 +1731,9 @@ x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.seq_set
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.seq_wr
@200
-
@1000200
@1401200
-scheduler16
@800200
@c00200
-mcntr_linear_rw_chn1
@28
x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_start
......@@ -1601,6 +1765,7 @@ x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_done
x393_testbench03.x393_i.membridge_i.start_mclk
@1000200
-membridge
@1401200
-mcntr_linear_rw_chn1
@c00200
-hisogram_channel00
......@@ -2090,8 +2255,108 @@ x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huff
-
@1401200
-stuffer_metadata
@800200
@c00200
-new_compressor
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.frame_start_dst
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.frame_done_dst
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.reading_frame
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.line_unfinished_dst[15:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.macroblock_x[6:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.first_mb
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.last_mb
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.component_num[2:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.component_first
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.component_color
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dbg_last_DCAC
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.flush_hclk
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_flush
@c00022
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_out[15:0]
@28
(0)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_out[15:0]
(1)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_out[15:0]
(2)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_out[15:0]
(3)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_out[15:0]
(4)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_out[15:0]
(5)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_out[15:0]
(6)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_out[15:0]
(7)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_out[15:0]
(8)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_out[15:0]
(9)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_out[15:0]
(10)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_out[15:0]
(11)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_out[15:0]
(12)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_out[15:0]
(13)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_out[15:0]
(14)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_out[15:0]
(15)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_out[15:0]
@1401200
-group_end
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.gotLastBlock
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_re
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.mb_pre_first_out
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.mb_data_out[7:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.signed_y[8:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.ywe
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.yc_pre_first_out
@800200
-cmprs_pix_buf_iface
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.xclk
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.mb_pre_end
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.buf_ra[11:0]
@800022
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.buf_re[3:0]
@28
(0)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.buf_re[3:0]
(1)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.buf_re[3:0]
(2)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.buf_re[3:0]
(3)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.buf_re[3:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.pre2_first_out
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.pre_first_out
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.data_valid
@1001200
-group_end
@800200
-memory
-compressor
@22
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.window_width[13:0]
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.window_height[16:0]
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.window_x0[12:0]
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.window_y0[15:0]
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer_start32_rd
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer_bank[2:0]
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer_row[14:0]
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer_col[6:0]
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.rowcol_inc[13:0]
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.num_rows_m1[5:0]
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.num_cols_m1[5:0]
@200
-
@28
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer_partial
@1000200
-compressor
-memory
-cmprs_pix_buf_iface
@800200
-cs_convert18
@200
-
@1000200
-cs_convert18
@800200
-comressor
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.di[15:0]
@28
......@@ -2105,15 +2370,15 @@ x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huff
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_last_block
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.stuffer_do32[31:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.stuffer_bytes[1:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.stuffer_dv
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.stuffer_flush_out
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_escape_i.num_zeros_w[1:0]
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.escape_do32[31:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.escape_bytes[1:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.escape_dv
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.escape_flush_out
@22
......@@ -2127,7 +2392,251 @@ x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huff
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.imgsz4[21:0]
@1000200
-comressor
@1401200
-new_compressor
@c00200
- new_compressor_chn2
-tile_rd_chn2
@200
-
@1401200
-tile_rd_chn2
@c00200
-mem_buf_cmprs2
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.chn_rd_buf_i.wclk
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.chn_rd_buf_i.data_in[63:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.chn_rd_buf_i.we
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.chn_rd_buf_i.page[1:0]
@c00022
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.chn_rd_buf_i.waddr[6:0]
@28
(0)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.chn_rd_buf_i.waddr[6:0]
(1)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.chn_rd_buf_i.waddr[6:0]
(2)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.chn_rd_buf_i.waddr[6:0]
(3)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.chn_rd_buf_i.waddr[6:0]
(4)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.chn_rd_buf_i.waddr[6:0]
(5)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.chn_rd_buf_i.waddr[6:0]
(6)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.chn_rd_buf_i.waddr[6:0]
@1401200
-group_end
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.chn_rd_buf_i.ext_clk
@800022
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.chn_rd_buf_i.ext_raddr[11:0]
@28
(0)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.chn_rd_buf_i.ext_raddr[11:0]
(1)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.chn_rd_buf_i.ext_raddr[11:0]
(2)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.chn_rd_buf_i.ext_raddr[11:0]
(3)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.chn_rd_buf_i.ext_raddr[11:0]
(4)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.chn_rd_buf_i.ext_raddr[11:0]
(5)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.chn_rd_buf_i.ext_raddr[11:0]
(6)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.chn_rd_buf_i.ext_raddr[11:0]
(7)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.chn_rd_buf_i.ext_raddr[11:0]
(8)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.chn_rd_buf_i.ext_raddr[11:0]
(9)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.chn_rd_buf_i.ext_raddr[11:0]
(10)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.chn_rd_buf_i.ext_raddr[11:0]
(11)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.chn_rd_buf_i.ext_raddr[11:0]
@1001200
-group_end
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.chn_rd_buf_i.ext_rd
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.chn_rd_buf_i.ext_data_out[7:0]
@1401200
-mem_buf_cmprs2
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.di[15:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.ds
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.huffman_do27[26:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.huffman_dl[4:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.huffman_dv
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.huffman_flush
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.huffman_last_block
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.stuffer_do32[31:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.stuffer_bytes[1:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.stuffer_dv
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.stuffer_flush_out
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.escape_do32[31:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.escape_bytes[1:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.escape_dv
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.escape_flush_out
@22
[color] 3
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.data_out[31:0]
@28
[color] 3
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.data_out_valid
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.done
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.running
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.imgsz4[21:0]
@800200
-top_jp_channel2
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.frame_start_dst
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.frame_done_dst
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.reading_frame
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.line_unfinished_dst[15:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.component_first
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.converter_type[2:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct_start
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.mb_pre_first_out
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.mb_pre2_first_out
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.mb_data_out[7:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.signed_y[8:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.ywe
@1000200
-top_jp_channel2
@800200
-cmprs_macroblock_buf_iface
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_macroblock_buf_iface_i.left_marg[4:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_macroblock_buf_iface_i.n_blocks_in_row_m1[12:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_macroblock_buf_iface_i.n_block_rows_m1[12:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_w_m1[5:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_hper[4:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_macroblock_buf_iface_i.tile_width[1:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_macroblock_buf_iface_i.start_page[1:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_macroblock_buf_iface_i.first_mb
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_macroblock_buf_iface_i.last_mb
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_end_in
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_release_buf
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start_out
@800022
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start[8:0]
@28
(0)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start[8:0]
(1)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start[8:0]
(2)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start[8:0]
(3)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start[8:0]
(4)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start[8:0]
(5)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start[8:0]
(6)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start[8:0]
(7)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start[8:0]
(8)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start[8:0]
@1001200
-group_end
@1000200
-cmprs_macroblock_buf_iface
@800200
-cmprs_pix_buf_iface
@28
(7)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start[8:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.last_in_col
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.tile_col_width
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.col_inc[9:4]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.macroblock_x[6:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.extra_start_addr_w[9:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.extra_start_addr_r[5:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.mb_start_addr[9:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.mb_col_number[2:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.row_sa[11:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.mb_pre_start
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.last_col
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.last_in_tile
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.tile_sa[9:0]
@800022
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.buf_ra[11:0]
@28
(0)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.buf_ra[11:0]
(1)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.buf_ra[11:0]
(2)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.buf_ra[11:0]
(3)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.buf_ra[11:0]
(4)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.buf_ra[11:0]
(5)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.buf_ra[11:0]
(6)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.buf_ra[11:0]
(7)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.buf_ra[11:0]
(8)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.buf_ra[11:0]
(9)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.buf_ra[11:0]
(10)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.buf_ra[11:0]
(11)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.buf_ra[11:0]
@1001200
-group_end
@c00022
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.buf_re[3:0]
@28
(0)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.buf_re[3:0]
(1)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.buf_re[3:0]
(2)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.buf_re[3:0]
(3)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.buf_re[3:0]
@1401200
-group_end
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.mb_pre_end
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.pre2_first_out
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.pre_first_out
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.data_out[7:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.data_valid
@200
-
@1000200
-cmprs_pix_buf_iface
@c00200
-cs_convert_chn2
@800200
-cs_convert_jp4
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.csconvert_i.i_csconvert_jp4.en
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.csconvert_i.i_csconvert_jp4.pre_first_in
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.csconvert_i.i_csconvert_jp4.yaddr_cntr[7:0]
@200
-
@1000200
-cs_convert_jp4
@1401200
-cs_convert_chn2
@800200
-memory
-compressor
@22
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.window_width[13:0]
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.window_height[16:0]
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.window_x0[12:0]
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.window_y0[15:0]
@28
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.xfer_start32_rd
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.xfer_bank[2:0]
@22
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.xfer_row[14:0]
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.xfer_col[6:0]
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.rowcol_inc[13:0]
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.num_rows_m1[5:0]
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.num_cols_m1[5:0]
@28
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.xfer_partial
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.xfer_page_done
@1000200
-compressor
@200
-
@1000200
-memory
@1401200
- new_compressor_chn2
@22
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.fifo_rdata0[63:0]
@28
......@@ -2203,6 +2712,15 @@ x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.we
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.web[3:0]
@1401200
-memctrl_sequencer_cmd1buf
@28
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.mclk
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.hclk
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.fifo_rst0
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.fifo_ren0
@200
-
@29
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.eof_written0
@200
-
[pattern_trace] 1
......
x393_testbench03.tf
View file @ 944ff196
......@@ -114,7 +114,7 @@ parameter EXTERNAL_TIMESTAMP = 0; // 1 ; // embed local timestamp, 1 - emb
parameter TRIG_PERIOD = 6000 ;
`ifdef HISPI
parameter HBLANK= 52; // 90; // 12; /// 52; //*********************
parameter HBLANK= 92; // 72; // 62; // 52; // 90; // 12; /// 52; //*********************
parameter BLANK_ROWS_BEFORE= 3; // 9; // 3; //8; ///2+2 - a little faster than compressor
parameter BLANK_ROWS_AFTER= 1; //8;
......@@ -2136,7 +2136,7 @@ simul_axi_hp_wr #(
.FULL_HEIGHT (HISPI_FULL_HEIGHT),
.CLOCK_MPY (HISPI_CLK_MULT),
.CLOCK_DIV (HISPI_CLK_DIV),
.LANE0_DLY (1.3),
.LANE0_DLY (1.2), // 1.3), 1.3 not stable with default delays
.LANE1_DLY (2.7),
.LANE2_DLY (0.2),
.LANE3_DLY (1.8),
......@@ -2160,7 +2160,7 @@ simul_axi_hp_wr #(
.FULL_HEIGHT (HISPI_FULL_HEIGHT),
.CLOCK_MPY (HISPI_CLK_MULT),
.CLOCK_DIV (HISPI_CLK_DIV),
.LANE0_DLY (1.3),
.LANE0_DLY (1.2), // 1.3), 1.3 not stable with default delays
.LANE1_DLY (2.7),
.LANE2_DLY (0.2),
.LANE3_DLY (1.8),
......@@ -2184,7 +2184,7 @@ simul_axi_hp_wr #(
.FULL_HEIGHT (HISPI_FULL_HEIGHT),
.CLOCK_MPY (HISPI_CLK_MULT),
.CLOCK_DIV (HISPI_CLK_DIV),
.LANE0_DLY (1.3),
.LANE0_DLY (1.2), // 1.3), 1.3 not stable with default delays
.LANE1_DLY (2.7),
.LANE2_DLY (0.2),
.LANE3_DLY (1.8),
......@@ -2208,7 +2208,7 @@ simul_axi_hp_wr #(
.FULL_HEIGHT (HISPI_FULL_HEIGHT),
.CLOCK_MPY (HISPI_CLK_MULT),
.CLOCK_DIV (HISPI_CLK_DIV),
.LANE0_DLY (1.3),
.LANE0_DLY (1.2), // 1.3), 1.3 not stable with default delays
.LANE1_DLY (2.7),
.LANE2_DLY (0.2),
.LANE3_DLY (1.8),
......@@ -2623,6 +2623,7 @@ task setup_sensor_channel;
reg [31:0] frame_start_address;
reg [31:0] frame_start_address_inc;
reg [31:0] last_buf_frame;
reg [31:0] cmode; // compressor mode
// reg [31:0] camsync_delay;
// reg [ 3:0] sensor_mask;
......@@ -2632,6 +2633,13 @@ task setup_sensor_channel;
// Setting up a single sensor channel 0, sunchannel 0
//
begin
case (num_sensor)
2'h0: cmode = SIMULATE_CMPRS_CMODE0;
2'h1: cmode = SIMULATE_CMPRS_CMODE1;
2'h2: cmode = SIMULATE_CMPRS_CMODE2;
2'h3: cmode = SIMULATE_CMPRS_CMODE3;
endcase
window_height = FULL_HEIGHT;
window_left = 0;
window_top = 0;
......@@ -2688,49 +2696,112 @@ task setup_sensor_channel;
compressor_run (num_sensor, 0); // reset compressor
setup_compressor_channel(
num_sensor, // sensor channel number (0..3)
0, // qbank; // [6:3] quantization table page - 100% quality
// 1, // qbank; // [6:3] quantization table page - 85%? quality
1, // dc_sub; // [8:7] subtract DC
CMPRS_CBIT_CMODE_JPEG18, //input [31:0] cmode; // [13:9] color mode:
// parameter CMPRS_CBIT_CMODE_JPEG18 = 4'h0, // color 4:2:0
// parameter CMPRS_CBIT_CMODE_MONO6 = 4'h1, // mono 4:2:0 (6 blocks)
// parameter CMPRS_CBIT_CMODE_JP46 = 4'h2, // jp4, 6 blocks, original
// parameter CMPRS_CBIT_CMODE_JP46DC = 4'h3, // jp4, 6 blocks, dc -improved
// parameter CMPRS_CBIT_CMODE_JPEG20 = 4'h4, // mono, 4 blocks (but still not actual monochrome JPEG as the blocks are scanned in 2x2 macroblocks)
// parameter CMPRS_CBIT_CMODE_JP4 = 4'h5, // jp4, 4 blocks, dc-improved
// parameter CMPRS_CBIT_CMODE_JP4DC = 4'h6, // jp4, 4 blocks, dc-improved
// parameter CMPRS_CBIT_CMODE_JP4DIFF = 4'h7, // jp4, 4 blocks, differential
// parameter CMPRS_CBIT_CMODE_JP4DIFFHDR = 4'h8, // jp4, 4 blocks, differential, hdr
// parameter CMPRS_CBIT_CMODE_JP4DIFFDIV2 = 4'h9, // jp4, 4 blocks, differential, divide by 2
// parameter CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = 4'ha, // jp4, 4 blocks, differential, hdr,divide by 2
// parameter CMPRS_CBIT_CMODE_MONO1 = 4'hb, // mono JPEG (not yet implemented)
// parameter CMPRS_CBIT_CMODE_MONO4 = 4'he, // mono 4 blocks
1, // input [31:0] multi_frame; // [15:14] 0 - single-frame buffer, 1 - multiframe video memory buffer
3, // 0, // input [31:0] bayer; // [20:18] // Bayer shift
0, // input [31:0] focus_mode; // [23:21] Set focus mode
3, // num_macro_cols_m1; // number of macroblock colums minus 1
1, // num_macro_rows_m1; // number of macroblock rows minus 1
1, // input [31:0] left_margin; // left margin of the first pixel (0..31) for 32-pixel wide colums in memory access
'h120, // input [31:0] colorsat_blue; //color saturation for blue (10 bits) //'h90 for 100%
'h16c, // colorsat_red; //color saturation for red (10 bits) // 'b6 for 100%
0); // input [31:0] coring; // coring value
if (cmode == CMPRS_CBIT_CMODE_JPEG18) begin
setup_compressor_channel(
num_sensor, // sensor channel number (0..3)
0, // qbank; // [6:3] quantization table page - 100% quality
// 1, // qbank; // [6:3] quantization table page - 85%? quality
1, // dc_sub; // [8:7] subtract DC
cmode, // CMPRS_CBIT_CMODE_JPEG18, //input [31:0] cmode; // [13:9] color mode:
// parameter CMPRS_CBIT_CMODE_JPEG18 = 4'h0, // color 4:2:0
// parameter CMPRS_CBIT_CMODE_MONO6 = 4'h1, // mono 4:2:0 (6 blocks)
// parameter CMPRS_CBIT_CMODE_JP46 = 4'h2, // jp4, 6 blocks, original
// parameter CMPRS_CBIT_CMODE_JP46DC = 4'h3, // jp4, 6 blocks, dc -improved
// parameter CMPRS_CBIT_CMODE_JPEG20 = 4'h4, // mono, 4 blocks (but still not actual monochrome JPEG as the blocks are scanned in 2x2 macroblocks)
// parameter CMPRS_CBIT_CMODE_JP4 = 4'h5, // jp4, 4 blocks, dc-improved
// parameter CMPRS_CBIT_CMODE_JP4DC = 4'h6, // jp4, 4 blocks, dc-improved
// parameter CMPRS_CBIT_CMODE_JP4DIFF = 4'h7, // jp4, 4 blocks, differential
// parameter CMPRS_CBIT_CMODE_JP4DIFFHDR = 4'h8, // jp4, 4 blocks, differential, hdr
// parameter CMPRS_CBIT_CMODE_JP4DIFFDIV2 = 4'h9, // jp4, 4 blocks, differential, divide by 2
// parameter CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = 4'ha, // jp4, 4 blocks, differential, hdr,divide by 2
// parameter CMPRS_CBIT_CMODE_MONO1 = 4'hb, // mono JPEG (not yet implemented)
// parameter CMPRS_CBIT_CMODE_MONO4 = 4'he, // mono 4 blocks
1, // input [31:0] multi_frame; // [15:14] 0 - single-frame buffer, 1 - multiframe video memory buffer
3, // 0, // input [31:0] bayer; // [20:18] // Bayer shift
0, // input [31:0] focus_mode; // [23:21] Set focus mode
3, // num_macro_cols_m1; // number of macroblock colums minus 1
1, // num_macro_rows_m1; // number of macroblock rows minus 1
1, // input [31:0] left_margin; // left margin of the first pixel (0..31) for 32-pixel wide colums in memory access
'h120, // input [31:0] colorsat_blue; //color saturation for blue (10 bits) //'h90 for 100%
'h16c, // colorsat_red; //color saturation for red (10 bits) // 'b6 for 100%
0); // input [31:0] coring; // coring value
// TODO: calculate widths correctly!
setup_compressor_memory (
num_sensor, // input [1:0] num_sensor;
frame_start_address, // input [31:0] frame_sa; // 22-bit frame start address ((3 CA LSBs==0. BA==0)
frame_start_address_inc, // input [31:0] frame_sa_inc; // 22-bit frame start address increment ((3 CA LSBs==0. BA==0)
last_buf_frame, // input [31:0] last_frame_num; // 16-bit number of the last frame in a buffer
frame_full_width, // input [31:0] frame_full_width; // 13-bit Padded line length (8-row increment), in 8-bursts (16 bytes)
window_width, // & ~3, // input [31:0] window_width; // 13 bit - in 8*16=128 bit bursts
window_height & ~15, // input [31:0] window_height; // 16 bit
window_left, // input [31:0] window_left;
window_top+1, // input [31:0] window_top; (to match 20x20 tiles in 353)
1, // input byte32; // == 1?
2, //input [31:0] tile_width; // == 2
1, // input [31:0] extra_pages; // 1
1); // disable "need" (yield to sensor channels)
setup_compressor_memory (
num_sensor, // input [1:0] num_sensor;
frame_start_address, // input [31:0] frame_sa; // 22-bit frame start address ((3 CA LSBs==0. BA==0)
frame_start_address_inc, // input [31:0] frame_sa_inc; // 22-bit frame start address increment ((3 CA LSBs==0. BA==0)
last_buf_frame, // input [31:0] last_frame_num; // 16-bit number of the last frame in a buffer
frame_full_width, // input [31:0] frame_full_width; // 13-bit Padded line length (8-row increment), in 8-bursts (16 bytes)
window_width, // & ~3, // input [31:0] window_width; // 13 bit - in 8*16=128 bit bursts
window_height & ~15, // input [31:0] window_height; // 16 bit
window_left, // input [31:0] window_left;
window_top+1, // input [31:0] window_top; (to match 20x20 tiles in 353)
1, // input byte32; // == 1?
2, //input [31:0] tile_width; // == 2
1, // input [31:0] extra_pages; // 1
1,
18, // reg [7:0] tile_height;
16 // reg [7:0] tile_vstep;
); // disable "need" (yield to sensor channels)
end else if ((cmode == CMPRS_CBIT_CMODE_JP46) ||
(cmode == CMPRS_CBIT_CMODE_JP46DC) ||
(cmode == CMPRS_CBIT_CMODE_JP4) ||
(cmode == CMPRS_CBIT_CMODE_JP4DC) ||
(cmode == CMPRS_CBIT_CMODE_JP4DIFF) ||
(cmode == CMPRS_CBIT_CMODE_JP4DIFFHDR) ||
(cmode == CMPRS_CBIT_CMODE_JP4DIFFDIV2) ||
(cmode == CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2)) begin
setup_compressor_channel(
num_sensor, // sensor channel number (0..3)
0, // qbank; // [6:3] quantization table page - 100% quality
// 1, // qbank; // [6:3] quantization table page - 85%? quality
1, // dc_sub; // [8:7] subtract DC
cmode, // CMPRS_CBIT_CMODE_JPEG18, //input [31:0] cmode; // [13:9] color mode:
// parameter CMPRS_CBIT_CMODE_JPEG18 = 4'h0, // color 4:2:0
// parameter CMPRS_CBIT_CMODE_MONO6 = 4'h1, // mono 4:2:0 (6 blocks)
// parameter CMPRS_CBIT_CMODE_JP46 = 4'h2, // jp4, 6 blocks, original
// parameter CMPRS_CBIT_CMODE_JP46DC = 4'h3, // jp4, 6 blocks, dc -improved
// parameter CMPRS_CBIT_CMODE_JPEG20 = 4'h4, // mono, 4 blocks (but still not actual monochrome JPEG as the blocks are scanned in 2x2 macroblocks)
// parameter CMPRS_CBIT_CMODE_JP4 = 4'h5, // jp4, 4 blocks, dc-improved
// parameter CMPRS_CBIT_CMODE_JP4DC = 4'h6, // jp4, 4 blocks, dc-improved
// parameter CMPRS_CBIT_CMODE_JP4DIFF = 4'h7, // jp4, 4 blocks, differential
// parameter CMPRS_CBIT_CMODE_JP4DIFFHDR = 4'h8, // jp4, 4 blocks, differential, hdr
// parameter CMPRS_CBIT_CMODE_JP4DIFFDIV2 = 4'h9, // jp4, 4 blocks, differential, divide by 2
// parameter CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = 4'ha, // jp4, 4 blocks, differential, hdr,divide by 2
// parameter CMPRS_CBIT_CMODE_MONO1 = 4'hb, // mono JPEG (not yet implemented)
// parameter CMPRS_CBIT_CMODE_MONO4 = 4'he, // mono 4 blocks
1, // input [31:0] multi_frame; // [15:14] 0 - single-frame buffer, 1 - multiframe video memory buffer
3, // 0, // input [31:0] bayer; // [20:18] // Bayer shift
0, // input [31:0] focus_mode; // [23:21] Set focus mode
window_width-1, // 3, // num_macro_cols_m1; // number of macroblock colums minus 1
1, // num_macro_rows_m1; // number of macroblock rows minus 1
0, // 1, // input [31:0] left_margin; // left margin of the first pixel (0..31) for 32-pixel wide colums in memory access
'bx, // n/a 'h120, // input [31:0] colorsat_blue; //color saturation for blue (10 bits) //'h90 for 100%
'bx, // n/a 'h16c, // colorsat_red; //color saturation for red (10 bits) // 'b6 for 100%
0); // input [31:0] coring; // coring value
// TODO: calculate widths correctly!
setup_compressor_memory (
num_sensor, // input [1:0] num_sensor;
frame_start_address, // input [31:0] frame_sa; // 22-bit frame start address ((3 CA LSBs==0. BA==0)
frame_start_address_inc, // input [31:0] frame_sa_inc; // 22-bit frame start address increment ((3 CA LSBs==0. BA==0)
last_buf_frame, // input [31:0] last_frame_num; // 16-bit number of the last frame in a buffer
frame_full_width, // input [31:0] frame_full_width; // 13-bit Padded line length (8-row increment), in 8-bursts (16 bytes)
window_width, // & ~3, // input [31:0] window_width; // 13 bit - in 8*16=128 bit bursts
window_height & ~15, // input [31:0] window_height; // 16 bit
window_left, // input [31:0] window_left;
window_top+0, // input [31:0] window_top; (to match 20x20 tiles in 353)
1, // input byte32; // == 1?
4, //input [31:0] tile_width; // == 2
0, // input [31:0] extra_pages; // 1
1,
16, // reg [7:0] tile_height;
16 // reg [7:0] tile_vstep;
); // disable "need" (yield to sensor channels)
end else begin
$display ("task setup_compressor_channel(): compressor mode %d is not supported",cmode);
$finish;
end
// compressor_run (num_sensor, 3); // run repetitive mode
`ifndef COMPRESS_SINGLE
......@@ -2741,8 +2812,11 @@ task setup_sensor_channel;
set_sensor_io_dly (
num_sensor, // input [1:0] num_sensor;
`ifdef HISPI
128'h33404850_58606870_000000e4_00000007); // input [127:0] dly; // {delays_delays_lane-map_fifo-start_delay]
`else
128'h33404850_58606870_78808890_98a0a8b0 ); //input [127:0] dly; // {mmsm_phase, bpf, vact, hact, pxd11,...,pxd0]
`endif
TEST_TITLE = "IO_SETUP";
$display("===================== TEST_%s =========================",TEST_TITLE);
set_sensor_io_width(
......@@ -3169,14 +3243,16 @@ task setup_compressor_memory;
input [31:0] tile_width; // == 2
input [31:0] extra_pages; // 1
input disable_need; // set to 1
input [7:0] tile_height;
input [7:0] tile_vstep;
reg [29:0] base_addr;
integer mode;
reg [7:0] tile_height;
reg [7:0] tile_vstep;
// reg [7:0] tile_height;
// reg [7:0] tile_vstep;
begin
tile_vstep = 16;
tile_height= 18;
// tile_vstep = 16;
// tile_height= 18;
base_addr = MCONTR_CMPRS_BASE + MCONTR_CMPRS_INC * num_sensor;
......
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