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Commit 944ff196 authored by Andrey Filippov's avatar Andrey Filippov
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Merge branch 'serial-sensors' to master

parents 8af3d0c0 2413557f
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.project
View file @ 944ff196
......@@ -62,42 +62,42 @@
<link>
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<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
......
axi/cmprs_afi_mux.v
View file @ 944ff196
......@@ -195,11 +195,12 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
// reg [2:0] cur_chn; // 'b0xx - none, 'b1** - ** - channel number (should match fifo_ren*)
reg [1:0] cur_chn; // 'b0xx - none, 'b1** - ** - channel number (should match fifo_ren*)
reg [31:0] left_to_eof; // number of chunks left to end of frame
reg [31:0] left_to_eof; // number of chunks left to end of frame (one less: 3 means 4 left)
reg [3:0] fifo_flush_d; // fifo_flush* delayed by 1 clk (to detect rising edge
reg [3:0] eof_stb; // single-cycle pulse after fifo_flush is asserted
// reg [1:0] w64_cnt; // count 64-bit words in a chunk
// adjusted counters used for channel arbitration
// pessimistic FIFO content counter - decrements (form FIFO counter) on FIFO reads, knows nothing of writes
reg [35:0] counts_corr0; // registers to hold corrected (decremented currently processed ones if any) fifo count values, MSB - needs flush
reg [17:0] counts_corr1; // first arbitration level winning values
reg [8:0] counts_corr2; // second arbitration level winning values
......@@ -231,6 +232,8 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
// 3'h4 :
// ({1'b0,left_to_eof[winner2 * 8 +: 2]} + 3'h1);
// Why it has priority for |counts_corr2[7:2] ? If next frame started, it may skip EOF? Or not?
// it is just to pass to a channel, actual transfer size will be decided here (depending on EOF)
wire [1:0] pre_chunk_inc_m1 = (|counts_corr2[7:2])? // Would like to increment, if not roll-over
2'h3 :
left_to_eof[winner2 * 8 +: 2];
......@@ -252,12 +255,15 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
wire [26:0] chunk_ptr_rd;
wire [ 3:0] chunk_ptr_ra;
// If flushing - whatever is left to EOF, otherwise corrected FIFO contents of the winner
wire [ 7:0] items_left = counts_corr2[8] ? left_to_eof[(winner2 * 8) +: 8] : counts_corr2[7:0];
reg [5:0] afi_awid_r;
// "rollover" - roll over destination memory range
wire [2:0] max_wlen; // 0,1,2,3,7 (7 - not limited by rollover) - calculated by cmprs_afi_mux_ptr
wire [1:0] want_wleft32 = (|items_left[7:2])? 2'b11 : items_left[1:0]; // want to set wleft[3:2] if not roll-over
// wants to write (want_wleft32+1) 32-byte chunks (4,3,2,1)
wire [1:0] want_wleft32 = (|items_left[7:2])? 2'b11 : items_left[1:0]; // want to set wleft[3:2] if not roll-over (actually "3" means 2)
assign cmd_we_status_w = cmd_we && ((cmd_a & 'hc) == CMPRS_AFIMUX_STATUS_CNTRL);
assign cmd_we_mode_w = cmd_we && (cmd_a == CMPRS_AFIMUX_MODE);
......@@ -366,16 +372,22 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
// TODO: change &w64_cnt[1:0] so left_to_eof[*] will be updated earlier and valid at pre_busy_w
// Done, updating at the first (not last) word of 4
// Now seems that eof_stb[i] & fifo_ren{i} == 0
if (eof_stb[0]) left_to_eof[0 * 8 +: 8] <= fifo_count0_m1 - (fifo_ren0 & (&wleft[1:0]));
// Seems needs to decrement fifo_count0_m1 regardless of &wleft[1:0] - if started, will eventually decrement
// How to make sure that decremented value always >0?
// if (eof_stb[0]) left_to_eof[0 * 8 +: 8] <= fifo_count0_m1 - (fifo_ren0 & (&wleft[1:0]));
if (eof_stb[0]) left_to_eof[0 * 8 +: 8] <= fifo_count0_m1 - fifo_ren0;
else if (fifo_ren0 & (&wleft[1:0])) left_to_eof[0 * 8 +: 8] <= left_to_eof[0 * 8 +: 8] - 1;
if (eof_stb[1]) left_to_eof[1 * 8 +: 8] <= fifo_count1_m1 - (fifo_ren1 & (&wleft[1:0]));
// if (eof_stb[1]) left_to_eof[1 * 8 +: 8] <= fifo_count1_m1 - (fifo_ren1 & (&wleft[1:0]));
if (eof_stb[1]) left_to_eof[1 * 8 +: 8] <= fifo_count1_m1 - fifo_ren1;
else if (fifo_ren1 & (&wleft[1:0])) left_to_eof[1 * 8 +: 8] <= left_to_eof[1 * 8 +: 8] - 1;
if (eof_stb[2]) left_to_eof[2 * 8 +: 8] <= fifo_count2_m1 - (fifo_ren2 & (&wleft[1:0]));
// if (eof_stb[2]) left_to_eof[2 * 8 +: 8] <= fifo_count2_m1 - (fifo_ren2 & (&wleft[1:0]));
if (eof_stb[2]) left_to_eof[2 * 8 +: 8] <= fifo_count2_m1 - fifo_ren2;
else if (fifo_ren2 & (&wleft[1:0])) left_to_eof[2 * 8 +: 8] <= left_to_eof[2 * 8 +: 8] - 1;
if (eof_stb[3]) left_to_eof[3 * 8 +: 8] <= fifo_count3_m1 - (fifo_ren3 & (&wleft[1:0]));
// if (eof_stb[3]) left_to_eof[3 * 8 +: 8] <= fifo_count3_m1 - (fifo_ren3 & (&wleft[1:0]));
if (eof_stb[3]) left_to_eof[3 * 8 +: 8] <= fifo_count3_m1 - fifo_ren3;
else if (fifo_ren3 & (&wleft[1:0])) left_to_eof[3 * 8 +: 8] <= left_to_eof[3 * 8 +: 8] - 1;
// Calculate corrected values decrementing currently served channel (if any) values by 1 (latency 1 clk)
......
axi/membridge.v
View file @ 944ff196
......@@ -749,6 +749,7 @@ wire [63:0] afi_wdata0;
.ext_rd (bufrd_rd[0]), // input
.ext_regen (bufrd_rd[1]), // input
.ext_data_out (afi_wdata0), // output[63:0]
// .emul64 (1'b0), // input Modify buffer addresses (used for JP4 until a 64-wide mode is implemented)
.wclk (!mclk), // input
.wpage_in (2'b0), // input[1:0]
.wpage_set (xfer_reset_page_rd), // input TODO: Generate @ negedge mclk on frame start
......
compressor_jp/bit_stuffer_metadata.v
View file @ 944ff196
......@@ -146,7 +146,7 @@ module bit_stuffer_metadata(
// just for testing
`ifdef DEBUG_RING
assign dbg_ = ts_rstb;
assign dbg_ts_rstb = ts_rstb;
assign dbg_ts_dout = ts_dout;
always @ (posedge xclk) begin
......
compressor_jp/cmprs_pixel_buf_iface.v
View file @ 944ff196
......@@ -67,9 +67,11 @@ module cmprs_pixel_buf_iface #(
// controller this can just be the same as mb_pre_end_in
input mb_pre_start, // 1 clock cycle before stream of addresses to the buffer
input [ 1:0] start_page, // page to read next tile from (or first of several pages)
input [ 6:0] macroblock_x, // macroblock left pixel x relative to a tile (page) Maximal page - 128 bytes wide
input [ 6:0] macroblock_x, // macroblock left pixel x relative to a tile (page) Maximal page - 128 bytes wide.
// valid 3 cycles before mb_pre_start
output reg [ 7:0] data_out, //
output pre_first_out, // For each macroblock in a frame
output pre2_first_out, // 1 cycle before pre_first_out
output reg data_valid //
);
localparam PERIOD_COLOR18 = 384; // >18*18, limited by 6*64 (macroblocks)
......@@ -105,8 +107,13 @@ module cmprs_pixel_buf_iface #(
reg [ 8:0] period_cntr;
reg mb_pre_end_r;
reg mb_release_buf_r;
reg pre_first_out_r;
reg [CMPRS_BUF_EXTRA_LATENCY+2:0] pre_first_out_r;
reg [ 2:0] mb_col_number; // number of tile column where macrobloc starts - valid 2 cycles before mb_pre_start
wire [ 9:0] extra_start_addr_w = mb_col_number * mb_h_m1; //added to mb_start_addr when non-zero column
reg [ 5:0] extra_start_addr_r;
// reg [ 5:0] mb_h; // macroblock height (lost MSB - OK)
reg [ 9:0] mb_start_addr; // was macroblock_x, noccrected for multi-column. valid with mb_pre_start
assign buf_ra = bufa_r;
assign tile_width_or= tile_width[1]?(tile_width[0]?0:'h40):(tile_width[0]?'h60:'h70);
......@@ -119,21 +126,31 @@ module cmprs_pixel_buf_iface #(
assign mb_release_buf = mb_release_buf_r;
assign buf_rd = buf_re[1:0];
// assign data_out = do_r;
assign pre_first_out = pre_first_out_r;
assign pre_first_out = pre_first_out_r[0];
assign pre2_first_out = pre_first_out_r[1];
always @(posedge xclk) begin
// mb_h <= mb_h_m1+1; // macroblock height
mb_col_number <= {macroblock_x[6:5],tile_col_width?1'b0:macroblock_x[4]};
extra_start_addr_r <= extra_start_addr_w[5:0];
mb_start_addr <= {3'b0,macroblock_x} + {extra_start_addr_r,4'b0};
if (!frame_en) buf_re[0] <= 0;
else if (mb_pre_start) buf_re[0] <= 1'b1;
else if (addr_run_end) buf_re[0] <= 1'b0;
if (!frame_en) buf_re[CMPRS_BUF_EXTRA_LATENCY+3:1] <= 0;
else buf_re[CMPRS_BUF_EXTRA_LATENCY+3:1] <= {buf_re[CMPRS_BUF_EXTRA_LATENCY+2:0]};
else buf_re[CMPRS_BUF_EXTRA_LATENCY+3:1] <= {buf_re[CMPRS_BUF_EXTRA_LATENCY + 2:0]};
// Buffer data read:
if (buf_re[CMPRS_BUF_EXTRA_LATENCY+2]) data_out <= buf_di;
//mb_pre_start
if (!frame_en) pre_first_out_r <= 0;
else pre_first_out_r <= buf_re[CMPRS_BUF_EXTRA_LATENCY+1] && ! buf_re[CMPRS_BUF_EXTRA_LATENCY+2];
else pre_first_out_r <= {mb_pre_start, pre_first_out_r[CMPRS_BUF_EXTRA_LATENCY + 2 : 1]};
// else pre_first_out_r <= buf_re[CMPRS_BUF_EXTRA_LATENCY+1] && ! buf_re[CMPRS_BUF_EXTRA_LATENCY+2];
// if (!frame_en) pre2_first_out <= 0;
// else pre2_first_out <= buf_re[CMPRS_BUF_EXTRA_LATENCY + 0] && ! buf_re[CMPRS_BUF_EXTRA_LATENCY + 1];
if (mb_pre_start) rows_left <= mb_h_m1;
else if (last_col) rows_left <= rows_left - 1;
......@@ -153,7 +170,8 @@ module cmprs_pixel_buf_iface #(
first_col <= (mb_pre_start || (last_col && !last_row));
if (mb_pre_start) row_sa <= {start_page,3'b0,macroblock_x};
// if (mb_pre_start) row_sa <= {start_page,3'b0,mb_start_addr}; // macroblock_x};
if (mb_pre_start) row_sa <= {start_page,mb_start_addr}; // macroblock_x};
else if (first_col) row_sa <= row_sa + (tile_col_width ? 12'h20:12'h10);
if (mb_pre_start) tile_sa <= 0;
......@@ -172,7 +190,8 @@ module cmprs_pixel_buf_iface #(
else if (last_in_tile) bufa_r[11:10] <= bufa_r[11:10] + 1;
// Most time critical - calculation of the buffer address
if (mb_pre_start) bufa_r[9:0] <= {3'b0,macroblock_x};
// if (mb_pre_start) bufa_r[9:0] <= {3'b0,mb_start_addr}; // macroblock_x};
if (mb_pre_start) bufa_r[9:0] <= {mb_start_addr}; // macroblock_x};
else if (last_col) bufa_r[9:0] <= row_sa[9:0]; // 'bx next cycle after AFTER mb_pre_start
else if (last_in_tile) bufa_r[9:0] <= tile_sa;
else if (buf_re[0]) bufa_r[9:0] <= bufa_r[9:0] + {last_in_col?col_inc[9:4]:6'b0,4'b1};
......
compressor_jp/csconvert.v
View file @ 944ff196
......@@ -55,7 +55,7 @@ module csconvert#(
input [ 9:0] m_cr, // [9:0] scale for CB - default 0.713 (10'hb6)
input [ 7:0] mb_din, // input bayer data in scanline sequence, GR/BG sequence
input [ 1:0] bayer_phase,
input pre_first_in, // marks the first input pixel
input pre2_first_in, // marks the first input pixel (2 cycles ahead)
output reg [ 8:0] signed_y, // - now signed char, -128(black) to +127 (white)
output reg [ 8:0] signed_c, // new, q is just signed char
......@@ -69,7 +69,7 @@ module csconvert#(
// output reg ccv_out_start, //TODO: adjust to minimal latency?
output reg [ 7:0] n000, // not clear how they are used, make them just with latency1 from old
output reg [ 7:0] n255);
reg pre_first_in;
// outputs to be multiplexed:
wire [7:0] conv18_signed_y, conv20_signed_y, mono16_signed_y, jp4_signed_y;
wire [8:0] jp4diff_signed_y, conv18_signed_c, conv20_signed_c;
......@@ -100,7 +100,8 @@ module csconvert#(
reg [5:0] component_firstsS; // first_r this component in a frame (DC absolute, otherwise - difference to previous)
*/
always @ (posedge xclk) begin
if (pre_first_in) begin
pre_first_in <= pre2_first_in;
if (pre2_first_in) begin
converter_type_r [2:0] <= converter_type[2:0];
ignore_color_r <= ignore_color;
// jp4_dc_improved_r <= jp4_dc_improved;
......@@ -117,22 +118,22 @@ module csconvert#(
// generate one-hot converter enable
if (!frame_en) en_converters[CMPRS_COLOR18] <= 0;
else if (pre_first_in) en_converters[CMPRS_COLOR18] <= converter_type == CMPRS_COLOR18;
else if (pre2_first_in) en_converters[CMPRS_COLOR18] <= converter_type == CMPRS_COLOR18;
if (!frame_en) en_converters[CMPRS_COLOR20] <= 0;
else if (pre_first_in) en_converters[CMPRS_COLOR20] <= converter_type == CMPRS_COLOR20;
else if (pre2_first_in) en_converters[CMPRS_COLOR20] <= converter_type == CMPRS_COLOR20;
if (!frame_en) en_converters[CMPRS_MONO16] <= 0;
else if (pre_first_in) en_converters[CMPRS_MONO16] <= converter_type == CMPRS_MONO16;
else if (pre2_first_in) en_converters[CMPRS_MONO16] <= converter_type == CMPRS_MONO16;
if (!frame_en) en_converters[CMPRS_JP4] <= 0;
else if (pre_first_in) en_converters[CMPRS_JP4] <= converter_type == CMPRS_JP4;
else if (pre2_first_in) en_converters[CMPRS_JP4] <= converter_type == CMPRS_JP4;
if (!frame_en) en_converters[CMPRS_JP4DIFF] <= 0;
else if (pre_first_in) en_converters[CMPRS_JP4DIFF] <= converter_type == CMPRS_JP4DIFF;
else if (pre2_first_in) en_converters[CMPRS_JP4DIFF] <= converter_type == CMPRS_JP4DIFF;
if (!frame_en) en_converters[CMPRS_MONO8] <= 0;
else if (pre_first_in) en_converters[CMPRS_MONO8] <= converter_type == CMPRS_MONO8;
else if (pre2_first_in) en_converters[CMPRS_MONO8] <= converter_type == CMPRS_MONO8;
end
......
compressor_jp/huffman_stuffer_meta.v
View file @ 944ff196
......@@ -161,6 +161,11 @@ module huffman_stuffer_meta(
.data_out_valid (data_out_valid), // output reg
.done (done), // output reg
.running (running) // output reg
`ifdef DEBUG_RING
,.dbg_etrax_dma (dbg_etrax_dma), // output[3:0] reg
.dbg_ts_rstb (dbg_ts_rstb), // output
.dbg_ts_dout (dbg_ts_dout) // output[7:0]
`endif
);
endmodule
......
compressor_jp/jp_channel.v
View file @ 944ff196
......@@ -262,6 +262,7 @@ module jp_channel#(
// signals connecting modules: chn_rd_buf_i and ???:
wire [ 7:0] mb_data_out; // Macroblock data out in scanline order
wire mb_pre_first_out; // Macroblock data out strobe - 1 cycle just before data valid
wire mb_pre2_first_out; // Macroblock data out strobe - 2 cycles just before data valid
// wire mb_data_valid; // Macroblock data out valid
wire limit_diff = 1'b1; // as in the prototype - just a constant 1
......@@ -376,6 +377,7 @@ module jp_channel#(
// wire flush; // output reg @ negedge xclk2x
wire last_block = 0; // @negedge xxlk2x - used to copy timestamp in stuffer
wire stuffer_rdy = 1; // receiver (bit stuffer) is ready to accept data;
wire xrst2xn = xrst;
`endif
......@@ -418,7 +420,19 @@ module jp_channel#(
reg [15:0] dbg_zds_cntr;
wire [2:0] dbg_block_mem_wa;
wire [2:0] dbg_block_mem_wa_save;
`ifndef USE_XCLK2X
// temporarily assigning unused debug signals to 0
// assign dbg_add_invalid = 0;
// assign dbg_mb_release_buf = 0;
// assign etrax_dma = 0;
// assign dbg_ts_rstb = 0; // output
// assign dbg_ts_dout = 0; //output [7:0]
assign dbg_flushing = 0; // still not used in huffman_stuffer_meta
// assign dbg_test_lbw = 0;
// assign dbg_gotLastBlock = 0;
assign dbg_fifo_or_full = 0; // still not used in huffman_stuffer_meta
`endif
timestamp_to_parallel dbg_timestamp_to_parallel_i (
`ifdef USE_XCLK2X
.clk (~xclk2x), // input
......@@ -428,7 +442,7 @@ module jp_channel#(
.pre_stb (dbg_ts_rstb), // input
.tdata (dbg_ts_dout), // input[7:0]
.sec (dbg_sec), // output[31:0] reg
.usec (dbg_usec), // output[19:0] reg
.usec (dbg_usec[19:0]), // output[19:0] reg
.done() // output
);
......@@ -599,7 +613,13 @@ module jp_channel#(
.start (status_start) // input
);
//hifreq
// Port buffer - TODO: Move to memory controller
// Not needed?
// reg emul64;
// always @ (negedge mclk) begin
// emul64 <= tile_width[1]; // will not work for monochrome (128 pixel wide) - chnge to 64?
// end
mcntrl_buf_rd #(
.LOG2WIDTH_RD(3) // 64 bit external interface
) chn_rd_buf_i (
......@@ -608,6 +628,7 @@ module jp_channel#(
.ext_rd (buf_rd[0]), // input
.ext_regen (buf_rd[1]), // input
.ext_data_out (buf_pxd), // output[7:0]
// .emul64 (1'b0), //emul64), // input Modify buffer addresses (used for JP4 until a 64-wide mode is implemented)
.wclk (!mclk), // input
.wpage_in (2'b0), // input[1:0]
.wpage_set (xfer_reset_page_rd), // input TODO: Generate @ negedge mclk on frame start
......@@ -824,7 +845,8 @@ module jp_channel#(
.data_out (mb_data_out), // output[7:0] // Macroblock data out in scanline order
.pre_first_out (mb_pre_first_out), // output // Macroblock data out strobe - 1 cycle just before data valid == old pre_first_pixel?
// .data_valid (mb_data_valid) // output // Macroblock data out valid
.data_valid () // output // Macroblock data out valid Unused
.pre2_first_out (mb_pre2_first_out), // output reg
.data_valid () // output reg // Macroblock data out valid Unused
);
csconvert #(
......@@ -846,7 +868,7 @@ module jp_channel#(
.m_cr (m_cr), // input[9:0]
.mb_din (mb_data_out), // input[7:0]
.bayer_phase (bayer_phase), // input[1:0]
.pre_first_in (mb_pre_first_out), // input
.pre2_first_in (mb_pre2_first_out),// input
.signed_y (signed_y), // output[8:0] reg
.signed_c (signed_c), // output[8:0] reg
.yaddrw (yaddrw), // output[7:0] reg
......
fpga_version.vh
View file @ 944ff196
......@@ -31,8 +31,18 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
parameter FPGA_VERSION = 32'h0393006a; // modified clock generation, trying with HiSPi - 72.77% utilization
parameter FPGA_VERSION = 32'h03930071; // Fixing AXI HP multiplexer xclk -0.083 -1.968 44 / 15163 (77.17%)
// parameter FPGA_VERSION = 32'h03930070; // Fixing HiSPi xclk -0.049 -0.291 17, utilization 15139 (77.04%)
// parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xcl -0.002 -0.004 2, utilization 15144 (77.07 %)
// parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xclk -0.209/-2.744/23, utilization 15127 (76.98%)
// parameter FPGA_VERSION = 32'h0393006e; // Trying lane switch again after bug fix, failing 1 in ddr3_mclk -> ddr3_clk_div by -0.023
// parameter FPGA_VERSION = 32'h0393006d; // -1 with lane switch - does not work
// parameter FPGA_VERSION = 32'h0393006d; // Reversing pixels/lanes order xclk violated -0.154
// parameter FPGA_VERSION = 32'h0393006c; // will try debug for HiSPi. xclk violated by -0.030, slices 15062 (76.65%)
// parameter FPGA_VERSION = 32'h0393006b; // Correcting sensor external clock generation - was wrong division. xclk violated by 0.095 ns
// parameter FPGA_VERSION = 32'h0393006a; // modified clock generation, trying with HiSPi - 72.77% utilization x40..x60
// parameter FPGA_VERSION = 32'h03930069; // modified clock generation, rebuilding for parallel sensors - all met, 71.8% utilization
// Worked OK, but different phase for sensor 0 (all quadrants as 1,3 OK)
// parameter FPGA_VERSION = 32'h03930068; // trying BUFR/FUFIO on all sensors ipclk/ipclk2x
// parameter FPGA_VERSION = 32'h03930067; // removing DUMMY_TO_KEEP, moving IOSTANDARD to HDL code
// parameter FPGA_VERSION = 32'h03930066; // trying just one histogram to watch utilization - with 4 was: Slice 15913 (80.98%), now Slice = 14318 (72.87%)
......
includes/x393_parameters.vh
View file @ 944ff196
......@@ -598,7 +598,10 @@
parameter HISPI_MMCM1 = "FALSE",
parameter HISPI_MMCM2 = "TRUE",
parameter HISPI_MMCM3 = "FALSE",
parameter HISPI_KEEP_IRST = 5, // number of cycles to keep irst on after release of prst (small number - use 1 hot)
parameter HISPI_WAIT_ALL_LANES = 4'h8, // number of output pixel cycles to wait after the earliest lane
parameter HISPI_FIFO_DEPTH = 4,
parameter HISPI_FIFO_START = 7,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
parameter HISPI_DQS_BIAS = "TRUE",
......
includes/x393_simulation_parameters.vh
View file @ 944ff196
......@@ -41,7 +41,11 @@
parameter SIMUL_AXI_READ_WIDTH=16,
parameter MEMCLK_PERIOD = 5.0,
parameter FCLK0_PERIOD = 41.667, // 10.417, 24MHz
`ifdef HISPI
parameter FCLK0_PERIOD = 40.91, // 24.444MHz
`else
parameter FCLK0_PERIOD = 41.667, // 24MHz
`endif
parameter FCLK1_PERIOD = 0.0,
// parameter SENSOR12BITS_LLINE = 192, // 1664;// line duration in clocks
......@@ -55,6 +59,29 @@
parameter SENSOR_IMAGE_TYPE1 = "RUN1",
parameter SENSOR_IMAGE_TYPE2 = "NORM", // "RUN1",
parameter SENSOR_IMAGE_TYPE3 = "RUN1",
parameter SIMULATE_CMPRS_CMODE0 = CMPRS_CBIT_CMODE_JPEG18,
parameter SIMULATE_CMPRS_CMODE1 = CMPRS_CBIT_CMODE_JPEG18,
parameter SIMULATE_CMPRS_CMODE2 = CMPRS_CBIT_CMODE_JP4,
parameter SIMULATE_CMPRS_CMODE3 = CMPRS_CBIT_CMODE_JP4,
// CMPRS_CBIT_CMODE_JPEG18, //input [31:0] cmode; // [13:9] color mode:
// parameter CMPRS_CBIT_CMODE_JPEG18 = 4'h0, // color 4:2:0
// parameter CMPRS_CBIT_CMODE_MONO6 = 4'h1, // mono 4:2:0 (6 blocks)
// parameter CMPRS_CBIT_CMODE_JP46 = 4'h2, // jp4, 6 blocks, original
// parameter CMPRS_CBIT_CMODE_JP46DC = 4'h3, // jp4, 6 blocks, dc -improved
// parameter CMPRS_CBIT_CMODE_JPEG20 = 4'h4, // mono, 4 blocks (but still not actual monochrome JPEG as the blocks are scanned in 2x2 macroblocks)
// parameter CMPRS_CBIT_CMODE_JP4 = 4'h5, // jp4, 4 blocks, dc-improved
// parameter CMPRS_CBIT_CMODE_JP4DC = 4'h6, // jp4, 4 blocks, dc-improved
// parameter CMPRS_CBIT_CMODE_JP4DIFF = 4'h7, // jp4, 4 blocks, differential
// parameter CMPRS_CBIT_CMODE_JP4DIFFHDR = 4'h8, // jp4, 4 blocks, differential, hdr
// parameter CMPRS_CBIT_CMODE_JP4DIFFDIV2 = 4'h9, // jp4, 4 blocks, differential, divide by 2
// parameter CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = 4'ha, // jp4, 4 blocks, differential, hdr,divide by 2
// parameter CMPRS_CBIT_CMODE_MONO1 = 4'hb, // mono JPEG (not yet implemented)
// parameter CMPRS_CBIT_CMODE_MONO4 = 4'he, // mono 4 blocks
parameter SENSOR12BITS_NGPL = 8, // bpf to hact
parameter SENSOR12BITS_NVLO = 1, // VACT=0 in video mode (clocks)
//parameter tMD = 14; //
......
memctrl/mcntrl393.v
View file @ 944ff196
......@@ -947,6 +947,7 @@ module mcntrl393 #(
.ext_rd (buf2rd_rd), // input
.ext_regen (buf2rd_regen), // input
.ext_data_out (buf2rd_data), // output[31:0]
// .emul64 (1'b0), // input Modify buffer addresses (used for JP4 until a 64-wide mode is implemented)
.wclk (!mclk), // input
.wpage_in (2'b0), // input[1:0]
.wpage_set (xfer_reset_page2_rd), // input TODO: Generate @ negedge mclk on frame start
......@@ -982,6 +983,7 @@ module mcntrl393 #(
.ext_rd (buf3rd_rd), // input
.ext_regen (buf3rd_regen), // input
.ext_data_out (buf3rd_data), // output[31:0]
// .emul64 (1'b0), // input Modify buffer addresses (used for JP4 until a 64-wide mode is implemented)
.wclk (!mclk), // input
.wpage_in (2'b0), // input[1:0]
.wpage_set (xfer_reset_page3_rd), // input @ negedge mclk
......@@ -1017,6 +1019,7 @@ module mcntrl393 #(
.ext_rd (buf4rd_rd), // input
.ext_regen (buf4rd_regen), // input
.ext_data_out (buf4rd_data), // output[31:0]
// .emul64 (1'b0), // input Modify buffer addresses (used for JP4 until a 64-wide mode is implemented)
.wclk (!mclk), // input
.wpage_in (2'b0), // input[1:0]
.wpage_set (xfer_reset_page4_rd), // input @ negedge mclk
......
memctrl/mcntrl_buf_rd.v
View file @ 944ff196
......@@ -43,6 +43,8 @@ module mcntrl_buf_rd #(
input ext_regen, // output register enable
output [(1 << LOG2WIDTH_RD)-1:0] ext_data_out, // data out
// input emul64, // emulate 64 pixel wide reads with actual 32-wide columns
// in the future - use rd64/wr64 for JP4 mode
input wclk, // !mclk (inverted)
input [1:0] wpage_in, // will register to wclk, input OK with mclk
input wpage_set, // set internal write page to wpage_in
......@@ -54,6 +56,9 @@ module mcntrl_buf_rd #(
reg [1:0] page_r;
reg [6:0] waddr;
assign page=page_r;
// wire [4:0] next62_norm = waddr[6:2] + 1;
// wire [4:0] next62_rot = {waddr[2],waddr[6:3]} + 1;
// wire [4:0] next62_emul64 = {next62_rot[3:0],next62_rot[4]};
always @ (posedge wclk) begin
if (wpage_set) page_r <= wpage_in;
......@@ -61,6 +66,13 @@ module mcntrl_buf_rd #(
if (page_next || wpage_set) waddr <= 0;
else if (we) waddr <= waddr+1;
// if (page_next || wpage_set) waddr[1:0] <= 0;
// else if (we) waddr[1:0] <= waddr[1:0] + 1;
// if (page_next || wpage_set) waddr[6:2] <= 0;
// else if (we && (&waddr[1:0])) waddr[6:2] <= emul64 ? next62_emul64 : next62_norm;
end
// ram_512x64w_1kx32r #(
ram_var_w_var_r #(
......
memctrl/mcntrl_ps_pio.v
View file @ 944ff196
......@@ -252,9 +252,10 @@ fifo_same_clock #(
.ext_rd (port0_re), // input
.ext_regen (port0_regen), // input
.ext_data_out (port0_data), // output[31:0]
// .emul64 (1'b0), // input Modify buffer addresses (used for JP4 until a 64-wide mode is implemented)
.wclk (!mclk), // input
.wpage_in (page_out_r_negedge), // page_neg), // input[1:0]
.wpage_set (page_w_set_negedge), //wpage_set_chn0_neg), // input
.wpage_set (page_w_set_negedge), // wpage_set_chn0_neg), // input
.page_next (buf_wpage_nxt), // input
.page (), // output[1:0]
.we (buf_wr), // input
......@@ -270,7 +271,7 @@ fifo_same_clock #(
.ext_we (port1_we), // input
.ext_data_in (port1_data), // input[31:0]
.rclk (mclk), // input
.rpage_in (page_out_r), //page), // input[1:0]
.rpage_in (page_out_r), // page), // input[1:0]
.rpage_set (page_r_set), // rpage_set_chn1), // input
.page_next (buf_rpage_nxt), // input
.page (), // output[1:0]
......@@ -287,9 +288,9 @@ fifo_same_clock #(
.sync_rst (mrst || !nreset_page_fifo), // synchronously reset fifo;
.we (channel_pgm_en),
.re (buf_run),
.data_in ({cmd_wr,cmd_page}), //page),
.data_in ({cmd_wr,cmd_page}), // page),
.data_out ({cmd_wr_out,page_out}),
.nempty (), //page_fifo1_nempty),
.nempty (), // page_fifo1_nempty),
.half_full ()
);
......
py393/dbg/x393_mcntrl.pickle
View file @ 944ff196
This diff is collapsed.
py393/hargs
View file @ 944ff196
......@@ -3,4 +3,5 @@
-f /usr/local/verilog/x393_parameters.vh /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh
-l /usr/local/verilog/x393_cur_params_target.vh
-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
-c copy /usr/local/bin/imgsrv.py /www/pages
-i
\ No newline at end of file
py393/imgsrv.py 0 → 100644
View file @ 944ff196
#!/usr/bin/python
from __future__ import division
from __future__ import print_function
'''
# Copyright (C) 2015, Elphel.inc.
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http:#www.gnu.org/licenses/>.
@author: Andrey Filippov
@copyright: 2015 Elphel, Inc.
@license: GPLv3.0+
@contact: andrey@elphel.coml
@deffield updated: Updated
'''
__author__ = "Andrey Filippov"
__copyright__ = "Copyright 2015, Elphel, Inc."
__license__ = "GPL"
__version__ = "3.0+"
__maintainer__ = "Andrey Filippov"
__email__ = "andrey@elphel.com"
__status__ = "Development"
import os
import urlparse
import time
import socket
import shutil
import sys
path="/www/pages/img.jpeg"
PORT=8888
def communicate(port,snd_str):
sock = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
sock.connect(('localhost', port))
sock.send(snd_str)
reply = sock.recv(16384) # limit reply to 16K
sock.close()
return reply
try:
qs=urlparse.parse_qs(os.environ['QUERY_STRING'])
except:
print("failed in os.environ['QUERY_STRING']")
qs={}
acquisition_parameters={
"file_path": "img.jpeg",
"channel": "0",
"cmode": "0",
"bayer": None,
"y_quality": None,
"c_quality": None,
"portrait": None,
"gamma": None,
"black": None,
"colorsat_blue":None,
"colorsat_red": None,
"server_root": "/www/pages/",
"gain_r": None,
"gain_gr": None,
"gain_gb": None,
"gain_b": None,
"expos": None,
"flip_x": None,
"flip_y": None,
"verbose": "0"}
for k in qs:
if k == "cmode":
if qs[k][0].upper() == "JP4":
acquisition_parameters[k] = "5"
else:
acquisition_parameters[k] = "0"
else:
acquisition_parameters[k] = qs[k][0]
#correct bayer (if specified) for flips
if ((not acquisition_parameters["bayer"] is None) and
((not acquisition_parameters["flip_x"] is None) or
(not acquisition_parameters["flip_y"] is None))):
ibayer= int (acquisition_parameters["bayer"])
if acquisition_parameters["flip_x"]:
if int (acquisition_parameters["flip_x"]):
ibayer ^= 1
if int (acquisition_parameters["flip_y"]):
ibayer ^= 2
acquisition_parameters["bayer"] = str(ibayer)
cmd_str = "jpeg_acquire_write %s %s %s %s %s %s %s %s %s %s %s %s %s"%(
str(acquisition_parameters["file_path"]),
str(acquisition_parameters["channel"]),
str(acquisition_parameters["cmode"]),
str(acquisition_parameters["bayer"]),
str(acquisition_parameters["y_quality"]),
str(acquisition_parameters["c_quality"]),
str(acquisition_parameters["portrait"]),
str(acquisition_parameters["gamma"]),
str(acquisition_parameters["black"]),
str(acquisition_parameters["colorsat_blue"]),
str(acquisition_parameters["colorsat_red"]),
str(acquisition_parameters["server_root"]),
str(acquisition_parameters["verbose"]))
gains_exp_changed = False
geometry_changed = False
#change gains/exposure if needed
if ((not acquisition_parameters["gain_r"] is None) or
(not acquisition_parameters["gain_gr"] is None) or
(not acquisition_parameters["gain_gb"] is None) or
(not acquisition_parameters["gain_b"] is None) or
(not acquisition_parameters["expos"] is None)):
gains_exp_changed = True
gstr = "set_sensor_gains_exposure %s %s %s %s %s %s %s"%(
str(acquisition_parameters["channel"]),
str(acquisition_parameters["gain_r"]),
str(acquisition_parameters["gain_gr"]),
str(acquisition_parameters["gain_gb"]),
str(acquisition_parameters["gain_b"]),
str(acquisition_parameters["expos"]),
str(acquisition_parameters["verbose"]))
communicate(PORT, gstr)
#change flips if needed
if ((not acquisition_parameters["flip_x"] is None) or
(not acquisition_parameters["flip_yr"] is None)):
geometry_changed = True
fstr = "set_sensor_flipXY %s %s %s %s"%(
str(acquisition_parameters["channel"]),
str(acquisition_parameters["flip_x"]),
str(acquisition_parameters["flip_y"]),
str(acquisition_parameters["verbose"]))
communicate(PORT, fstr)
#How many bad/non modified frames are to be skipped (just a guess)
skip_frames = 0
if geometry_changed:
skip_frames = 2
elif gains_exp_changed:
skip_frames = 1
if (str(acquisition_parameters["channel"])[0].upper() == 'A'):
channel_mask = 0x0f
else:
channel_mask = 1 << int(acquisition_parameters["channel"])
skip_str= "skip_frame %d"%(channel_mask)
for i in range(skip_frames):
communicate(PORT, skip_str)
# Now - get that image
reply = communicate(PORT,cmd_str)
if (acquisition_parameters["cmode"] =="5"):
path = path.replace("jpeg","jp4")
timestamp =str(time.time()).replace(".","_") # later use image timestamp
print("Content-Type: image/jpeg")
print("Content-Disposition: inline; filename=\"elphelimg_%s.jpeg\""%(timestamp))
print("Content-Length: %d\n"%(os.path.getsize(path))) # extra \n
with open(path, "r") as f:
shutil.copyfileobj(f, sys.stdout)
py393/test_mcntrl.py
View file @ 944ff196
......@@ -22,6 +22,7 @@
@contact: andrey@elphel.coml
@deffield updated: Updated
'''
from __future__ import print_function
from __builtin__ import str
__author__ = "Andrey Filippov"
__copyright__ = "Copyright 2015, Elphel, Inc."
......@@ -43,6 +44,10 @@ from argparse import ArgumentParser
#import argparse
from argparse import RawDescriptionHelpFormatter
import time
#import shutil
import socket
import select
from import_verilog_parameters import ImportVerilogParameters
#from import_verilog_parameters import VerilogParameters
from verilog_utils import hx
......@@ -217,6 +222,8 @@ USAGE
parser.add_argument("-x", "--exceptions", dest="exceptions", action="count", help="Exit on more exceptions [default: %(default)s]")
parser.add_argument("-l", "--localparams", dest="localparams", action="store", default="",
help="path were modified parameters are saved [default: %(default)s]", metavar="path")
parser.add_argument("-P", "--socket-port", dest="socket_port", action="store", default="",
help="port to use for socket connection [default: %(default)s]")
# Process arguments
args = parser.parse_args()
......@@ -391,18 +398,75 @@ USAGE
'''
#TODO: use readline
'''
if args.socket_port:
PORT = int(args.socket_port) # 8888
else:
PORT = 0
HOST = '' # Symbolic name meaning all available interfaces
socket_conn = None
if PORT:
socket_conn = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
try:
socket_conn.bind((HOST, PORT))
print ('Socket bind complete')
socket_conn.listen(1) # just a single request
print ('Socket now listening to a single request on port %d: send command, receive response, close'%(PORT))
except socket.error as msg:
print ('Bind failed. Error Code : %s Message %s'%( str(msg[0]),msg[1]))
socket_conn = None # do not use sockets
if (args.interactive):
line =""
while True:
line=raw_input('x393%s +%3.3fs--> '%(('','(simulated)')[args.simulated],(time.time()-tim))).strip()
soc_conn = None
prompt = 'x393%s +%3.3fs--> '%(('','(simulated)')[args.simulated],(time.time()-tim))
if socket_conn:
print(prompt , end="")
sys.stdout.flush()
ready_to_read, _, _ = select.select( #ready_to_write, in_error
[socket_conn, sys.stdin], # potential_readers,
[], # potential_writers,
[]) # potential_errs,
if sys.stdin in ready_to_read:
line=raw_input()
# print ("stdin: ", line)
elif socket_conn in ready_to_read:
try:
soc_conn, soc_addr = socket_conn.accept()
print ("Connected with %s"%(soc_addr[0] + ':' + str(soc_addr[1])))
#Sending message to connected client
#soc_conn.send('Welcome to the server. Type something and hit enter\n') #send only takes string
line = soc_conn.recv(4096) # or make it unlimited?
print ('Received from socket: ', line)
except:
continue # socket probably died, wait for the next command
else:
print ("Unexpected result from select: ready_to_read = ",ready_to_read)
continue
else: # No sockets, just command line input
line=raw_input(prompt)
# line=raw_input('x393%s +%3.3fs--> '%(('','(simulated)')[args.simulated],(time.time()-tim))).strip()
line=line.strip() # maybe also remove comment?
# Process command, return result to a socket if it was a socket, not stdin
tim=time.time()
#remove comment from the input line
if line.find("#") > 0:
had_comment=False
if line.find("#") >= 0:
line=line[:line.find("#")]
had_comment=True
lineList=line.split()
if not line:
if not had_comment:
print ('Use "quit" to exit, "help" - for help')
elif (line == 'quit') or (line == 'exit'):
if soc_conn:
soc_conn.send('0\n') # OK\n')
soc_conn.close()
# soc_conn=None
break
elif line== 'help' :
print ("\nAvailable tasks:")
......@@ -412,6 +476,8 @@ USAGE
print ('\n"parameters" and "defines" list known defined parameters and macros')
print ("args.exception=%d, QUIET=%d"%(args.exceptions,QUIET))
print ("Enter 'R' to toggle show/hide command results, now it is %s"%(("OFF","ON")[showResult]))
print ("Use 'socket_port [PORT]' to (re-)open socket on PORT (0 or no PORT - disable socket)")
# print ("Use 'copy <SRC> <DST> to copy files in file the system")
print ("Use 'pydev_predefines' to generate a parameter list to paste to vrlg.py, so Pydev will be happy")
elif lineList[0].upper() == 'R':
if len(lineList)>1:
......@@ -424,9 +490,27 @@ USAGE
else:
showResult = not showResult
print ("Show results mode is now %s"%(("OFF","ON")[showResult]))
# elif (len(line) > len("help")) and (line[:len("help")]=='help'):
elif (lineList[0].upper() == 'SOCKET_PORT') and (not soc_conn): # socket_conn):
if socket_conn : # close old socket (if open)
print ("Closed socket on port %d"%(PORT))
socket_conn.close()
socket_conn = None
if len(lineList) > 1: # port specified
PORT = int(lineList[1])
if PORT:
socket_conn = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
try:
socket_conn.bind((HOST, PORT))
print ('Socket bind complete')
socket_conn.listen(1) # just a single request
print ('Socket now listening to a single request on port %d: send command, receive response, close'%(PORT))
except socket.error as msg:
print ('Bind failed. Error Code : %s Message %s'%( str(msg[0]),msg[1]))
socket_conn = None # do not use sockets
continue
# elif lineList[0] == 'copy':
# shutil.copy2(lineList[1], lineList[2])
elif lineList[0] == 'help':
# helpFilter=line[len('help'):].strip()
helpFilter=lineList[1] # should not fail
try:
re.match(helpFilter,"")
......@@ -506,6 +590,10 @@ USAGE
vrlg_text=vrlg_text[:index+1]+"\n"+predefines
except:
print ("Failed to update %s - it is either missing or does not have a '%s'"%(vrlg_path,magic))
if soc_conn:
soc_conn.send('0\n')
soc_conn.close()
# soc_conn=None
continue
try:
with open (vrlg_path, "w") as vrlg_file:
......@@ -536,6 +624,16 @@ USAGE
rslt= execTask(cmdLine)
if showResult:
print (' Result: '+hx(rslt))
if soc_conn:
soc_conn.send(str(rslt)+'\n')
soc_conn.close()
# soc_conn=None
continue
if soc_conn:
soc_conn.send('0\n')
soc_conn.close()
# soc_conn=None
#http://stackoverflow.com/questions/11781265/python-using-getattr-to-call-function-with-variable-parameters
#*getattr(foo,bar)(*params)
return 0
......
py393/vrlg.py
View file @ 944ff196
This diff is collapsed.
py393/x393_axi_control_status.py
View file @ 944ff196
......@@ -173,6 +173,9 @@ class X393AxiControlStatus(object):
{FILE:"vccint", ITEM:"VCCint", UNITS:"V", SCALE: 0.001},
{FILE:"vccbram", ITEM:"VCCbram", UNITS:"V", SCALE: 0.001}]
print("hwmon:")
if self.DRY_MODE:
print ("Not defined for simulation mode")
return
for par in HWMON_ITEMS:
with open(HWMON_PATH + par[FILE]) as f:
d=int(f.read())
......
py393/x393_cmprs.py
View file @ 944ff196
......@@ -279,6 +279,8 @@ class X393Cmprs(object):
window_top,
byte32,
tile_width,
tile_vstep, # = 16
tile_height, #= 18
extra_pages,
disable_need):
"""
......@@ -294,13 +296,16 @@ class X393Cmprs(object):
@param window_top - 16-bit window top margin (in scan lines
@param byte32 - 32-byte columns
@param tile_width tile width,
@param tile_vstep tile vertical step in pixel rows (JPEG18/jp4 = 16)
@param tile_height tile height: 18 for color JPEG, 16 fore JP$ flavors,
@param extra_pages extra pages needed (1)
@param disable_need disable need (preference to sensor channels - they can not wait
"""
tile_vstep = 16
tile_height= 18
# tile_vstep = 16
# tile_height= 18
base_addr = vrlg.MCONTR_CMPRS_BASE + vrlg.MCONTR_CMPRS_INC * num_sensor;
mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = False,
disable_need = disable_need,
repetitive= True,
single = False,
......@@ -351,7 +356,7 @@ class X393Cmprs(object):
# run_mode = run_mode) #0 - reset, 2 - run single from memory, 3 - run repetitive
def setup_compressor_channel (self,
num_sensor,
chn,
qbank,
dc_sub,
cmode,
......@@ -366,7 +371,7 @@ class X393Cmprs(object):
coring,
verbose=0):
"""
@param num_sensor - sensor port number (0..3)
@param chn - compressor channel (0..3)
@param qbank - quantization table page (0..15)
@param dc_sub - True - subtract DC before running DCT, False - no subtraction, convert as is,
@param cmode - color mode:
......@@ -396,7 +401,7 @@ class X393Cmprs(object):
"""
if verbose > 0:
print("COMPRESSOR_SETUP")
print ( "num_sensor = ",num_sensor)
print ( "num_sensor = ",chn)
print ( "qbank = ",qbank)
print ( "dc_sub = ",dc_sub)
print ( "cmode = ",cmode)
......@@ -404,7 +409,7 @@ class X393Cmprs(object):
print ( "bayer = ",bayer)
print ( "focus_mode = ",focus_mode)
self.compressor_control(
chn = num_sensor, # sensor channel number (0..3)
chn = chn, # compressor channel number (0..3)
qbank = qbank, # [6:3] quantization table page
dc_sub = dc_sub, # [8:7] subtract DC
cmode = cmode, # [13:9] color mode:
......@@ -413,18 +418,18 @@ class X393Cmprs(object):
focus_mode = focus_mode) # [23:21] Set focus mode
self.compressor_format(
chn = num_sensor, # sensor channel number (0..3)
chn = chn, # compressor channel number (0..3)
num_macro_cols_m1 = num_macro_cols_m1, # number of macroblock colums minus 1
num_macro_rows_m1 = num_macro_rows_m1, # number of macroblock rows minus 1
left_margin = left_margin) # left margin of the first pixel (0..31) for 32-pixel wide colums in memory access
self.compressor_color_saturation(
chn = num_sensor, # sensor channel number (0..3)
chn = chn, # compressor channel number (0..3)
colorsat_blue = colorsat_blue, # color saturation for blue (10 bits) #'h90 for 100%
colorsat_red = colorsat_red) # color saturation for red (10 bits) # 'b6 for 100%
self.compressor_coring(
chn = num_sensor, # sensor channel number (0..3)
chn = chn, # compressor channel number (0..3)
coring = coring); # coring value
py393/x393_cmprs_afi.py
View file @ 944ff196
......@@ -110,6 +110,7 @@ class X393CmprsAfi(object):
@param channel - AFI input channel (0..3) - with 2 AFIs - 0..1 only
@return - memory segments (1 or two) with image data, timestamp in numeric and string format
"""
if verbose >0:
print ("\n------------ channel %d --------------"%(channel))
print ("x393_sens_cmprs.GLBL_WINDOW = ", x393_sens_cmprs.GLBL_WINDOW)
if (self.DRY_MODE):
......@@ -123,14 +124,37 @@ class X393CmprsAfi(object):
# offs_len32 = 0x20 - CCAM_MMAP_META_LENGTH # 0x1c #from last image 32-byte chunk to lower of 3-byte image length (MSB == 0xff)
next_image = self.afi_mux_get_image_pointer(port_afi = port_afi,
channel = channel)
# Bug - got 0x20 more than start of the new image
last_image_chunk = next_image - 0x40
if last_image_chunk < 0:
last_image_chunk += circbuf_len
len32 = self.x393_mem.read_mem(cirbuf_start + last_image_chunk + (0x20 - CCAM_MMAP_META_LENGTH))
markerFF = len32 >> 24
if (markerFF != 0xff):
print ("Failed to get 0xff marker at offset 0x%08x - length word = 0x%08x, next_image = 0x%08x)"%
(cirbuf_start + last_image_chunk + (0x20 - CCAM_MMAP_META_LENGTH) + 3,len32,next_image))
if verbose >0:
for a in range ( next_image - (0x10 * num_lines_print), next_image + (0x10 * num_lines_print), 4):
d = self.x393_mem.read_mem(cirbuf_start + a)
if (a % 16) == 0:
print ("\n%08x: "%(a),end ="" )
print("%02x %02x %02x %02x "%(d & 0xff, (d >> 8) & 0xff, (d >> 16) & 0xff, (d >> 24) & 0xff), end = "")
#Try noticed (but not yet identified) bug - reduce afi_mux_get_image_pointer result by 1
next_image -= 0x20
if next_image < 0:
next_image += circbuf_len
last_image_chunk = next_image - 0x40
if last_image_chunk < 0:
last_image_chunk += circbuf_len
len32 = self.x393_mem.read_mem(cirbuf_start + last_image_chunk + (0x20 - CCAM_MMAP_META_LENGTH))
markerFF = len32 >> 24
if (markerFF != 0xff):
print ("Failed to get 0xff marker at offset 0x%08x - length word = 0x%08x)"%(cirbuf_start + last_image_chunk + (0x20 - CCAM_MMAP_META_LENGTH) + 3,len32))
print ("**** Failed to get 0xff marker at CORRECTED offset 0x%08x - length word = 0x%08x, next_image = 0x%08x)"%
(cirbuf_start + last_image_chunk + (0x20 - CCAM_MMAP_META_LENGTH) + 3,len32,next_image))
return None
if verbose >0:
print ("\n-----------reduced next frame byte pointer by 0x20 -------------")
len32 &= 0xffffff
# inserted_bytes = (32 - (((len32 % 32) + CCAM_MMAP_META) % 32)) % 32
#adjusting to actual...
......@@ -174,10 +198,10 @@ class X393CmprsAfi(object):
"segments":segments}
if verbose >0 :
print ("Inserted bytes after image before meta = 0x%x"%(inserted_bytes))
print ("Image start (relative to cirbuf) = 0x%x"%(img_start))
print ("Image start (relative to cirbuf) = 0x%x, image length = 0x%x"%(img_start, len32 ))
print ("Image time stamp = %s (%f)"%(tstr, fsec))
for s in segments:
print ("start_address = 0x%x, length = 0x%x"%(s[0],s[1]))
for i,s in enumerate(segments):
print ("segment %d: start_address = 0x%x, length = 0x%x"%(i, s[0],s[1]))
return result
......
py393/x393_jpeg.py
View file @ 944ff196
This diff is collapsed.
py393/x393_mcntrl.py
View file @ 944ff196
......@@ -40,7 +40,8 @@ __status__ = "Development"
#import time
import vrlg
def func_encode_mode_scan_tiled (disable_need = False,
def func_encode_mode_scan_tiled (skip_too_late = False,
disable_need = False,
repetitive= True,
single = False,
reset_frame = False,
......@@ -52,6 +53,7 @@ def func_encode_mode_scan_tiled (disable_need = False,
chn_reset = False):
"""
Combines arguments to create a 12-bit encoded data for scanline mode memory R/W
@param skip_too_late - Skip over missed blocks to preserve frame structure (increment pointers),
@param disable_need - disable 'need' generation, only 'want' (compressor channels),
@param repetitive - run repetitive frames (add this to older 'master' tests)
@param single - run single frame
......@@ -77,6 +79,7 @@ def func_encode_mode_scan_tiled (disable_need = False,
rslt |= (0,1)[single] << vrlg.MCONTR_LINTILE_SINGLE
rslt |= (0,1)[repetitive] << vrlg.MCONTR_LINTILE_REPEAT
rslt |= (0,1)[disable_need] << vrlg.MCONTR_LINTILE_DIS_NEED
rslt |= (0,1)[skip_too_late] << vrlg.MCONTR_LINTILE_SKIP_LATE
return rslt
'''
......
py393/x393_mcntrl_membridge.py
View file @ 944ff196
......@@ -308,6 +308,7 @@ class X393McntrlMembridge(object):
0) # chn_reset
'''
mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = False,
disable_need = False,
repetitive= True,
single = False,
......
py393/x393_mcntrl_tests.py
View file @ 944ff196
......@@ -290,6 +290,7 @@ class X393McntrlTests(object):
0) # chn_reset
'''
mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = False,
disable_need = False,
repetitive= True,
single = False,
......@@ -442,6 +443,7 @@ class X393McntrlTests(object):
0) # chn_reset
'''
mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = False,
disable_need = False,
repetitive= True,
single = False,
......@@ -556,6 +558,7 @@ class X393McntrlTests(object):
0) # chn_reset
'''
mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = False,
disable_need = False,
repetitive= True,
single = False,
......@@ -698,6 +701,7 @@ class X393McntrlTests(object):
0) # chn_reset
'''
mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = False,
disable_need = False,
repetitive= True,
single = False,
......
py393/x393_mcntrl_timing.py
View file @ 944ff196
......@@ -64,7 +64,8 @@ class X393McntrlTiming(object):
fSDCLK=fVCO/CLKOUT1_DIVIDE
tSDCLK=1000.0/fSDCLK # in ns
phaseStep=1000.0/(fVCO*56.0) # 1 unit of phase shift (now 112 for the full period
fREF=fCLK_IN*vrlg.CLKFBOUT_MULT_REF/vrlg.CLKFBOUT_DIV_REF
# fREF=fCLK_IN*vrlg.CLKFBOUT_MULT_REF/vrlg.CLKFBOUT_DIV_REF
fREF=fCLK_IN*vrlg.MULTICLK_MULT/vrlg.MULTICLK_DIV_DLYREF/vrlg.MULTICLK_DIVCLK
dlyStep=1000.0/fREF/32/2 # Approximate, depending on calibration
dlyFStep=0.01 # fine step
return{"SDCLK_PERIOD":tSDCLK,
......
py393/x393_sens_cmprs.py
View file @ 944ff196
This diff is collapsed.
py393/x393_sensor.py
View file @ 944ff196
This diff is collapsed.
py393/x393_utils.py
View file @ 944ff196
......@@ -38,7 +38,7 @@ from x393_mem import X393Mem
from time import sleep
import vrlg # global parameters
import x393_axi_control_status
import shutil
DEFAULT_BITFILE="/usr/local/verilog/x393.bit"
FPGA_RST_CTRL= 0xf8000240
FPGA0_THR_CTRL=0xf8000178
......@@ -96,6 +96,10 @@ class X393Utils(object):
"""
if bitfile is None:
bitfile=DEFAULT_BITFILE
print ("Sensor ports power off")
POWER393_PATH = '/sys/devices/elphel393-pwr.1'
with open (POWER393_PATH + "/channels_dis","w") as f:
print("vcc_sens01 vp33sens01 vcc_sens23 vp33sens23", file = f)
print ("FPGA clock OFF")
self.x393_mem.write_mem(FPGA0_THR_CTRL,1)
print ("Reset ON")
......@@ -286,4 +290,13 @@ class X393Utils(object):
print ("Failed to write to %s"%(os.path.abspath(fileName)))
else:
print(txt)
def copy (self,
src,
dst):
"""
Copy files in the file system
@param src - source path
@param dst - destination path/directory
"""
shutil.copy2(src, dst)
sensor/sens_10398.v
View file @ 944ff196
......@@ -41,7 +41,7 @@ module sens_10398 #(
parameter SENSIO_JTAG = 'h2,
// parameter SENSIO_WIDTH = 'h3, // set line width (1.. 2^16) if 0 - use HACT
parameter SENSIO_DELAYS = 'h4, // 'h4..'h7 - each address sets 4 delays through 4 bytes of 32-bit data
// 6 - delays, 7 - phase
// 5, swap lanes 6 - delays, 7 - phase
parameter SENSIO_STATUS_REG = 'h21,
parameter SENS_JTAG_PGMEN = 8,
......@@ -91,6 +91,10 @@ module sens_10398 #(
parameter HISPI_NUMLANES = 4,
parameter HISPI_DELAY_CLK = "FALSE",
parameter HISPI_MMCM = "TRUE",
parameter HISPI_KEEP_IRST = 5, // number of cycles to keep irst on after release of prst (small number - use 1 hot)
parameter HISPI_WAIT_ALL_LANES = 4'h8, // number of output pixel cycles to wait after the earliest lane
parameter HISPI_FIFO_DEPTH = 4,
parameter HISPI_FIFO_START = 7,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
......@@ -157,7 +161,8 @@ module sens_10398 #(
reg [31:0] data_r;
// reg [3:0] set_idelay;
reg set_lanes_map; // set sequence of lanes im the composite pixel line
reg set_fifo_dly; // set how long to wait after strating to fill FIFOs (in items) ~= 1/2 2^FIFO_DEPTH
reg set_idelays;
reg set_iclk_phase;
reg set_ctrl_r;
......@@ -213,6 +218,12 @@ module sens_10398 #(
if (mrst) data_r <= 0;
else if (cmd_we) data_r <= cmd_data;
if (mrst) set_fifo_dly <= 0;
else set_fifo_dly <= cmd_we & (cmd_a==(SENSIO_DELAYS+0)); // TODO - add Symbolic names
if (mrst) set_lanes_map <= 0;
else set_lanes_map <= cmd_we & (cmd_a==(SENSIO_DELAYS+1));
if (mrst) set_idelays <= 0;
else set_idelays <= cmd_we & (cmd_a==(SENSIO_DELAYS+2));
......@@ -271,7 +282,7 @@ module sens_10398 #(
// generate (slow) clock for the sensor - it will be multiplied by the sensor VCO
always @(posedge pclk) begin
if (prst || (pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] == 0)) pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] <= (PXD_CLK_DIV / 2);
if (prst || (pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] == 0)) pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] <= (PXD_CLK_DIV / 2) -1;
else pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] <= pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] - 1;
// treat MSB separately to make 50% duty cycle
if (prst) pxd_clk_cntr[PXD_CLK_DIV_BITS-1] <= 0;
......@@ -342,6 +353,10 @@ module sens_10398 #(
.HISPI_NUMLANES (HISPI_NUMLANES),
.HISPI_DELAY_CLK (HISPI_DELAY_CLK),
.HISPI_MMCM (HISPI_MMCM),
.HISPI_KEEP_IRST (HISPI_KEEP_IRST),
.HISPI_WAIT_ALL_LANES (HISPI_WAIT_ALL_LANES),
.HISPI_FIFO_DEPTH (HISPI_FIFO_DEPTH),
.HISPI_FIFO_START (HISPI_FIFO_START),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
......@@ -349,6 +364,7 @@ module sens_10398 #(
.HISPI_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
.HISPI_IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.HISPI_IOSTANDARD (HISPI_IOSTANDARD)
) sens_hispi12l4_i (
.pclk (pclk), // input
.prst (prsts), //prst), // input
......@@ -363,6 +379,8 @@ module sens_10398 #(
.mclk (mclk), // input
.mrst (mrst), // input
.dly_data (data_r), // input[31:0]
.set_lanes_map (set_lanes_map), // input
.set_fifo_dly (set_fifo_dly), // input
.set_idelay ({4{set_idelays}}), // input[3:0]
.ld_idelay (ld_idelay), // input
.set_clk_phase (set_iclk_phase), // input
......
sensor/sens_hispi12l4.v
View file @ 944ff196
......@@ -57,18 +57,22 @@ module sens_hispi12l4#(
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
parameter DEFAULT_LANE_MAP = 8'b11100100, // one-to-one map (or make it 8'b00111001 ?)
parameter HISPI_MSB_FIRST = 0,
parameter HISPI_NUMLANES = 4,
parameter HISPI_DELAY_CLK = "FALSE",
parameter HISPI_MMCM = "TRUE",
parameter HISPI_KEEP_IRST = 5, // number of cycles to keep irst on after release of prst (small number - use 1 hot)
parameter HISPI_WAIT_ALL_LANES = 4'h8, // number of output pixel cycles to wait after the earliest lane
parameter HISPI_FIFO_DEPTH = 4,
parameter HISPI_FIFO_START = 7,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA),
parameter HISPI_KEEP_IRST = 5 // number of cycles to keep irst on after release of prst (small number - use 1 hot)
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I" //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA),
)(
input pclk, // global clock input, pixel rate (220MHz for MT9F002)
input prst, // reset @pclk (add sensor reset here)
......@@ -89,6 +93,8 @@ module sens_hispi12l4#(
input mclk,
input mrst,
input [HISPI_NUMLANES * 8-1:0] dly_data, // delay value (3 LSB - fine delay) - @posedge mclk
input set_lanes_map, // set number of physical lane for each logical one
input set_fifo_dly,
input [HISPI_NUMLANES-1:0] set_idelay, // mclk synchronous load idelay value
input ld_idelay, // mclk synchronous set idealy value
input set_clk_phase, // mclk synchronous set idealy value
......@@ -106,10 +112,33 @@ module sens_hispi12l4#(
wire ipclk; // re-generated half HiSPi clock (165 MHz)
wire ipclk2x;// re-generated HiSPi clock (330 MHz)
wire [HISPI_NUMLANES * 4-1:0] sns_d;
localparam WAIT_ALL_LANES = 4'h8; // number of output pixel cycles to wait after the earliest lane
localparam FIFO_DEPTH = 4;
// localparam WAIT_ALL_LANES = 4'h8; // number of output pixel cycles to wait after the earliest lane
// localparam FIFO_DEPTH = 4;
reg [HISPI_KEEP_IRST-1:0] irst_r;
wire irst = irst_r[0];
reg [HISPI_NUMLANES * 2-1:0] lanes_map;
reg [HISPI_NUMLANES * 4-1:0] logical_lanes4;
reg [HISPI_FIFO_DEPTH-1:0] fifo_out_dly_mclk;
reg [HISPI_FIFO_DEPTH-1:0] fifo_out_dly;
always @ (posedge mclk) begin
if (mrst) lanes_map <= DEFAULT_LANE_MAP; //{2'h3,2'h2,2'h1,2'h0}; // 1-to-1 default map
else if (set_lanes_map) lanes_map <= dly_data[HISPI_NUMLANES * 2-1:0];
if (mrst) fifo_out_dly_mclk <= HISPI_FIFO_START;
else if (set_fifo_dly) fifo_out_dly_mclk <= dly_data[HISPI_FIFO_DEPTH-1:0];
end
//non-parametrized lane switch (4x4)
always @(posedge ipclk) begin
logical_lanes4[ 3: 0] <= sns_d[{lanes_map[1:0],2'b0} +:4];
logical_lanes4[ 7: 4] <= sns_d[{lanes_map[3:2],2'b0} +:4];
logical_lanes4[11: 8] <= sns_d[{lanes_map[5:4],2'b0} +:4];
logical_lanes4[15:12] <= sns_d[{lanes_map[7:6],2'b0} +:4];
end
always @(posedge ipclk) begin
fifo_out_dly <= fifo_out_dly_mclk;
end
sens_hispi_clock #(
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
......@@ -182,8 +211,13 @@ module sens_hispi12l4#(
.ipclk (ipclk), // input
.ipclk2x (ipclk2x), // input
.irst (irst), // input
//`ifdef REVERSE_LANES
// .din_p ({sns_dp[0],sns_dp[1],sns_dp[2],sns_dp[3]}), // input[3:0]
// .din_n ({sns_dn[0],sns_dn[1],sns_dn[2],sns_dn[3]}), // input[3:0]
//`else
.din_p (sns_dp), // input[3:0]
.din_n (sns_dn), // input[3:0]
//`endif
.dout (sns_d) // output[15:0]
);
......@@ -209,6 +243,7 @@ module sens_hispi12l4#(
reg sof_pclk;
// wire [HISPI_NUMLANES-1:0] sol_pclk = rd_run & ~rd_run_d;
wire sol_pclk = |(rd_run & ~rd_run_d); // possibly multi-cycle
reg start_fifo_re; // start reading FIFO - single-cycle
reg [HISPI_NUMLANES-1:0] good_lanes; // lanes that started active line OK
reg [HISPI_NUMLANES-1:0] fifo_re;
reg [HISPI_NUMLANES-1:0] fifo_re_r;
......@@ -225,6 +260,7 @@ module sens_hispi12l4#(
assign hact_out = hact_r;
assign sof = sof_pclk;
......@@ -251,6 +287,8 @@ module sens_hispi12l4#(
rd_run_d <= rd_run;
start_fifo_re <= sol_pclk && !rd_line; // sol_pclk may be multi-cycle
sof_pclk <= vact_pclk_strt[0] && ! vact_pclk_strt[1];
if (prst || sof_pclk) rd_line <= 0;
......@@ -271,7 +309,8 @@ module sens_hispi12l4#(
({12 {fifo_re_r[3] & rd_run[3]}} & fifo_out[3 * 12 +:12]); */
if (prst) fifo_re <= 0;
else if (sol_pclk || (rd_line && fifo_re[HISPI_NUMLANES - 1])) fifo_re <= 1;
// else if (sol_pclk || (rd_line && fifo_re[HISPI_NUMLANES - 1])) fifo_re <= 1;
else if (start_fifo_re || (rd_line && fifo_re[HISPI_NUMLANES - 1])) fifo_re <= 1;
else fifo_re <= fifo_re << 1;
// if (prst || (hact_off && (|(good_lanes & ~rd_run)))) hact_r <= 0;
......@@ -288,7 +327,7 @@ module sens_hispi12l4#(
) dly_16_start_line_i (
.clk (pclk), // input
.rst (1'b0), // input
.dly (WAIT_ALL_LANES), // input[3:0]
.dly (HISPI_WAIT_ALL_LANES), // input[3:0]
.din (rd_line && !rd_line_r), // input[0:0]
.dout (sol_all_dly) // output[0:0]
);
......@@ -339,7 +378,7 @@ module sens_hispi12l4#(
) sens_hispi_lane_i (
.ipclk (ipclk), // input
.irst (irst), // input
.din (sns_d[4*i +: 4]), // input[3:0]
.din (logical_lanes4[4*i +: 4]), // input[3:0]
.dout (hispi_aligned[12*i +: 12]), // output[3:0] reg
.dv (hispi_dv[i]), // output reg
.embed (hispi_embed[i]), // output reg
......@@ -349,9 +388,9 @@ module sens_hispi12l4#(
.eol (hispi_eol[i]) // output reg
);
sens_hispi_fifo #(
.COUNT_START (7),
// .COUNT_START (HISPI_FIFO_START),
.DATA_WIDTH (12),
.DATA_DEPTH (FIFO_DEPTH)
.DATA_DEPTH (HISPI_FIFO_DEPTH)
) sens_hispi_fifo_i (
.ipclk (ipclk), // input
.irst (irst), // input
......@@ -359,6 +398,7 @@ module sens_hispi12l4#(
.sol (hispi_sol[i] && !(hispi_embed[i] && ignore_embedded_ipclk)), // input
.eol (hispi_eol[i]), // input
.din (hispi_aligned[12*i +: 12]), // input[11:0]
.out_dly (fifo_out_dly), // input[3:0]
.pclk (pclk), // input
.prst (prst), // input
.re (fifo_re[i]), // input
......
sensor/sens_hispi_fifo.v
View file @ 944ff196
......@@ -34,7 +34,7 @@
`timescale 1ns/1ps
module sens_hispi_fifo#(
parameter COUNT_START = 7, // wait these many samples input before starting output
// parameter COUNT_START = 7, // wait these many samples input before starting output
parameter DATA_WIDTH = 12,
parameter DATA_DEPTH = 4 // >=3
) (
......@@ -44,6 +44,7 @@ module sens_hispi_fifo#(
input sol, // start of line - 1 cycle before dv
input eol, // end of line - last dv
input [DATA_WIDTH-1:0] din,
input [DATA_DEPTH-1:0] out_dly, // wait these many samples input before starting output
input pclk,
input prst,
input re,
......@@ -55,8 +56,11 @@ module sens_hispi_fifo#(
reg [DATA_DEPTH:0] ra;
wire line_start_pclk;
reg line_run_ipclk;
reg line_run_ipclk_d; // to generate start for very short lines (may just use small out_dly value)
reg line_run_pclk;
reg run_r;
reg start_sent;
reg start_out_ipclk;
assign run = run_r;
// TODO: generate early done by comparing ra with (wa-1) - separate counter
......@@ -69,6 +73,15 @@ module sens_hispi_fifo#(
if (irst || eol) line_run_ipclk <= 0;
else if (sol) line_run_ipclk <= 1;
if (!line_run_ipclk) start_sent <= 0;
else if (start_out_ipclk) start_sent <= 1;
line_run_ipclk_d <= line_run_ipclk;
if (irst) start_out_ipclk <= 0;
else start_out_ipclk <= line_run_ipclk? (!start_sent && we && (wa[DATA_DEPTH-1:0] == out_dly)) : (line_run_ipclk_d && !start_sent);
end
always @(posedge pclk) begin
......@@ -91,7 +104,8 @@ module sens_hispi_fifo#(
.rst (irst), // input
.src_clk (ipclk), // input
.dst_clk (pclk), // input
.in_pulse (we && (wa == COUNT_START)), // input
// .in_pulse (we && (wa == COUNT_START)), // input
.in_pulse (start_out_ipclk), // input
.out_pulse (line_start_pclk), // output
.busy() // output
);
......
sensor/sensor_channel.v
View file @ 944ff196
......@@ -257,6 +257,10 @@ module sensor_channel#(
parameter HISPI_NUMLANES = 4,
parameter HISPI_DELAY_CLK = "FALSE",
parameter HISPI_MMCM = "TRUE",
parameter HISPI_KEEP_IRST = 5, // number of cycles to keep irst on after release of prst (small number - use 1 hot)
parameter HISPI_WAIT_ALL_LANES = 4'h8, // number of output pixel cycles to wait after the earliest lane
parameter HISPI_FIFO_DEPTH = 4,
parameter HISPI_FIFO_START = 7,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_DQS_BIAS = "TRUE",
......@@ -462,13 +466,30 @@ module sensor_channel#(
`ifdef DEBUG_RING
reg vact_to_fifo_r;
// reg vact_to_fifo_r;
reg hact_to_fifo_r;
reg [15:0] debug_line_cntr;
reg [15:0] debug_lines;
reg [15:0] hact_cntr;
reg [15:0] vact_cntr;
`ifdef HISPI
always @(posedge pclk) begin
// vact_to_fifo_r <= vact_to_fifo;
hact_to_fifo_r <= hact;
if (sof) debug_line_cntr <= 0;
else if (hact && !hact_to_fifo_r) debug_line_cntr <= debug_line_cntr + 1;
if (sof) debug_lines <= debug_line_cntr;
if (prst) hact_cntr <= 0;
else if (hact && !hact_to_fifo_r) hact_cntr <= hact_cntr + 1;
if (prst) vact_cntr <= 0;
else if (sof) vact_cntr <= vact_cntr + 1;
end
`else
always @(posedge ipclk) begin
vact_to_fifo_r <= vact_to_fifo;
hact_to_fifo_r <= hact_to_fifo;
......@@ -485,6 +506,7 @@ module sensor_channel#(
else if (vact_to_fifo && !vact_to_fifo_r) vact_cntr <= vact_cntr + 1;
end
`endif
debug_slave #(
.SHIFT_WIDTH (128),
.READ_WIDTH (128),
......@@ -501,7 +523,12 @@ module sensor_channel#(
// .rd_data ({6'b0,hist_grant,hist_request, hist_gr[3:0], hist_rq[3:0], hact_cntr[15:0], debug_lines[15:0], debug_line_cntr[15:0]}), // input[31:0]
.rd_data ({
lens_pxd_in, gamma_pxd_in[15:0],
pxd_to_fifo[11:0],pxd[11:0],gamma_pxd_out[7:0],
`ifdef HISPI
12'b0,
`else
pxd_to_fifo[11:0],
`endif
pxd[11:0],gamma_pxd_out[7:0],
6'b0,hist_grant,hist_request, hist_gr[3:0], hist_rq[3:0], hact_cntr[15:0],
debug_lines[15:0], debug_line_cntr[15:0]}), // input[31:0]
......@@ -755,6 +782,10 @@ module sensor_channel#(
.HISPI_NUMLANES (HISPI_NUMLANES),
.HISPI_DELAY_CLK (HISPI_DELAY_CLK),
.HISPI_MMCM (HISPI_MMCM),
.HISPI_KEEP_IRST (HISPI_KEEP_IRST),
.HISPI_WAIT_ALL_LANES (HISPI_WAIT_ALL_LANES),
.HISPI_FIFO_DEPTH (HISPI_FIFO_DEPTH),
.HISPI_FIFO_START (HISPI_FIFO_START),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
......
sensor/sensors393.v
View file @ 944ff196
......@@ -289,6 +289,10 @@ module sensors393 #(
parameter HISPI_MMCM1 = "TRUE",
parameter HISPI_MMCM2 = "TRUE",
parameter HISPI_MMCM3 = "TRUE",
parameter HISPI_KEEP_IRST = 5, // number of cycles to keep irst on after release of prst (small number - use 1 hot)
parameter HISPI_WAIT_ALL_LANES = 4'h8, // number of output pixel cycles to wait after the earliest lane
parameter HISPI_FIFO_DEPTH = 4,
parameter HISPI_FIFO_START = 7,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_DQS_BIAS = "TRUE",
......@@ -610,7 +614,10 @@ module sensors393 #(
.HISPI_DELAY_CLK ((i & 2) ? ((i & 1) ? HISPI_DELAY_CLK3 : HISPI_DELAY_CLK2) : ((i & 1) ?HISPI_DELAY_CLK1 : HISPI_DELAY_CLK0 )),
.HISPI_MMCM ((i & 2) ? ((i & 1) ? HISPI_MMCM3 : HISPI_MMCM2) : ((i & 1) ?HISPI_MMCM1 : HISPI_MMCM0 )),
.HISPI_KEEP_IRST (HISPI_KEEP_IRST),
.HISPI_WAIT_ALL_LANES (HISPI_WAIT_ALL_LANES),
.HISPI_FIFO_DEPTH (HISPI_FIFO_DEPTH),
.HISPI_FIFO_START (HISPI_FIFO_START),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
......
status_read.v
View file @ 944ff196
......@@ -95,6 +95,9 @@ module status_read#(
assign axird_selected = select_r;
initial begin
ram [DATA_2DEPTH] = FPGA_VERSION;
`ifdef HISPI
ram [DATA_2DEPTH-1] = 1; //0 - parallel sensor, 1 - HiSPi sensor
`endif
end
always @ (posedge axi_clk) begin
if (arst) select_r <= 0;
......
system_defines.vh
View file @ 944ff196
......@@ -41,7 +41,8 @@
// `define USE_OLD_XDCT393
// `define USE_PCLK2X
// `define USE_XCLK2X
// `define DEBUG_RING 1
`define REVERSE_LANES 1
`define DEBUG_RING 1
// `define MCLK_VCO_MULT 16
// DDR3 memory speed grade and density
`define sg25 1
......
util_modules/debug_master.v
View file @ 944ff196
......@@ -67,6 +67,7 @@ module debug_master #(
reg ld_r;
reg cmd; //command stae (0 - idle)
reg [DEBUG_CMD_LATENCY : 0] cmd_reg;
wire [3:0] debug_latency_plus1 = DEBUG_CMD_LATENCY+1;
wire set_status_w = cmd_we && (cmd_a == DEBUG_SET_STATUS);
wire shift32_w = cmd_we && (cmd_a == DEBUG_SHIFT_DATA);
......@@ -104,7 +105,7 @@ module debug_master #(
) dly_16_i (
.clk (mclk), // input
.rst (1'b0), // input
.dly (DEBUG_CMD_LATENCY+1), // input[3:0]
.dly (debug_latency_plus1), // DEBUG_CMD_LATENCY+1), // input[3:0]
.din (&cntr), // input[0:0]
.dout (shift_done) // output[0:0]
);
......
util_modules/resync_data.v 0 → 100644
View file @ 944ff196
/*******************************************************************************
* Module: resync_data
* Date:2015-12-22
* Author: Andrey Filippov
* Description: Resynchronize data between clock domains. No over/underruns
* are checker, start with half FIFO full. Async reset sets
* specifies output values regardless of the clocks
*
* Copyright (c) 2014 Elphel, Inc.
* resync_data.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* resync_data.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module resync_data
#(
parameter integer DATA_WIDTH=16,
parameter integer DATA_DEPTH=4, // >= 2
parameter INITIAL_VALUE = 0
) (
input arst, // async reset, active high (global)
input srst, // same as arst, but relies on the clocks
input wclk, // write clock - positive edge
input rclk, // read clock - positive edge
input we, // write enable
input re, // read enable
input [DATA_WIDTH-1:0] data_in, // input data
output reg [DATA_WIDTH-1:0] data_out, // output data
output reg valid // data valid @ rclk
);
localparam integer DATA_2DEPTH=(1<<DATA_DEPTH)-1;
reg [DATA_WIDTH-1:0] ram [0:DATA_2DEPTH];
reg [DATA_DEPTH-1:0] raddr;
reg [DATA_DEPTH-1:0] waddr;
reg [1:0] rrst = 3;
always @ (posedge rclk or posedge arst) begin
if (arst) valid <= 0;
else if (srst) valid <= 0;
else if (&waddr[DATA_DEPTH-2:0] && we) valid <= 1; // just once set and stays until reset
end
always @ (posedge wclk or posedge arst) begin
if (arst) waddr <= 0;
else if (srst) waddr <= 0;
else if (we) waddr <= waddr + 1;
end
always @ (posedge rclk or posedge arst) begin
if (arst) rrst <= 3;
else if (srst) rrst <= 3; // resync to rclk
else rrst <= rrst << 1;
if (arst) raddr <= 0;
else if (rrst[0]) raddr <= 0;
else if (re || rrst[1]) raddr <= raddr + 1;
if (arst) data_out <= INITIAL_VALUE;
else if (rrst[0]) data_out <= INITIAL_VALUE;
else if (re || rrst[1]) data_out <= ram[raddr];
end
always @ (posedge wclk) begin
if (we) ram[waddr] <= data_in;
end
endmodule
x393.v
View file @ 944ff196
......@@ -1647,7 +1647,10 @@ assign axi_grst = axi_rst_pre;
.HISPI_MMCM1 (HISPI_MMCM1),
.HISPI_MMCM2 (HISPI_MMCM2),
.HISPI_MMCM3 (HISPI_MMCM3),
.HISPI_KEEP_IRST (HISPI_KEEP_IRST),
.HISPI_WAIT_ALL_LANES (HISPI_WAIT_ALL_LANES),
.HISPI_FIFO_DEPTH (HISPI_FIFO_DEPTH),
.HISPI_FIFO_START (HISPI_FIFO_START),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
......
x393_testbench03.sav
View file @ 944ff196
This diff is collapsed.
x393_testbench03.tf
View file @ 944ff196
This diff is collapsed.
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