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x393
Commit 8f05c2c2 authored by Andrey Filippov's avatar Andrey Filippov
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adding rigger out from the sensors running i free mode

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cocotb/x393_cocotb_lwir_04.sav
View file @ 8f05c2c2
[*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Fri May 3 04:06:38 2019
[*] Fri May 3 15:28:46 2019
[*]
[dumpfile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/simulation/x393_dut-20190502213839545.fst"
[dumpfile_mtime] "Fri May 3 04:06:09 2019"
......@@ -3061,16 +3061,44 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepto
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.start_spi_seq_mclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.start_spi_seq_pclk
@29
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.spi_timeout_cntr[1:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.spi_seq
@200
-
@1000200
-reset_seq
@800200
-sens_channel0
-timestamping
@22
x393_dut.x393_i.timing393_i.frame_sync[3:0]
@28
x393_dut.x393_i.timing393_i.frsync_chn0
x393_dut.x393_i.timing393_i.frsync_chn1
x393_dut.x393_i.timing393_i.frsync_chn2
x393_dut.x393_i.timing393_i.frsync_chn3
@22
x393_dut.x393_i.timing393_i.trig[3:0]
@28
x393_dut.x393_i.timing393_i.trig_chn0
x393_dut.x393_i.timing393_i.trig_chn1
x393_dut.x393_i.timing393_i.trig_chn2
x393_dut.x393_i.timing393_i.trig_chn3
x393_dut.x393_i.timing393_i.triggered_mode
@22
x393_dut.x393_i.timing393_i.ts_data_chn0[7:0]
x393_dut.x393_i.timing393_i.ts_data_chn1[7:0]
x393_dut.x393_i.timing393_i.ts_data_chn2[7:0]
x393_dut.x393_i.timing393_i.ts_data_chn3[7:0]
x393_dut.x393_i.timing393_i.ts_stb[3:0]
@28
x393_dut.x393_i.timing393_i.ts_stb_chn0
x393_dut.x393_i.timing393_i.ts_stb_chn1
x393_dut.x393_i.timing393_i.ts_stb_chn2
x393_dut.x393_i.timing393_i.ts_stb_chn3
@201
-
@1000200
-timestamping
@800200
-lepto3_0
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.prst
......
fpga_version.vh
View file @ 8f05c2c2
......@@ -35,7 +35,8 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h03930136; // Fiixing spi_seq
parameter FPGA_VERSION = 32'h03930137; // longer reset, sync output
// parameter FPGA_VERSION = 32'h03930136; // Fiixing spi_seq
// parameter FPGA_VERSION = 32'h03930135; // Adding multi-cam reset
// parameter FPGA_VERSION = 32'h0393014; // Adding multi-cam reset - buggy
// parameter FPGA_VERSION = 32'h03930133; // Works with linux kernel rocko commit of 05/01/2019 bd61276e05f7343415929112ae368230a9c472f0
......
includes/x393_parameters.vh
View file @ 8f05c2c2
......@@ -594,7 +594,7 @@
parameter VOSPI_MRST_AFTER_MS = 5, // Wait after master reset and generate SOF pulse to advance sequencer
parameter VOSPI_SPI_TIMEOUT_MS = 3, // Wait to tymeout SPI when needed to re-sync
`else
parameter VOSPI_MRST_MS = 5, // master reset duration in ms
parameter VOSPI_MRST_MS = 200, // master reset duration in ms (so even all channels would overlap)
parameter VOSPI_MRST_AFTER_MS = 2000, // Wait after master reset and generate SOF pulse to advance sequencer
parameter VOSPI_SPI_TIMEOUT_MS = 185, // Wait to tymeout SPI when needed to re-sync
`endif
......
sensor/sens_lepton3.v
View file @ 8f05c2c2
......@@ -89,7 +89,7 @@ module sens_lepton3 #(
parameter VOSPI_SOF_TO_HACT = 100, // 10, // clock cycles from SOF to HACT (limited to 8 bits)
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
parameter VOSPI_MRST_MS = 5, // master reset duration in ms
parameter VOSPI_MRST_MS = 200, // master reset duration in ms (so even all channels would overlap)
parameter VOSPI_MRST_AFTER_MS = 2000, // Wait after master reset and generate SOF pulse to advance sequencer
parameter VOSPI_SPI_TIMEOUT_MS = 185 // Wait to tymeout SPI when needed to re-sync
)(
......
sensor/sensor_channel.v
View file @ 8f05c2c2
......@@ -276,7 +276,7 @@ module sensor_channel#(
parameter VOSPI_SOF_TO_HACT = 100, // 10, // clock cycles from SOF to HACT (limited to 8 bits)
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
parameter VOSPI_MRST_MS = 5, // master reset duration in ms
parameter VOSPI_MRST_MS = 200, // master reset duration in ms (so even all channels would overlap)
parameter VOSPI_MRST_AFTER_MS = 2000, // Wait after master reset and generate SOF pulse to advance sequencer
parameter VOSPI_SPI_TIMEOUT_MS = 185 // Wait to tymeout SPI when needed to re-sync
`else
......@@ -1061,7 +1061,7 @@ module sensor_channel#(
.VOSPI_SOF_TO_HACT (VOSPI_SOF_TO_HACT), // 100,
.VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF), // 2,
.VOSPI_MCLK_HALFDIV (VOSPI_MCLK_HALFDIV), // 4
.VOSPI_MRST_MS (VOSPI_MRST_MS), // 5
.VOSPI_MRST_MS (VOSPI_MRST_MS), // 200, // master reset duration in ms (so even all channels would overlap)
.VOSPI_MRST_AFTER_MS (VOSPI_MRST_AFTER_MS), // 2000
.VOSPI_SPI_TIMEOUT_MS (VOSPI_SPI_TIMEOUT_MS) // 185
) sens_lepton3_i (
......
sensor/sensors393.v
View file @ 8f05c2c2
......@@ -272,7 +272,7 @@ module sensors393 #(
parameter VOSPI_SOF_TO_HACT = 100, // 10, // clock cycles from SOF to HACT (limited to 8 bits)
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
parameter VOSPI_MRST_MS = 5, // master reset duration in ms
parameter VOSPI_MRST_MS = 200, // master reset duration in ms (so even all channels would overlap)
parameter VOSPI_MRST_AFTER_MS = 2000, // Wait after master reset and generate SOF pulse to advance sequencer
parameter VOSPI_SPI_TIMEOUT_MS = 185, // Wait to tymeout SPI when needed to re-sync
`else
......@@ -764,7 +764,7 @@ module sensors393 #(
.VOSPI_SOF_TO_HACT (VOSPI_SOF_TO_HACT), // 100,
.VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF), // 2,
.VOSPI_MCLK_HALFDIV (VOSPI_MCLK_HALFDIV), // 4
.VOSPI_MRST_MS (VOSPI_MRST_MS), // 5
.VOSPI_MRST_MS (VOSPI_MRST_MS), // 200, // master reset duration in ms (so even all channels would overlap)
.VOSPI_MRST_AFTER_MS (VOSPI_MRST_AFTER_MS), // 2000
.VOSPI_SPI_TIMEOUT_MS (VOSPI_SPI_TIMEOUT_MS) // 185
`else
......
timing/camsync393.v
View file @ 8f05c2c2
This diff is collapsed.
x393.v
View file @ 8f05c2c2
......@@ -1883,7 +1883,7 @@ assign axi_grst = axi_rst_pre;
.VOSPI_SOF_TO_HACT (VOSPI_SOF_TO_HACT), // 100,
.VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF), // 2,
.VOSPI_MCLK_HALFDIV (VOSPI_MCLK_HALFDIV), // 4
.VOSPI_MRST_MS (VOSPI_MRST_MS), // 5
.VOSPI_MRST_MS (VOSPI_MRST_MS), // 200, // master reset duration in ms (so even all channels would overlap)
.VOSPI_MRST_AFTER_MS (VOSPI_MRST_AFTER_MS), // 2000
.VOSPI_SPI_TIMEOUT_MS (VOSPI_SPI_TIMEOUT_MS), // 185
......
x393_vospi.bit
View file @ 8f05c2c2
No preview for this file type
x393_vospi.timing_summary_impl
View file @ 8f05c2c2
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x393_vospi_utilization.report
View file @ 8f05c2c2
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
| Date : Thu May 2 22:27:59 2019
| Date : Fri May 3 14:00:41 2019
| Host : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS
| Command : report_utilization -file vivado_build/x393_vospi_utilization.report
| Design : x393
......@@ -31,13 +31,13 @@ Table of Contents
+----------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs | 42274 | 0 | 78600 | 53.78 |
| LUT as Logic | 38918 | 0 | 78600 | 49.51 |
| LUT as Memory | 3356 | 0 | 26600 | 12.62 |
| Slice LUTs | 42462 | 0 | 78600 | 54.02 |
| LUT as Logic | 39108 | 0 | 78600 | 49.76 |
| LUT as Memory | 3354 | 0 | 26600 | 12.61 |
| LUT as Distributed RAM | 2802 | 0 | | |
| LUT as Shift Register | 554 | 0 | | |
| Slice Registers | 54220 | 0 | 157200 | 34.49 |
| Register as Flip Flop | 54220 | 0 | 157200 | 34.49 |
| LUT as Shift Register | 552 | 0 | | |
| Slice Registers | 54238 | 0 | 157200 | 34.50 |
| Register as Flip Flop | 54238 | 0 | 157200 | 34.50 |
| Register as Latch | 0 | 0 | 157200 | 0.00 |
| F7 Muxes | 34 | 0 | 39300 | 0.09 |
| F8 Muxes | 0 | 0 | 19650 | 0.00 |
......@@ -58,8 +58,8 @@ Table of Contents
| 0 | Yes | - | - |
| 8 | Yes | - | Set |
| 680 | Yes | - | Reset |
| 1084 | Yes | Set | - |
| 52448 | Yes | Reset | - |
| 1108 | Yes | Set | - |
| 52442 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
......@@ -69,27 +69,27 @@ Table of Contents
+-------------------------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------------------------+-------+-------+-----------+-------+
| Slice | 16898 | 0 | 19650 | 85.99 |
| SLICEL | 11122 | 0 | | |
| SLICEM | 5776 | 0 | | |
| LUT as Logic | 38918 | 0 | 78600 | 49.51 |
| using O5 output only | 1 | | | |
| using O6 output only | 30285 | | | |
| using O5 and O6 | 8632 | | | |
| LUT as Memory | 3356 | 0 | 26600 | 12.62 |
| Slice | 16910 | 0 | 19650 | 86.06 |
| SLICEL | 11158 | 0 | | |
| SLICEM | 5752 | 0 | | |
| LUT as Logic | 39108 | 0 | 78600 | 49.76 |
| using O5 output only | 6 | | | |
| using O6 output only | 30466 | | | |
| using O5 and O6 | 8636 | | | |
| LUT as Memory | 3354 | 0 | 26600 | 12.61 |
| LUT as Distributed RAM | 2802 | 0 | | |
| using O5 output only | 2 | | | |
| using O6 output only | 84 | | | |
| using O5 and O6 | 2716 | | | |
| LUT as Shift Register | 554 | 0 | | |
| using O5 output only | 285 | | | |
| using O6 output only | 219 | | | |
| using O5 and O6 | 50 | | | |
| LUT Flip Flop Pairs | 24502 | 0 | 78600 | 31.17 |
| fully used LUT-FF pairs | 4550 | | | |
| LUT-FF pairs with one unused LUT output | 17779 | | | |
| LUT-FF pairs with one unused Flip Flop | 17787 | | | |
| Unique Control Sets | 4739 | | | |
| LUT as Shift Register | 552 | 0 | | |
| using O5 output only | 272 | | | |
| using O6 output only | 228 | | | |
| using O5 and O6 | 52 | | | |
| LUT Flip Flop Pairs | 24526 | 0 | 78600 | 31.20 |
| fully used LUT-FF pairs | 4532 | | | |
| LUT-FF pairs with one unused LUT output | 17794 | | | |
| LUT-FF pairs with one unused Flip Flop | 17697 | | | |
| Unique Control Sets | 4907 | | | |
+-------------------------------------------+-------+-------+-----------+-------+
* Note: Review the Control Sets Report for more information regarding control sets.
......@@ -196,17 +196,17 @@ Table of Contents
+------------------------+-------+----------------------+
| Ref Name | Used | Functional Category |
+------------------------+-------+----------------------+
| FDRE | 52448 | Flop & Latch |
| LUT3 | 11328 | LUT |
| LUT6 | 10336 | LUT |
| LUT2 | 8397 | LUT |
| LUT4 | 7992 | LUT |
| LUT5 | 7901 | LUT |
| FDRE | 52442 | Flop & Latch |
| LUT3 | 11375 | LUT |
| LUT6 | 10433 | LUT |
| LUT2 | 8421 | LUT |
| LUT4 | 8002 | LUT |
| LUT5 | 7906 | LUT |
| RAMD32 | 4126 | Distributed Memory |
| CARRY4 | 2733 | CarryLogic |
| LUT1 | 1596 | LUT |
| LUT1 | 1607 | LUT |
| RAMS32 | 1392 | Distributed Memory |
| FDSE | 1084 | Flop & Latch |
| FDSE | 1108 | Flop & Latch |
| FDCE | 680 | Flop & Latch |
| SRL16E | 496 | Distributed Memory |
| SRLC32E | 108 | Distributed Memory |
......
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