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x393
Commit 8f05c2c2 authored by Andrey Filippov's avatar Andrey Filippov
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adding rigger out from the sensors running i free mode

parent ae33ff53
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cocotb/x393_cocotb_lwir_04.sav
View file @ 8f05c2c2
[*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Fri May 3 04:06:38 2019
[*] Fri May 3 15:28:46 2019
[*]
[dumpfile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/simulation/x393_dut-20190502213839545.fst"
[dumpfile_mtime] "Fri May 3 04:06:09 2019"
......@@ -3061,16 +3061,44 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepto
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.start_spi_seq_mclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.start_spi_seq_pclk
@29
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.spi_timeout_cntr[1:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.spi_seq
@200
-
@1000200
-reset_seq
@800200
-sens_channel0
-timestamping
@22
x393_dut.x393_i.timing393_i.frame_sync[3:0]
@28
x393_dut.x393_i.timing393_i.frsync_chn0
x393_dut.x393_i.timing393_i.frsync_chn1
x393_dut.x393_i.timing393_i.frsync_chn2
x393_dut.x393_i.timing393_i.frsync_chn3
@22
x393_dut.x393_i.timing393_i.trig[3:0]
@28
x393_dut.x393_i.timing393_i.trig_chn0
x393_dut.x393_i.timing393_i.trig_chn1
x393_dut.x393_i.timing393_i.trig_chn2
x393_dut.x393_i.timing393_i.trig_chn3
x393_dut.x393_i.timing393_i.triggered_mode
@22
x393_dut.x393_i.timing393_i.ts_data_chn0[7:0]
x393_dut.x393_i.timing393_i.ts_data_chn1[7:0]
x393_dut.x393_i.timing393_i.ts_data_chn2[7:0]
x393_dut.x393_i.timing393_i.ts_data_chn3[7:0]
x393_dut.x393_i.timing393_i.ts_stb[3:0]
@28
x393_dut.x393_i.timing393_i.ts_stb_chn0
x393_dut.x393_i.timing393_i.ts_stb_chn1
x393_dut.x393_i.timing393_i.ts_stb_chn2
x393_dut.x393_i.timing393_i.ts_stb_chn3
@201
-
@1000200
-timestamping
@800200
-lepto3_0
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.prst
......
fpga_version.vh
View file @ 8f05c2c2
......@@ -35,7 +35,8 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h03930136; // Fiixing spi_seq
parameter FPGA_VERSION = 32'h03930137; // longer reset, sync output
// parameter FPGA_VERSION = 32'h03930136; // Fiixing spi_seq
// parameter FPGA_VERSION = 32'h03930135; // Adding multi-cam reset
// parameter FPGA_VERSION = 32'h0393014; // Adding multi-cam reset - buggy
// parameter FPGA_VERSION = 32'h03930133; // Works with linux kernel rocko commit of 05/01/2019 bd61276e05f7343415929112ae368230a9c472f0
......
includes/x393_parameters.vh
View file @ 8f05c2c2
......@@ -594,7 +594,7 @@
parameter VOSPI_MRST_AFTER_MS = 5, // Wait after master reset and generate SOF pulse to advance sequencer
parameter VOSPI_SPI_TIMEOUT_MS = 3, // Wait to tymeout SPI when needed to re-sync
`else
parameter VOSPI_MRST_MS = 5, // master reset duration in ms
parameter VOSPI_MRST_MS = 200, // master reset duration in ms (so even all channels would overlap)
parameter VOSPI_MRST_AFTER_MS = 2000, // Wait after master reset and generate SOF pulse to advance sequencer
parameter VOSPI_SPI_TIMEOUT_MS = 185, // Wait to tymeout SPI when needed to re-sync
`endif
......
sensor/sens_lepton3.v
View file @ 8f05c2c2
......@@ -89,7 +89,7 @@ module sens_lepton3 #(
parameter VOSPI_SOF_TO_HACT = 100, // 10, // clock cycles from SOF to HACT (limited to 8 bits)
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
parameter VOSPI_MRST_MS = 5, // master reset duration in ms
parameter VOSPI_MRST_MS = 200, // master reset duration in ms (so even all channels would overlap)
parameter VOSPI_MRST_AFTER_MS = 2000, // Wait after master reset and generate SOF pulse to advance sequencer
parameter VOSPI_SPI_TIMEOUT_MS = 185 // Wait to tymeout SPI when needed to re-sync
)(
......
sensor/sensor_channel.v
View file @ 8f05c2c2
......@@ -276,7 +276,7 @@ module sensor_channel#(
parameter VOSPI_SOF_TO_HACT = 100, // 10, // clock cycles from SOF to HACT (limited to 8 bits)
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
parameter VOSPI_MRST_MS = 5, // master reset duration in ms
parameter VOSPI_MRST_MS = 200, // master reset duration in ms (so even all channels would overlap)
parameter VOSPI_MRST_AFTER_MS = 2000, // Wait after master reset and generate SOF pulse to advance sequencer
parameter VOSPI_SPI_TIMEOUT_MS = 185 // Wait to tymeout SPI when needed to re-sync
`else
......@@ -1061,7 +1061,7 @@ module sensor_channel#(
.VOSPI_SOF_TO_HACT (VOSPI_SOF_TO_HACT), // 100,
.VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF), // 2,
.VOSPI_MCLK_HALFDIV (VOSPI_MCLK_HALFDIV), // 4
.VOSPI_MRST_MS (VOSPI_MRST_MS), // 5
.VOSPI_MRST_MS (VOSPI_MRST_MS), // 200, // master reset duration in ms (so even all channels would overlap)
.VOSPI_MRST_AFTER_MS (VOSPI_MRST_AFTER_MS), // 2000
.VOSPI_SPI_TIMEOUT_MS (VOSPI_SPI_TIMEOUT_MS) // 185
) sens_lepton3_i (
......
sensor/sensors393.v
View file @ 8f05c2c2
......@@ -272,7 +272,7 @@ module sensors393 #(
parameter VOSPI_SOF_TO_HACT = 100, // 10, // clock cycles from SOF to HACT (limited to 8 bits)
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
parameter VOSPI_MRST_MS = 5, // master reset duration in ms
parameter VOSPI_MRST_MS = 200, // master reset duration in ms (so even all channels would overlap)
parameter VOSPI_MRST_AFTER_MS = 2000, // Wait after master reset and generate SOF pulse to advance sequencer
parameter VOSPI_SPI_TIMEOUT_MS = 185, // Wait to tymeout SPI when needed to re-sync
`else
......@@ -764,7 +764,7 @@ module sensors393 #(
.VOSPI_SOF_TO_HACT (VOSPI_SOF_TO_HACT), // 100,
.VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF), // 2,
.VOSPI_MCLK_HALFDIV (VOSPI_MCLK_HALFDIV), // 4
.VOSPI_MRST_MS (VOSPI_MRST_MS), // 5
.VOSPI_MRST_MS (VOSPI_MRST_MS), // 200, // master reset duration in ms (so even all channels would overlap)
.VOSPI_MRST_AFTER_MS (VOSPI_MRST_AFTER_MS), // 2000
.VOSPI_SPI_TIMEOUT_MS (VOSPI_SPI_TIMEOUT_MS) // 185
`else
......
timing/camsync393.v
View file @ 8f05c2c2
......@@ -236,6 +236,7 @@ module camsync393 #(
// delaying everything by 1 clock to reduce data fan in
reg high_zero; // 24 MSBs are zero
reg [9:0] input_use; // 1 - use this bit
// reg [3:0] input_use_cam; // 1 - use this bit
reg [9:0] input_pattern; // data to be compared for trigger event to take place
reg [9:0] gpio_out_en_r;
reg pre_input_use_intern = 1;// @(posedge mclk) Use internal trigger generator, 0 - use external trigger (also switches delay from input to output)
......@@ -282,6 +283,7 @@ module camsync393 #(
reg [31:0] dly_cntr_chn1; // trigger delay counter
reg [31:0] dly_cntr_chn2; // trigger delay counter
reg [31:0] dly_cntr_chn3; // trigger delay counter
wire [3:0] dly_cntr_non_zero; // respective delay counter is not zero
reg [3:0] dly_cntr_run=0; // trigger delay counter running (to use FD for simulation)
reg [3:0] dly_cntr_run_d=0; // trigger delay counter running - delayed by 1
wire [3:0] dly_cntr_end;
......@@ -373,19 +375,19 @@ module camsync393 #(
reg suppress_immediate; // suppress first trigger if period was not 0 (to avoid re-started frames)
wire start_pclk2_masked= start_pclk[2] && !suppress_immediate;
// reg
wire [3:0] frsync_pclk; // time to copy timestamps from master/received to channels (will always be after it is available)
// assign chn_en = ch_en_r & {4{en}}; // enable channels
wire [3:0] frsync_pclk; // time to copy timestamps from master/received to channels (will always be after it is available)
wire [3:0] dly_cntr_start; // start delay counters (added non-triggered mode option)
assign dly_cntr_start = triggered_mode_pclk? {4{start_dly}} : frsync_pclk; // each delay counter will be started in free running mode
assign dly_cntr_non_zero = {(dly_cntr_chn3[31:0]!=0)?1'b1:1'b0,
(dly_cntr_chn2[31:0]!=0)?1'b1:1'b0,
(dly_cntr_chn1[31:0]!=0)?1'b1:1'b0,
(dly_cntr_chn0[31:0]!=0)?1'b1:1'b0};
assign gpio_out_en = gpio_out_en_r;
// reg [3:0] ts_to_send; // per-channel discrimination between (first) timestamp to send and the second (individual, captured at frame sync)
//! in testmode GPIO[9] and GPIO[8] use internal signals instead of the outsync:
//! bit 11 - same as TRIGGER output to the sensor (signal to the sensor may be disabled externally)
//! then that bit will be still from internall trigger to frame valid
......@@ -394,8 +396,7 @@ module camsync393 #(
assign bit_length_plus1 [ 7:0] =bit_length[7:0]+1;
assign dly_cntr_end= dly_cntr_run_d & ~dly_cntr_run;
assign pre_start_out_pulse=input_use_intern?dly_cntr_end[master_chn]:start_late;
assign pre_start_out_pulse=input_use_intern?dly_cntr_end[master_chn]:start_late; // OK for non-triggered
assign gpio_out[7: 0] = out_data? gpio_active[7: 0]: ~gpio_active[7: 0];
assign gpio_out[8] = (testmode? dly_cntr_run[0]: out_data)? gpio_active[8]: ~gpio_active[8];
......@@ -434,8 +435,6 @@ module camsync393 #(
assign triggered_mode = triggered_mode_r;
assign {ts_snap_mclk_chn3, ts_snap_mclk_chn2, ts_snap_mclk_chn1, ts_snap_mclk_chn0 } = {4{en}} & (triggered_mode? ts_snap_triggered_mclk: frame_sync);
// keep previous value if 2'b01
// assign input_use_w = pre_input_use | (~pre_input_use & pre_input_pattern & input_use);
// wire [9:0] input_mask = pre_input_pattern | ~pre_input_use;
wire [9:0] input_mask = ~pre_input_pattern | pre_input_use;
wire [9:0] input_use_w = ((input_use ^ pre_input_use) & input_mask) ^ input_use;
wire [9:0] input_pattern_w = ((input_pattern ^ pre_input_pattern) & input_mask) ^ input_pattern;
......@@ -464,7 +463,6 @@ module camsync393 #(
end
// Do not try to use external timestamp in free run or internally triggered mode
/// ts_external <= ts_external_m && !input_use_intern && triggered_mode_r;
ts_external <= ts_external_m && triggered_mode_r; // internal will still use common timestamp made for sending
if (mrst) input_use <= 0;
......@@ -472,10 +470,12 @@ module camsync393 #(
input_use <= 0;
input_pattern <= 0;
pre_input_use_intern <= 1; // use internal source for triggering
// input_use_cam <= 0;
end else if (set_trig_src_w) begin
input_use <= input_use_w;
input_pattern <= input_pattern_w;
pre_input_use_intern <= (input_use_w == 0); // use internal source for triggering
pre_input_use_intern <= (input_use_w == 0) && (cmd_data[23:20] == 0); // use internal source for triggering
// input_use_cam <= cmd_data[23:20]; // use camera frame sync for triggering
end
if (set_trig_delay0_w) begin
......@@ -521,7 +521,6 @@ module camsync393 #(
start_en <= en && (repeat_period[31:0]!=0);
// if (!en) rep_en <= 0;
if (mrst) rep_en <= 0;
else if (set_period) rep_en <= !high_zero;
......@@ -547,7 +546,6 @@ module camsync393 #(
// request master timestamp at start if it is sent out or at receive (if it is not). ts_snd_en_pclk should be 0 if incoming sync does not have timestamps
/// ts_master_snap_pclk <= ts_snd_en_pclk? start_pclk[2]: rcv_done;
ts_master_snap_pclk <= ts_snd_en_pclk? start_pclk2_masked: rcv_done;
ts_snd_en_pclk<=ts_snd_en;
......@@ -600,7 +598,7 @@ module camsync393 #(
ext_int_mode_pclk <= ext_int_mode_mclk;
end
/*
always @ (posedge pclk) begin
if (eprst) dly_cntr_run <= 0;
else if (!triggered_mode_pclk) dly_cntr_run <= 0;
......@@ -611,6 +609,13 @@ module camsync393 #(
(dly_cntr_chn1[31:0]!=0)?1'b1:1'b0,
(dly_cntr_chn0[31:0]!=0)?1'b1:1'b0};
end
*/
always @ (posedge pclk) begin
if (eprst) dly_cntr_run <= 0;
else dly_cntr_run <= dly_cntr_start | (dly_cntr_run & dly_cntr_non_zero);
end
`ifdef GENERATE_TRIG_OVERDUE
always @ (posedge mclk) begin
......@@ -642,11 +647,6 @@ module camsync393 #(
triggered_mode_pclk<= triggered_mode_r;
bit_length_short[7:0] <= bit_length[7:0]-bit_length_plus1[7:2]-1; // 3/4 of the duration
// trigger_condition <= (((gpio_in[9:0] ^ input_pattern[9:0]) & input_use[9:0]) == 10'b0);
// trigger_condition <= (((gpio_in[9:0] ^ input_pattern[9:0]) & input_use[9:0] &
// ~(ext_int_mode_pclk?(10'b1 << CAMSYNC_GPIO_EXT_IN):10'b0)) == 10'b0); // disable external trigger in line
// trigger_condition_mask_w is @ mclk, but input signal is asynchronous too, so filtering is needed anyway)
trigger_condition <= (|trigger_condition_mask_w) && (((gpio_in[9:0] ^ input_pattern[9:0]) & trigger_condition_mask_w) == 10'b0); // disable external trigger in line
trigger_condition_d <= {trigger_condition_d[0], trigger_condition};
......@@ -683,9 +683,6 @@ module camsync393 #(
(rcv_run && !rcv_run_d); // all start at the same time - master/others
/// start_early <=input_use_intern ?
/// (start_pclk[2] && start_en) :
/// (rcv_run && !rcv_run_d); // all start at the same time - master/others
start_early <=input_use_intern ?
(start_pclk2_masked && start_en) :
(rcv_run && !rcv_run_d); // all start at the same time - master/others
......@@ -775,65 +772,10 @@ module camsync393 #(
end
/*
if (rcv_done) begin
ts_rcv_sec_chn0 [31:0] <= {sr_rcv_first[25:0],sr_rcv_second[31:26]};
ts_rcv_usec_chn0 [19:0] <= rcv_error?20'hfffff: sr_rcv_second[25:6];
end else if (master_got_pclk && ts_external_pclk) begin
ts_rcv_sec_chn0[31:0] <= ts_snd_sec[31:0];
ts_rcv_usec_chn0[19:0] <= ts_snd_usec[19:0];
end else if (!triggered_mode_pclk || (!ts_external_pclk && local_got_pclk[0])) begin
ts_rcv_sec_chn0[31:0] <= ts_snd_sec_chn0 [31:0];
ts_rcv_usec_chn0[19:0] <= ts_snd_usec_chn0[19:0];
end
ts_incoming <= ts_snd_en_pclk && !input_use_intern;
if (triggered_mode_pclk && ts_external_pclk) begin
if (frsync_pclk[0]) begin
ts_rcv_sec_chn0 [31:0] <= ts_incoming? {sr_rcv_first[25:0], sr_rcv_second[31:26]} : ts_snd_sec[31:0];
ts_rcv_usec_chn0 [19:0] <= ts_incoming? {rcv_error?20'hfffff: sr_rcv_second[25:6]} : ts_snd_usec[19:0];
end
if (frsync_pclk[1]) begin
ts_rcv_sec_chn1 [31:0] <= ts_incoming? {sr_rcv_first[25:0], sr_rcv_second[31:26]} : ts_snd_sec[31:0];
ts_rcv_usec_chn1 [19:0] <= ts_incoming? {rcv_error?20'hfffff: sr_rcv_second[25:6]} : ts_snd_usec[19:0];
end
if (frsync_pclk[2]) begin
ts_rcv_sec_chn2 [31:0] <= ts_incoming? {sr_rcv_first[25:0], sr_rcv_second[31:26]} : ts_snd_sec[31:0];
ts_rcv_usec_chn2 [19:0] <= ts_incoming? {rcv_error?20'hfffff: sr_rcv_second[25:6]} : ts_snd_usec[19:0];
end
if (frsync_pclk[3]) begin
ts_rcv_sec_chn3 [31:0] <= ts_incoming? {sr_rcv_first[25:0], sr_rcv_second[31:26]} : ts_snd_sec[31:0];
ts_rcv_usec_chn3 [19:0] <= ts_incoming? {rcv_error?20'hfffff: sr_rcv_second[25:6]} : ts_snd_usec[19:0];
end
end else begin
if (local_got_pclk[0]) begin
ts_rcv_sec_chn0[31:0] <= ts_snd_sec_chn0 [31:0];
ts_rcv_usec_chn0[19:0] <= ts_snd_usec_chn0[19:0];
end
if (local_got_pclk[1]) begin
ts_rcv_sec_chn1[31:0] <= ts_snd_sec_chn1 [31:0];
ts_rcv_usec_chn1[19:0] <= ts_snd_usec_chn1[19:0];
end
if (local_got_pclk[2]) begin
ts_rcv_sec_chn2[31:0] <= ts_snd_sec_chn2 [31:0];
ts_rcv_usec_chn2[19:0] <= ts_snd_usec_chn2[19:0];
end
if (local_got_pclk[3]) begin
ts_rcv_sec_chn3[31:0] <= ts_snd_sec_chn3 [31:0];
ts_rcv_usec_chn3[19:0] <= ts_snd_usec_chn3[19:0];
end
end
*/
end
// assign ts_stb = (!ts_external || pre_input_use_intern) ? local_got : {4{rcv_done_mclk}};
// rcv_done_mclk - make it either really received or from FPGA if internal?
// Making delayed start that waits for timestamp use timestamp_got, otherwise - nothing to wait
/// assign start_late = ts_snd_en_pclk?master_got_pclk : start_pclk[2];
assign start_late = ts_snd_en_pclk?master_got_pclk : start_pclk2_masked;
assign start_late_first = start_late && (armed_internal_trigger|| !ts_snd_en_pclk);
......
x393.v
View file @ 8f05c2c2
......@@ -1883,7 +1883,7 @@ assign axi_grst = axi_rst_pre;
.VOSPI_SOF_TO_HACT (VOSPI_SOF_TO_HACT), // 100,
.VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF), // 2,
.VOSPI_MCLK_HALFDIV (VOSPI_MCLK_HALFDIV), // 4
.VOSPI_MRST_MS (VOSPI_MRST_MS), // 5
.VOSPI_MRST_MS (VOSPI_MRST_MS), // 200, // master reset duration in ms (so even all channels would overlap)
.VOSPI_MRST_AFTER_MS (VOSPI_MRST_AFTER_MS), // 2000
.VOSPI_SPI_TIMEOUT_MS (VOSPI_SPI_TIMEOUT_MS), // 185
......
x393_vospi.bit
View file @ 8f05c2c2
No preview for this file type
x393_vospi.timing_summary_impl
View file @ 8f05c2c2
This source diff could not be displayed because it is too large. You can view the blob instead.
x393_vospi_utilization.report
View file @ 8f05c2c2
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
| Date : Thu May 2 22:27:59 2019
| Date : Fri May 3 14:00:41 2019
| Host : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS
| Command : report_utilization -file vivado_build/x393_vospi_utilization.report
| Design : x393
......@@ -31,13 +31,13 @@ Table of Contents
+----------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs | 42274 | 0 | 78600 | 53.78 |
| LUT as Logic | 38918 | 0 | 78600 | 49.51 |
| LUT as Memory | 3356 | 0 | 26600 | 12.62 |
| Slice LUTs | 42462 | 0 | 78600 | 54.02 |
| LUT as Logic | 39108 | 0 | 78600 | 49.76 |
| LUT as Memory | 3354 | 0 | 26600 | 12.61 |
| LUT as Distributed RAM | 2802 | 0 | | |
| LUT as Shift Register | 554 | 0 | | |
| Slice Registers | 54220 | 0 | 157200 | 34.49 |
| Register as Flip Flop | 54220 | 0 | 157200 | 34.49 |
| LUT as Shift Register | 552 | 0 | | |
| Slice Registers | 54238 | 0 | 157200 | 34.50 |
| Register as Flip Flop | 54238 | 0 | 157200 | 34.50 |
| Register as Latch | 0 | 0 | 157200 | 0.00 |
| F7 Muxes | 34 | 0 | 39300 | 0.09 |
| F8 Muxes | 0 | 0 | 19650 | 0.00 |
......@@ -58,8 +58,8 @@ Table of Contents
| 0 | Yes | - | - |
| 8 | Yes | - | Set |
| 680 | Yes | - | Reset |
| 1084 | Yes | Set | - |
| 52448 | Yes | Reset | - |
| 1108 | Yes | Set | - |
| 52442 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
......@@ -69,27 +69,27 @@ Table of Contents
+-------------------------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------------------------+-------+-------+-----------+-------+
| Slice | 16898 | 0 | 19650 | 85.99 |
| SLICEL | 11122 | 0 | | |
| SLICEM | 5776 | 0 | | |
| LUT as Logic | 38918 | 0 | 78600 | 49.51 |
| using O5 output only | 1 | | | |
| using O6 output only | 30285 | | | |
| using O5 and O6 | 8632 | | | |
| LUT as Memory | 3356 | 0 | 26600 | 12.62 |
| Slice | 16910 | 0 | 19650 | 86.06 |
| SLICEL | 11158 | 0 | | |
| SLICEM | 5752 | 0 | | |
| LUT as Logic | 39108 | 0 | 78600 | 49.76 |
| using O5 output only | 6 | | | |
| using O6 output only | 30466 | | | |
| using O5 and O6 | 8636 | | | |
| LUT as Memory | 3354 | 0 | 26600 | 12.61 |
| LUT as Distributed RAM | 2802 | 0 | | |
| using O5 output only | 2 | | | |
| using O6 output only | 84 | | | |
| using O5 and O6 | 2716 | | | |
| LUT as Shift Register | 554 | 0 | | |
| using O5 output only | 285 | | | |
| using O6 output only | 219 | | | |
| using O5 and O6 | 50 | | | |
| LUT Flip Flop Pairs | 24502 | 0 | 78600 | 31.17 |
| fully used LUT-FF pairs | 4550 | | | |
| LUT-FF pairs with one unused LUT output | 17779 | | | |
| LUT-FF pairs with one unused Flip Flop | 17787 | | | |
| Unique Control Sets | 4739 | | | |
| LUT as Shift Register | 552 | 0 | | |
| using O5 output only | 272 | | | |
| using O6 output only | 228 | | | |
| using O5 and O6 | 52 | | | |
| LUT Flip Flop Pairs | 24526 | 0 | 78600 | 31.20 |
| fully used LUT-FF pairs | 4532 | | | |
| LUT-FF pairs with one unused LUT output | 17794 | | | |
| LUT-FF pairs with one unused Flip Flop | 17697 | | | |
| Unique Control Sets | 4907 | | | |
+-------------------------------------------+-------+-------+-----------+-------+
* Note: Review the Control Sets Report for more information regarding control sets.
......@@ -196,17 +196,17 @@ Table of Contents
+------------------------+-------+----------------------+
| Ref Name | Used | Functional Category |
+------------------------+-------+----------------------+
| FDRE | 52448 | Flop & Latch |
| LUT3 | 11328 | LUT |
| LUT6 | 10336 | LUT |
| LUT2 | 8397 | LUT |
| LUT4 | 7992 | LUT |
| LUT5 | 7901 | LUT |
| FDRE | 52442 | Flop & Latch |
| LUT3 | 11375 | LUT |
| LUT6 | 10433 | LUT |
| LUT2 | 8421 | LUT |
| LUT4 | 8002 | LUT |
| LUT5 | 7906 | LUT |
| RAMD32 | 4126 | Distributed Memory |
| CARRY4 | 2733 | CarryLogic |
| LUT1 | 1596 | LUT |
| LUT1 | 1607 | LUT |
| RAMS32 | 1392 | Distributed Memory |
| FDSE | 1084 | Flop & Latch |
| FDSE | 1108 | Flop & Latch |
| FDCE | 680 | Flop & Latch |
| SRL16E | 496 | Distributed Memory |
| SRLC32E | 108 | Distributed Memory |
......
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