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Commit 51d9d5ad authored by Andrey Filippov's avatar Andrey Filippov
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working on memory channels synchronization

parent 95bcaf82
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cocotb/x393_cocotb_02.sav
View file @ 51d9d5ad
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compressor_jp/jp_channel.v
View file @ 51d9d5ad
......@@ -166,6 +166,8 @@ module jp_channel#(
input frame_done_dst, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
// use as 'eot_real' in 353
output suspend, // suspend reading data for this channel - waiting for the source data
// output master_follow, // compressor is following sensor, copy sesnor frame number instead of reset.
output reg [LAST_FRAME_BITS-1:0] frame_number_finished, // valid after stuffer done
......@@ -781,14 +783,14 @@ module jp_channel#(
.mrst (mrst), // input
.xrst (xrst), // input
.cmprs_en (cmprs_en_mclk), // input - @mclk 0 resets immediately
.cmprs_en_extend (cmprs_en_extend), // output
.cmprs_en_extend (cmprs_en_extend), // output
.cmprs_run (cmprs_run_mclk), // input - @mclk enable propagation of vsync_late to frame_start_dst in bonded(sync to src) mode
.cmprs_standalone (cmprs_standalone), // input - @mclk single-cycle: generate a single frame_start_dst in unbonded (not synchronized) mode.
// cmprs_run should be off
.sigle_frame_buf (sigle_frame_buf), // input - memory controller uses a single frame buffer (frame_number_* == 0), use other sync
.vsync_late (vsync_late), // input - @mclk delayed start of frame, @xclk. In 353 it was 16 lines after VACT active
// source channel should already start, some delay give time for sequencer commands
// that should arrive before it
// that should arrive before it, in NC393 it is programmable
.frame_started (first_mb && mb_pre_start), // @xclk started first macroblock (checking for broken frames)
.frame_start_dst (frame_start_dst), // output reg @mclk - trigger receive (tiled) memory channel (it will take care of
// single/repetitive modes itself this output either follows vsync_late (reclocks it)
......
fpga_version.vh
View file @ 51d9d5ad
......@@ -35,14 +35,15 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h039300a8; // parallel, fixing BUG in command sequencer that was missing some commands 79.25%, all met
// parameter FPGA_VERSION = 32'h039300a7; // parallel, changing parameter to reset buffer pages at each frame start. 79.4%, -0.022 (2 paths)
// parameter FPGA_VERSION = 32'h039300a6; // parallel, adding frame sync delays to mcntrl_linear 79.26, mclk and xclk violated
// parameter FPGA_VERSION = 32'h039300a5; // parallel, fixing command sequencer and ARO 80.21%, -0.068
// parameter FPGA_VERSION = 32'h039300a4; // parallel 79.66, -0.1
// parameter FPGA_VERSION = 32'h039300a3; // hispi, after minor interface changes (separated control bits)80.52% -0.163
// parameter FPGA_VERSION = 32'h039300a2; // hispi trying default placement 81.39% not met by -0.183
// parameter FPGA_VERSION = 32'h039300a1; // hispi 81.19%, not met by -0.07
parameter FPGA_VERSION = 32'h039300a9; // parallel, added copying maste-t-slave frame number -0.169(8 paths), 80.28%
// parameter FPGA_VERSION = 32'h039300a8; // parallel, fixing BUG in command sequencer that was missing some commands 79.25%, all met
// parameter FPGA_VERSION = 32'h039300a7; // parallel, changing parameter to reset buffer pages at each frame start. 79.4%, -0.022 (2 paths)
// parameter FPGA_VERSION = 32'h039300a6; // parallel, adding frame sync delays to mcntrl_linear 79.26, mclk and xclk violated
// parameter FPGA_VERSION = 32'h039300a5; // parallel, fixing command sequencer and ARO 80.21%, -0.068
// parameter FPGA_VERSION = 32'h039300a4; // parallel 79.66, -0.1
// parameter FPGA_VERSION = 32'h039300a3; // hispi, after minor interface changes (separated control bits)80.52% -0.163
// parameter FPGA_VERSION = 32'h039300a2; // hispi trying default placement 81.39% not met by -0.183
// parameter FPGA_VERSION = 32'h039300a1; // hispi 81.19%, not met by -0.07
// parameter FPGA_VERSION = 32'h039300a0; // parallel, re-ran after bug fix, %79.38%, not met -0.072
// parameter FPGA_VERSION = 32'h039300a0; // parallel, else same as 9f 78.91%, not met by -0.032
// parameter FPGA_VERSION = 32'h0393009f; // hispi, adding IRQ status register (placemnt "explore") 81.36%, all met - broken on one channel?
......
includes/x393_parameters.vh
View file @ 51d9d5ad
......@@ -297,6 +297,8 @@
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers
parameter MCONTR_LINTILE_COPY_FRAME = 13, // copy frame number from the master channel (single event, not a persistent mode)
parameter MCNTRL_SCANLINE_DLY_WIDTH = 7, // delay start pulse by 1..64 mclk
parameter MCNTRL_SCANLINE_DLY_DEFAULT = 63, // initial delay value for start pulse
......
memctrl/mcntrl393.v
View file @ 51d9d5ad
......@@ -261,6 +261,7 @@ module mcntrl393 #(
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers
parameter MCONTR_LINTILE_COPY_FRAME = 13, // copy frame number from the master channel (single event, not a persistent mode)
parameter MCNTRL_SCANLINE_DLY_WIDTH = 7, // delay start pulse by 1..64 mclk
parameter MCNTRL_SCANLINE_DLY_DEFAULT = 63 // initial delay value for start pulse
......@@ -352,7 +353,7 @@ module mcntrl393 #(
output [3:0] cmprs_frame_done_dst, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
// use as 'eot_real' in 353
input [3:0] cmprs_suspend, // suspend reading data for this channel - waiting for the source data
// input [3:0] master_follow, // compressor memory frame should follow that of the sensor channel, instead of reset
// TODO: move line_unfinished and suspend to internals of this module (and control comparator modes)
// Channel 1 - AFI read/write to system memory with scanline linear mode
input frame_start_chn1, // resets page, x,y, and initiates transfer requests (in write mode will wait for next_page)
......@@ -564,6 +565,7 @@ module mcntrl393 #(
wire [3:0] status_cmprs_start;
// Sensor and compressor signals
wire [3:0] sens_frame_set; // sensor memory controller has just set frame number (slave can use to sync)
wire [3:0] sens_want;
wire [3:0] sens_need;
wire [3:0] cmprs_want;
......@@ -1129,7 +1131,8 @@ module mcntrl393 #(
.frame_finished (), // output
.line_unfinished (cmprs_line_unfinished_src[i * FRAME_HEIGHT_BITS +: FRAME_HEIGHT_BITS]), // output[15:0]
.suspend (1'b0), // input
.frame_number (cmprs_frame_number_src[i * LAST_FRAME_BITS +: LAST_FRAME_BITS]),
.frame_number (cmprs_frame_number_src[i * LAST_FRAME_BITS +: LAST_FRAME_BITS]), //output[15:0]
.frame_set (sens_frame_set[i]), // output
.xfer_want (sens_want[i]), // output
.xfer_need (sens_need[i]), // output
.xfer_grant (sens_channel_pgm_en[i]), // input
......@@ -1185,7 +1188,8 @@ module mcntrl393 #(
.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED)
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
.MCONTR_LINTILE_COPY_FRAME (MCONTR_LINTILE_COPY_FRAME)
) mcntrl_tiled_rd_compressor_i (
.mrst (mrst), // input
.mclk (mclk), // input
......@@ -1200,7 +1204,10 @@ module mcntrl393 #(
.frame_finished (), // output
.line_unfinished (cmprs_line_unfinished_dst[i * FRAME_HEIGHT_BITS +: FRAME_HEIGHT_BITS]), // output[15:0]
.suspend (cmprs_suspend[i]), // input
.frame_number (cmprs_frame_number_dst[i * LAST_FRAME_BITS +: LAST_FRAME_BITS]),
.frame_number (cmprs_frame_number_dst[i * LAST_FRAME_BITS +: LAST_FRAME_BITS]), // output[15:0]
.master_frame (cmprs_frame_number_src[i * LAST_FRAME_BITS +: LAST_FRAME_BITS]), // input[15:0]
.master_set (sens_frame_set[i]), // input
// .master_follow (master_follow[i]), // input
.xfer_want (cmprs_want[i]), // output
.xfer_need (cmprs_need[i]), // output
.xfer_grant (cmprs_channel_pgm_en[i]), // input
......@@ -1279,6 +1286,7 @@ module mcntrl393 #(
.line_unfinished (line_unfinished_chn1), // output[15:0]
.suspend (suspend_chn1), // input
.frame_number (), // output[15:0] - not used for this channel
.frame_set (), // output
.xfer_want (want_rq1), // output
.xfer_need (need_rq1), // output
.xfer_grant (channel_pgm_en1), // input
......@@ -1352,6 +1360,7 @@ module mcntrl393 #(
.line_unfinished (line_unfinished_chn3), // output[15:0]
.suspend (suspend_chn3), // input
.frame_number (frame_number_chn3),
.frame_set (), // output
.xfer_want (want_rq3), // output
.xfer_need (need_rq3), // output
.xfer_grant (channel_pgm_en3), // input
......@@ -1422,6 +1431,9 @@ module mcntrl393 #(
.line_unfinished (line_unfinished_chn2), // output[15:0]
.suspend (suspend_chn2), // input
.frame_number (frame_number_chn2),
.master_frame (16'b0), // input[15:0]
.master_set (1'b0), // input
// .master_follow (1'b0), // input
.xfer_want (want_rq2), // output
.xfer_need (need_rq2), // output
.xfer_grant (channel_pgm_en2), // input
......@@ -1490,6 +1502,9 @@ module mcntrl393 #(
.line_unfinished (line_unfinished_chn4), // output[15:0]
.suspend (suspend_chn4), // input
.frame_number (frame_number_chn4), // output [15:0]
.master_frame (16'b0), // input[15:0]
.master_set (1'b0), // input
// .master_follow (1'b0), // input
.xfer_want (want_rq4), // output
.xfer_need (need_rq4), // output
.xfer_grant (channel_pgm_en4), // input
......
memctrl/mcntrl_linear_rw.v
View file @ 51d9d5ad
......@@ -106,6 +106,7 @@ module mcntrl_linear_rw #(
output [FRAME_HEIGHT_BITS-1:0] line_unfinished, // number of the current (unfinished ) line, RELATIVE TO FRAME, NOT WINDOW?.
input suspend, // suspend transfers (from external line number comparator)
output [LAST_FRAME_BITS-1:0] frame_number, // current frame number (for multi-frame ranges)
output frame_set, // frame number is just set to a new value (can be used by slave to sync)
output xfer_want, // "want" data transfer
output xfer_need, // "need" - really need a transfer (only 1 page/ room for 1 page left in a buffer), want should still be set.
input xfer_grant, // sequencer programming access granted, deassert wait/need
......@@ -258,6 +259,8 @@ module mcntrl_linear_rw #(
reg [MCNTRL_SCANLINE_DLY_WIDTH-1:0] start_delay; // how much to delay frame start
wire frame_start_late;
wire set_start_delay_w;
reg buf_reset_pend; // reset buffer page at next (late)frame sync (compressor should be disabled
// if total number of pages in a frame is not multiple of 4
assign frame_number = frame_number_current;
......@@ -277,7 +280,7 @@ module mcntrl_linear_rw #(
assign rst_frame_num_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_MODE) && cmd_data[MCONTR_LINTILE_RST_FRAME];
assign frame_run = busy_r;
assign frame_set = frame_start_r[3];
// Set parameter registers
always @(posedge mclk) begin
if (mrst) mode_reg <= 0;
......@@ -314,7 +317,11 @@ module mcntrl_linear_rw #(
if (mrst) frame_en <= 0;
else if (single_frame_r || repeat_frames) frame_en <= 1;
else if (frame_start_late) frame_en <= 0;
else if (frame_start_late) frame_en <= 0;
// will reset buffer page at next frame start
if (mrst ||frame_start_r[0]) buf_reset_pend <= 0;
else if (rst_frame_num_r) buf_reset_pend <= 1;
if (mrst) frame_number_cntr <= 0;
else if (rst_frame_num_r[0]) frame_number_cntr <= 0;
......@@ -578,10 +585,10 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
else if (!start_not_partial && next_page) page_cntr <= page_cntr + 1;
if (mrst) xfer_page_rst_r <= 1;
else xfer_page_rst_r <= chn_rst || (MCNTRL_SCANLINE_FRAME_PAGE_RESET ? (frame_start_r[0] & cmd_wrmem):1'b0);
else xfer_page_rst_r <= chn_rst || (buf_reset_pend && (MCNTRL_SCANLINE_FRAME_PAGE_RESET ? (frame_start_r[0] & cmd_wrmem):1'b0));
if (mrst) xfer_page_rst_pos <= 1;
else xfer_page_rst_pos <= chn_rst || (MCNTRL_SCANLINE_FRAME_PAGE_RESET ? (frame_start_r[0] & ~cmd_wrmem):1'b0);
else xfer_page_rst_pos <= chn_rst || (buf_reset_pend && (MCNTRL_SCANLINE_FRAME_PAGE_RESET ? (frame_start_r[0] & ~cmd_wrmem):1'b0));
// increment x,y (two cycles)
......
memctrl/mcntrl_tiled_rw.v
View file @ 51d9d5ad
......@@ -81,9 +81,9 @@ module mcntrl_tiled_rw#(
parameter MCONTR_LINTILE_BYTE32 = 6, // use 32-byte wide columns in each tile (false - 16-byte)
parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_DIS_NEED = 11 // disable 'need' request
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
parameter MCONTR_LINTILE_COPY_FRAME = 13 // copy frame number from the master channel (single event, not a persistent mode)
)(
input mrst,
input mclk,
......@@ -105,6 +105,9 @@ module mcntrl_tiled_rw#(
output [FRAME_HEIGHT_BITS-1:0] line_unfinished, // number of the current (unfinished ) line, RELATIVE TO FRAME, NOT WINDOW.
input suspend, // suspend transfers (from external line number comparator)
output [LAST_FRAME_BITS-1:0] frame_number, // current frame number (for multi-frame ranges)
input [LAST_FRAME_BITS-1:0] master_frame, // current frame number of a master channel
input master_set, // master frame number set (1-st cycle when new value is valid)
// input master_follow, // copy master frame number instead of reset @master_set, 0 - ignore master_set
output xfer_want, // "want" data transfer
output xfer_need, // "need" - really need a transfer (only 1 page/ room for 1 page left in a buffer), want should still be set.
input xfer_grant, // sequencer programming access granted, deassert wait/need
......@@ -185,6 +188,7 @@ module mcntrl_tiled_rw#(
wire repeat_frames; // mode bit
wire single_frame_w; // pulse
wire rst_frame_num_w;
wire set_copy_frame_num_w;
reg single_frame_r; // pulse
reg [1:0] rst_frame_num_r; // reset frame number/next start address
reg frame_en; // enable next frame
......@@ -264,6 +268,10 @@ module mcntrl_tiled_rw#(
reg [FRAME_WIDTH_BITS-1:0] start_x; // (programmed) normally 0, copied to curr_x on frame_start
reg [FRAME_HEIGHT_BITS-1:0] start_y; // (programmed) normally 0, copied to curr_y on frame_start
reg xfer_page_done_d; // next cycle after xfer_page_done
reg frame_master_pend; // set frame counter from the master frame number at next master_set
reg set_frame_from_master; // single-clock copy frame counter from the master channel
reg buf_reset_pend; // reset buffer page at next (late)frame sync (compressor should be disabled
// if total number of pages in a frame is not multiple of 4
assign frame_number = frame_number_current;
......@@ -278,10 +286,10 @@ module mcntrl_tiled_rw#(
assign set_window_start_w = cmd_we && (cmd_a== MCNTRL_TILED_WINDOW_STARTXY);
assign set_tile_whs_w = cmd_we && (cmd_a== MCNTRL_TILED_TILE_WHS);
assign single_frame_w = cmd_we && (cmd_a== MCNTRL_TILED_MODE) && cmd_data[MCONTR_LINTILE_SINGLE];
assign rst_frame_num_w = cmd_we && (cmd_a== MCNTRL_TILED_MODE) && cmd_data[MCONTR_LINTILE_RST_FRAME];
assign single_frame_w = cmd_we && (cmd_a== MCNTRL_TILED_MODE) && cmd_data[MCONTR_LINTILE_SINGLE];
assign rst_frame_num_w = cmd_we && (cmd_a== MCNTRL_TILED_MODE) && cmd_data[MCONTR_LINTILE_RST_FRAME];
assign set_copy_frame_num_w = cmd_we && (cmd_a== MCNTRL_TILED_MODE) && cmd_data[MCONTR_LINTILE_COPY_FRAME];
//
// Set parameter registers
always @(posedge mclk) begin
......@@ -293,7 +301,7 @@ module mcntrl_tiled_rw#(
if (mrst) rst_frame_num_r <= 0;
else rst_frame_num_r <= {rst_frame_num_r[0],
rst_frame_num_w |
rst_frame_num_w |
set_start_addr_w |
set_last_frame_w |
set_frame_size_w};
......@@ -321,9 +329,19 @@ module mcntrl_tiled_rw#(
else if (single_frame_r || repeat_frames) frame_en <= 1;
else if (frame_start) frame_en <= 0;
if (mrst) frame_number_cntr <= 0;
else if (rst_frame_num_r[0]) frame_number_cntr <= 0;
else if (frame_start_r[2]) frame_number_cntr <= is_last_frame?{LAST_FRAME_BITS{1'b0}}:(frame_number_cntr+1);
if (mrst ||master_set) frame_master_pend <= 0;
else if (set_copy_frame_num_w) frame_master_pend <= 1;
// will reset buffer page at next frame start
if (mrst ||frame_start_r[0]) buf_reset_pend <= 0;
else if (rst_frame_num_r) buf_reset_pend <= 1;
set_frame_from_master <= master_set && frame_master_pend;
if (mrst) frame_number_cntr <= 0;
else if (rst_frame_num_r[0]) frame_number_cntr <= 0;
else if (set_frame_from_master) frame_number_cntr <= master_frame;
else if (frame_start_r[2]) frame_number_cntr <= is_last_frame?{LAST_FRAME_BITS{1'b0}}:(frame_number_cntr+1);
if (mrst) frame_number_current <= 0;
else if (rst_frame_num_r[0]) frame_number_current <= 0;
......@@ -526,10 +544,10 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
else if (!start_not_partial && next_page) page_cntr <= page_cntr + 1;
if (mrst) xfer_page_rst_r <= 1;
else xfer_page_rst_r <= chn_rst || (MCNTRL_TILED_FRAME_PAGE_RESET ? (frame_start_r[0] & cmd_wrmem):1'b0);
else xfer_page_rst_r <= chn_rst || (buf_reset_pend && (MCNTRL_TILED_FRAME_PAGE_RESET ? (frame_start_r[0] & cmd_wrmem):1'b0));
if (mrst) xfer_page_rst_pos <= 1;
else xfer_page_rst_pos <= chn_rst || (MCNTRL_TILED_FRAME_PAGE_RESET ? (frame_start_r[0] & ~cmd_wrmem):1'b0);
else xfer_page_rst_pos <= chn_rst || (buf_reset_pend && (MCNTRL_TILED_FRAME_PAGE_RESET ? (frame_start_r[0] & ~cmd_wrmem):1'b0));
// increment x,y (two cycles)
if (mrst) curr_x <= 0;
......
py393/hargs
View file @ 51d9d5ad
......@@ -7,4 +7,4 @@
-c setupSensorsPower "PAR12" all 0 0.0
-c measure_all "*DI"
-c setSensorClock 24.0 "2V5_LVDS"
-c set_rtc # maybe not needed as it can be set differently
-c set_rtc
py393/vrlg.py
View file @ 51d9d5ad
......@@ -325,7 +325,7 @@ CMPRS_CBIT_CMODE_JP4DIFF__RAW = str
CMPRS_AFIMUX_MASK__TYPE = str
MCONTR_SENS_INC = int
CAMSYNC_TRIG_PERIOD__TYPE = str
CMPRS_STATUS_REG_BASE__RAW = str
SENSIO_STATUS = int
DFLT_DQS_PATTERN = int
SENS_GAMMA_ADDR_DATA__RAW = str
DLY_LANE1_IDELAY__RAW = str
......@@ -386,7 +386,6 @@ CMD_PAUSE_BITS__RAW = str
SENSI2C_TBL_DLY_BITS = int
IDELAY_VALUE__RAW = str
MULTICLK_PHASE_SYNC__TYPE = str
MCONTR_CMPRS_STATUS_BASE = int
BUFFER_DEPTH32 = int
SENS_CTRL_QUADRANTS__TYPE = str
SENS_LENS_BY_MASK__RAW = str
......@@ -428,6 +427,7 @@ MULTICLK_BUF_DLYREF__RAW = str
FCLK0_PERIOD = float
CMDFRAMESEQ_REL__TYPE = str
HISPI_DELAY_CLK0 = str
MCNTRL_SCANLINE_DLY_WIDTH = int
MAX_TILE_WIDTH__RAW = str
PICKLE = str
AFI_SIZE64__TYPE = str
......@@ -517,6 +517,7 @@ MCNTRL_TILED_FRAME_FULL_WIDTH = int
CMDFRAMESEQ_DEPTH = int
SENS_LENS_POST_SCALE__TYPE = str
RTC_MHZ__RAW = str
MCONTR_LINTILE_COPY_FRAME = int
SENSOR_PRIORITY__RAW = str
HIST_SAXI_ADDR_MASK__TYPE = str
SENS_CTRL_LD_DLY = int
......@@ -530,9 +531,11 @@ CMPRS_TABLES__TYPE = str
MCNTRL_PS_STATUS_CNTRL__TYPE = str
MCONTR_PHY_16BIT_ADDR = int
REF_JITTER1__TYPE = str
MCNTRL_TEST01_MASK = int
FFCLK1_DIFF_TERM = str
MULTICLK_PHASE_AXIHP__TYPE = str
FFCLK0_IOSTANDARD__TYPE = str
MCNTRL_SCANLINE_DLY_DEFAULT__TYPE = str
WOI_WIDTH__RAW = str
STATUS_MSB_RSHFT = int
CMPRS_CONTROL_REG__RAW = str
......@@ -546,7 +549,7 @@ MCONTR_BUF4_RD_ADDR__TYPE = str
NUM_CYCLES_16__RAW = str
LD_DLY_LANE0_ODELAY__TYPE = str
MCONTR_TOP_16BIT_ADDR__RAW = str
SENSIO_STATUS = int
MCNTRL_SCANLINE_DLY_WIDTH__RAW = str
HIST_SAXI_MODE_ADDR_REL = int
MCONTR_PHY_0BIT_SDRST_ACT__TYPE = str
BUFFER_DEPTH32__TYPE = str
......@@ -608,9 +611,10 @@ MCNTRL_TILED_MODE = int
MCNTRL_TILED_WINDOW_STARTXY__TYPE = str
CMPRS_COLOR20__TYPE = str
MCNTRL_TEST01_CHN2_STATUS_CNTRL__RAW = str
MCNTRL_SCANLINE_START_DELAY__TYPE = str
LOGGER_CONF_SYN = int
MCNTRL_TILED_CHN4_ADDR__RAW = str
CLK_DIV_PHASE__RAW = str
MCONTR_CMPRS_STATUS_BASE = int
MCONTR_PHY_16BIT_PATTERNS__TYPE = str
MCONTR_PHY_0BIT_CKE_EN__RAW = str
NUM_CYCLES_26__TYPE = str
......@@ -653,6 +657,7 @@ HISTOGRAM_TOP__TYPE = str
SENS_GAMMA_MODE_EN__RAW = str
SENSI2C_TBL_SA_BITS__TYPE = str
DEBUG_ADDR = int
MCNTRL_SCANLINE_START_DELAY__RAW = str
SIMULATE_CMPRS_CMODE2__TYPE = str
MULT_SAXI_ADV_WR__RAW = str
LOGGER_PAGE_GPS = int
......@@ -704,7 +709,7 @@ SENS_GAMMA_HEIGHT2 = int
DLY_LD_MASK__TYPE = str
STATUS_MSB_RSHFT__TYPE = str
MCONTR_BUF0_RD_ADDR = int
MCONTR_LINTILE_RST_FRAME__RAW = str
HIST_SAXI_ADDR_REL__TYPE = str
CMPRS_CBIT_CMODE_JPEG20 = int
CMPRS_TIMEOUT_BITS = int
CAMSYNC_PRE_MAGIC = int
......@@ -1066,6 +1071,7 @@ SENSI2C_STATUS_REG_INC__RAW = str
SDCLK_PHASE = float
SLEW_CMDA = str
SENSOR_IMAGE_TYPE0__RAW = str
CMPRS_STATUS_REG_BASE__RAW = str
MCNTRL_SCANLINE_MODE__TYPE = str
GPIO_N__RAW = str
TEST01_NEXT_PAGE__TYPE = str
......@@ -1510,12 +1516,14 @@ MEMCLK_IBUF_LOW_PWR__RAW = str
SENS_LENS_FAT0_OUT_MASK__RAW = str
SENSI2C_CMD_FIFO_RD__RAW = str
RTC_ADDR__TYPE = str
MCONTR_LINTILE_COPY_FRAME__RAW = str
SENSI2C_ABS_RADDR = int
PXD_IOSTANDARD__RAW = str
CMPRS_CBIT_FRAMES = int
SENS_GAMMA_HEIGHT01__RAW = str
CONTROL_RBACK_DEPTH__TYPE = str
CMPRS_CBIT_CMODE_MONO1__RAW = str
MCNTRL_SCANLINE_DLY_DEFAULT__RAW = str
GPIO_PORTEN__TYPE = str
CMDSEQMUX_ADDR__RAW = str
DLY_DM_ODELAY__TYPE = str
......@@ -1556,6 +1564,7 @@ CLK_ADDR__RAW = str
SENSIO_CTRL__RAW = str
HISTOGRAM_WIDTH__TYPE = str
MCNTRL_TILED_TILE_WHS = int
MCONTR_LINTILE_COPY_FRAME__TYPE = str
NUM_CYCLES_03__RAW = str
MULT_SAXI_HALF_BRAM = int
DLY_LANE1_DQS_WLV_IDELAY = long
......@@ -1682,9 +1691,9 @@ MCONTR_CMD_WR_ADDR__TYPE = str
SENSI2C_CMD_SOFT_SCL__TYPE = str
CLKFBOUT_MULT_SENSOR__RAW = str
CMPRS_CSAT_CR_BITS = int
HIST_SAXI_ADDR_REL__TYPE = str
MCONTR_LINTILE_RST_FRAME__RAW = str
LOGGER_CONFIG__TYPE = str
MCNTRL_TEST01_MASK = int
MCNTRL_SCANLINE_DLY_DEFAULT = int
TEST01_NEXT_PAGE__RAW = str
HIST_SAXI_MODE_ADDR_MASK__RAW = str
FFCLK1_IBUF_LOW_PWR__TYPE = str
......@@ -1774,6 +1783,7 @@ IPCLK_PHASE = float
SENSI2C_CTRL_RADDR = int
HIST_SAXI_MODE_ADDR_REL__RAW = str
AXI_WRDATA_LATENCY = int
MCNTRL_SCANLINE_START_DELAY = int
SENS_CTRL_QUADRANTS_EN = int
MCNTRL_SCANLINE_WINDOW_WH__RAW = str
MULTICLK_PHASE_FB__TYPE = str
......@@ -1935,6 +1945,7 @@ WOI_HEIGHT__RAW = str
SENS_LENS_COEFF = int
MULTICLK_PHASE_XCLK__RAW = str
LOGGER_BIT_DURATION__RAW = str
MCNTRL_SCANLINE_DLY_WIDTH__TYPE = str
MCONTR_WR_MASK__TYPE = str
SENS_LENS_C__RAW = str
CMDFRAMESEQ_ADDR_BASE__TYPE = str
......@@ -2135,6 +2146,7 @@ MCNTRL_PS_CMD = int
DEBUG_SHIFT_DATA__TYPE = str
MCNTRL_SCANLINE_CHN3_ADDR__TYPE = str
STATUS_2LSB_SHFT__RAW = str
CLK_DIV_PHASE__RAW = str
STATUS_MSB_RSHFT__RAW = str
SLEW_CMDA__RAW = str
HISPI_MMCM0__RAW = str
......
py393/x393_cmprs.py
View file @ 51d9d5ad
......@@ -350,6 +350,7 @@ class X393Cmprs(object):
num_sensor,
command,
reset_frame = False,
copy_frame = False,
verbose = 1):
"""
Control memory access (write) of a sensor channel
......@@ -359,7 +360,8 @@ class X393Cmprs(object):
stop - stop at the end of the frame (if repetitive),
single - acquire single frame ,
repetitive - repetitive mode
@param reset_frame - reset frame number
@param reset_frame - reset frame number
@param copy_frame copy frame number from the master channel (non-persistent)
@param vebose - verbose level
"""
try:
......@@ -369,6 +371,7 @@ class X393Cmprs(object):
self.control_compressor_memory(num_sensor = num_sensor,
command = command,
reset_frame = reset_frame,
copy_frame = copy_frame,
verbose = verbose)
return
except:
......@@ -406,7 +409,8 @@ class X393Cmprs(object):
extra_pages = 0,
write_mem = False,
enable = en,
chn_reset = rst)
chn_reset = rst,
copy_frame = copy_frame)
self.x393_axi_tasks.write_control_register(base_addr + vrlg.MCNTRL_TILED_MODE, mode)
if verbose > 0 :
......
py393/x393_export_c.py
View file @ 51d9d5ad
......@@ -277,6 +277,11 @@ class X393ExportC(object):
data = self._enc_window_frame_sa(),
name = "x393_mcntrl_window_frame_sa", typ="wo",
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "Delay start of the channel from sensor frame sync (to allow frame sequencer issue commands)",
data = self._enc_frame_start_dly(),
name = "x393_mcntrl_frame_start_dly", typ="wo",
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "PS PIO (software-programmed DDR3) access sequences enable and reset",
data = self._enc_ps_pio_en_rst(),
name = "x393_ps_pio_en_rst", typ="wo",
......@@ -702,7 +707,8 @@ class X393ExportC(object):
(("X393_SENS_MCNTRL_SCANLINE_FRAME_FULL_WIDTH",c, vrlg.MCNTRL_SCANLINE_FRAME_FULL_WIDTH + ba, ia, z3, "x393_mcntrl_window_full_width", "wo", "Set frame full(padded) width")),
(("X393_SENS_MCNTRL_SCANLINE_WINDOW_WH", c, vrlg.MCNTRL_SCANLINE_WINDOW_WH + ba, ia, z3, "x393_mcntrl_window_width_height", "wo", "Set frame window size")),
(("X393_SENS_MCNTRL_SCANLINE_WINDOW_X0Y0", c, vrlg.MCNTRL_SCANLINE_WINDOW_X0Y0 + ba, ia, z3, "x393_mcntrl_window_left_top", "wo", "Set frame position")),
(("X393_SENS_MCNTRL_SCANLINE_STARTXY", c, vrlg.MCNTRL_SCANLINE_WINDOW_STARTXY + ba, ia, z3, "x393_mcntrl_window_startx_starty", "wo", "Set startXY register"))]
(("X393_SENS_MCNTRL_SCANLINE_STARTXY", c, vrlg.MCNTRL_SCANLINE_WINDOW_STARTXY + ba, ia, z3, "x393_mcntrl_window_startx_starty", "wo", "Set startXY register")),
(("X393_SENS_MCNTRL_SCANLINE_START_DELAY", c, vrlg.MCNTRL_SCANLINE_START_DELAY + ba, ia, z3, "x393_mcntrl_frame_start_dly", "wo", "Set dDelay start of the channel from sensor frame sync"))]
ba = vrlg.MCONTR_CMPRS_BASE
ia = vrlg.MCONTR_CMPRS_INC
sdefines +=[
......@@ -1642,17 +1648,18 @@ class X393ExportC(object):
def _enc_func_encode_mode_scan_tiled(self):
dw=[]
dw.append(("chn_nreset", vrlg.MCONTR_LINTILE_EN,1,1, "0: immediately reset all the internal circuitry"))
dw.append(("enable", vrlg.MCONTR_LINTILE_NRESET,1,1, "enable requests from this channel ( 0 will let current to finish, but not raise want/need)"))
dw.append(("enable", vrlg.MCONTR_LINTILE_EN,1,1, "enable requests from this channel ( 0 will let current to finish, but not raise want/need)"))
dw.append(("chn_nreset", vrlg.MCONTR_LINTILE_NRESET,1,1, "0: immediately reset all the internal circuitry"))
dw.append(("write_mem", vrlg.MCONTR_LINTILE_WRITE,1,0, "0 - read from memory, 1 - write to memory"))
dw.append(("extra_pages", vrlg.MCONTR_LINTILE_EXTRAPG, vrlg.MCONTR_LINTILE_EXTRAPG_BITS,0, "2-bit number of extra pages that need to stay (not to be overwritten) in the buffer"))
dw.append(("keep_open", vrlg.MCONTR_LINTILE_KEEP_OPEN,1,0, "for 8 or less rows - do not close page between accesses (not used in scanline mode)"))
dw.append(("byte32", vrlg.MCONTR_LINTILE_BYTE32,1,1, "32-byte columns (0 - 16-byte), not used in scanline mode"))
dw.append(("reset_frame", vrlg.MCONTR_LINTILE_RST_FRAME,1,0, "reset frame number"))
dw.append(("reset_frame", vrlg.MCONTR_LINTILE_RST_FRAME,1,0, "reset frame number (also resets buffer at next frame start)"))
dw.append(("single", vrlg.MCONTR_LINTILE_SINGLE,1,0, "run single frame"))
dw.append(("repetitive", vrlg.MCONTR_LINTILE_REPEAT,1,1, "run repetitive frames"))
dw.append(("disable_need", vrlg.MCONTR_LINTILE_DIS_NEED,1,0, "disable 'need' generation, only 'want' (compressor channels)"))
dw.append(("skip_too_late",vrlg.MCONTR_LINTILE_SKIP_LATE,1,0, "Skip over missed blocks to preserve frame structure (increment pointers)"))
dw.append(("copy_frame", vrlg.MCONTR_LINTILE_COPY_FRAME,1,0, "Copy frame number from the master (sensor) channel. Combine with reset_frame to reset bjuffer"))
return dw
"""
self.x393_axi_tasks.write_control_register(
......@@ -1703,6 +1710,12 @@ class X393ExportC(object):
dw=[]
dw.append(("frame_sa", 0,22,0, "22-bit frame start address (3 CA LSBs==0. BA==0)"))
return dw
def _enc_frame_start_dly(self):
dw=[]
dw.append(("start_dly", 0,vrlg.MCNTRL_SCANLINE_DLY_WIDTH,vrlg.MCNTRL_SCANLINE_DLY_DEFAULT, "delay start pulse by mclk"))
return dw
def _enc_status_control(self):
dw=[]
......@@ -1909,7 +1922,7 @@ class X393ExportC(object):
def _enc_sens_sync_late(self):
dw=[]
dw.append(("mult_frames", 0, vrlg.SENS_SYNC_LBITS, 0, "Number of lines to delay late frame sync"))
dw.append(("delay_fsync", 0, vrlg.SENS_SYNC_LBITS, 0, "Number of lines to delay late frame sync"))
return dw
def _enc_mcntrl_priorities(self):
......
py393/x393_jpeg.py
View file @ 51d9d5ad
......@@ -1343,6 +1343,11 @@ write_cmd_frame_sequencer 0 1 1 0x700 0xa0
write_cmd_frame_sequencer 0 1 1 0x700 0x50
write_cmd_frame_sequencer 0 0 3 0x700 0xa000
write_cmd_frame_sequencer 0 1 0 0x700 0x90
write_cmd_frame_sequencer 0 0 2 0x438 0x5 # set gamma_bayer = 1
write_cmd_frame_sequencer 0 0 2 0x600 0x14c000 # set bayer = 1
write_cmd_frame_sequencer 0 0 3 0x438 0x4 # set gamma_bayer = 0
write_cmd_frame_sequencer 0 0 3 0x600 0x1cc000 # set bayer = 3
write_cmd_frame_sequencer 0 0 2 0x700 0xe00
write_cmd_frame_sequencer 0 0 3 0x700 0xa
write_cmd_frame_sequencer 0 0 2 0x700 0x6
......@@ -1352,6 +1357,13 @@ write_cmd_frame_sequencer 0 0 2 0x700 0x90
write_cmd_frame_sequencer 0 0 2 0x700 0x600
write_cmd_frame_sequencer 0 0 2 0x700 0x900
#stop compressor memory @2, restart @3 and copy frame number # Better to turn off compressor before resetting memory channel
write_cmd_frame_sequencer 0 0 2 0x600 0x5 # stop compressor
write_cmd_frame_sequencer 0 0 2 0x6c0 0x1c49 # enable off
#write_cmd_frame_sequencer 0 0 3 0x6c0 0x3c4b # enable on, copy frame
write_cmd_frame_sequencer 0 0 3 0x6c0 0x3d4b # enable on, copy frame, reset buffer
write_cmd_frame_sequencer 0 0 3 0x600 0x7 # run compressor (after memory?)
#set_sensor_io_dly_hispi all 0x48 0x68 0x68 0x68 0x68
#set_sensor_io_ctl all None None None None None 1 None # load all delays?
compressor_control all None None None None None 2
......@@ -1360,6 +1372,9 @@ compressor_interrupt_control all en
compressor_control all 3
jpeg_sim_multi 4
jpeg_sim_multi 8
jpeg_sim_multi 8
ctrl_cmd_frame_sequencer 0 0 1 0
......@@ -1387,6 +1402,48 @@ x393 (localhost:7777) +0.147s--> compressor_interrupt_control 2 en
x393 (localhost:7777) +0.150s--> compressor_interrupt_control 3 en
x393 (localhost:7777) +0.162s--> compressor_control all 3
################## Simulate Parallel 2 ####################
./py393/test_mcntrl.py @py393/cocoargs --simulated=localhost:7777
measure_all "*DI"
setup_all_sensors True None 0xf
set_sensor_io_ctl all None None 1 # Set ARO low - check if it is still needed?
#just testing
set_gpio_ports 1 # enable software gpio pins - just for testing. Also needed for legacy i2c!
set_gpio_pins 0 1 # pin 0 low, pin 1 - high
#sequencer test
#ctrl_cmd_frame_sequencer <num_sensor> <reset=False> <start=False> <stop=False>
ctrl_cmd_frame_sequencer 0 0 1 0
write_cmd_frame_sequencer 0 1 1 0x700 0x6
write_cmd_frame_sequencer 0 1 1 0x700 0x9
write_cmd_frame_sequencer 0 1 1 0x700 0xa0
write_cmd_frame_sequencer 0 1 1 0x700 0x50
write_cmd_frame_sequencer 0 0 3 0x700 0xa000
write_cmd_frame_sequencer 0 1 0 0x700 0x90
write_cmd_frame_sequencer 0 0 2 0x700 0xe00
write_cmd_frame_sequencer 0 0 3 0x700 0xa
write_cmd_frame_sequencer 0 0 2 0x700 0x6
write_cmd_frame_sequencer 0 0 2 0x700 0x9
write_cmd_frame_sequencer 0 0 2 0x700 0x60
write_cmd_frame_sequencer 0 0 2 0x700 0x90
write_cmd_frame_sequencer 0 0 2 0x700 0x600
write_cmd_frame_sequencer 0 0 2 0x700 0x900
#stop compressor memory @2, restart @3 and copy frame number # Better to turn off compressor before resetting memory channel
write_cmd_frame_sequencer 0 1 2 0x600 0x5 # stop compressor
#write_cmd_frame_sequencer 0 1 2 0x6c0 0x1c49 # enable off
#write_cmd_frame_sequencer 0 1 3 0x6c0 0x3c4b # enable on, copy frame
#write_cmd_frame_sequencer 0 1 3 0x6c0 0x3d4b # enable on, copy frame, reset buffer
write_cmd_frame_sequencer 0 1 3 0x600 0x7 # run compressor (after memory?)
#set_sensor_io_dly_hispi all 0x48 0x68 0x68 0x68 0x68
#set_sensor_io_ctl all None None None None None 1 None # load all delays?
compressor_control all None None None None None 2
compressor_interrupt_control all clr
compressor_interrupt_control all en
compressor_control all 3
jpeg_sim_multi 4
jpeg_sim_multi 8
################## Serial ####################
......
py393/x393_mcntrl.py
View file @ 51d9d5ad
......@@ -50,7 +50,8 @@ def func_encode_mode_scan_tiled (skip_too_late = False,
extra_pages = 0,
write_mem = False,
enable = True,
chn_reset = False):
chn_reset = False,
copy_frame = False):
"""
Combines arguments to create a 12-bit encoded data for scanline mode memory R/W
@param skip_too_late - Skip over missed blocks to preserve frame structure (increment pointers),
......@@ -64,7 +65,8 @@ def func_encode_mode_scan_tiled (skip_too_late = False,
This argument can be used for read access with horizontal overlapping tiles
@param write_mem, write to memory mode (0 - read from memory)
@param enable, enable requests from this channel ( 0 will let current to finish, but not raise want/need)
@param chn_reset): immediately reset all the internal circuitry
@param chn_reset immediately reset all the internal circuitry
@param copy_frame copy frame number from the master channel (non-persistent)
"""
rslt = 0;
......@@ -80,6 +82,7 @@ def func_encode_mode_scan_tiled (skip_too_late = False,
rslt |= (0,1)[repetitive] << vrlg.MCONTR_LINTILE_REPEAT
rslt |= (0,1)[disable_need] << vrlg.MCONTR_LINTILE_DIS_NEED
rslt |= (0,1)[skip_too_late] << vrlg.MCONTR_LINTILE_SKIP_LATE
rslt |= (0,1)[copy_frame] << vrlg.MCONTR_LINTILE_COPY_FRAME
return rslt
'''
......
x393.v
View file @ 51d9d5ad
......@@ -532,6 +532,7 @@ module x393 #(
wire [3:0] cmprs_frame_done_dst; // input single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
// use as 'eot_real' in 353
wire [3:0] cmprs_suspend; // output suspend reading data for this channel - waiting for the source data
// wire [3:0] cmprs_master_follow; // compressor memory is in dependent mode, frame number should be copied from sesnor, not reset to 0
wire [4*LAST_FRAME_BITS-1:0] cmprs_frame_number_finished; // frame numbers compressed
......@@ -1355,6 +1356,7 @@ assign axi_grst = axi_rst_pre;
.cmprs_frame_number_dst (cmprs_frame_number_dst), // output[63:0]
.cmprs_frame_done_dst (cmprs_frame_done_dst), // output[3:0]
.cmprs_suspend (cmprs_suspend), // input[3:0]
// .master_follow (cmprs_master_follow), // input[3:0]
// Originally implemented channels, some are just for testing and may be replaced
.frame_start_chn1 (frame_start_chn1), // input
......
x393_parallel.bit
View file @ 51d9d5ad
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