Commit 4ca48f7b authored by Andrey Filippov's avatar Andrey Filippov

Made several modifications to fix all timing violations to run compressor...

Made several modifications to fix all timing violations to run compressor @250MHz - 1.0 Gigapixel/sec in JP4 mode
parent ba35eb7a
......@@ -62,42 +62,42 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151031114347621.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151031232832558.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151031114347621.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151031232832558.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151031114347621.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151031232832558.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151031114347621.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151031232832558.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151031114347621.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151031232832558.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151031114347621.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151031232832558.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151031113658557.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151031232335810.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151031114347621.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151031232832558.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
......
......@@ -185,7 +185,8 @@ module bit_stuffer_escape(
default: fifo_re_mask_w <= 'bx; // impossible num_zeros_w
endcase
assign fifo_re = flush_pend[2]? fifo_nempty : (rdy_w ? fifo_re_mask_w : 4'b0); // when flushing read whatever is left
// assign fifo_re = flush_pend[2]? fifo_nempty : (rdy_w ? fifo_re_mask_w : 4'b0); // when flushing read whatever is left
assign fifo_re = fifo_nempty & (({4{rdy_w}} & fifo_re_mask_w) | {4{flush_pend[2]}});// when flushing read whatever is left
always @(posedge xclk) begin
if (rst || flush_pend[2]) cry_ff <= 0;
......
......@@ -583,10 +583,13 @@ always @ (posedge CLK) begin
cbcrmult1 <= sel_cbcrmult1?y[7:0]:pdc[7:0];
if (~ywe_r) use_cr <= ~(bayer_phase[1] ^ odd_line);
end
assign cbcrmult2=use_cr?m_cr:m_cb; // maybe will need a register? (use_cr will still be good as it is valid early)
assign cbcrmulto=cbcrmult1*cbcrmult2;
assign cbcrmult2 = use_cr?m_cr:m_cb; // maybe will need a register? (use_cr will still be good as it is valid early)
//assign cbcrmulto = cbcrmult1*cbcrmult2;
assign cbcrmulto = cbcrmult1*cbcrmult2_r;
reg [9:0] cbcrmult2_r; // will be one cycle later than cbcrmult2, but is still OK. Will be absorbed into the DSP block
// will preserve extra bit, but do not need to add half of the truncated MSB - on average there will be no shift after subtraction
always @ (posedge CLK) begin
cbcrmult2_r <= cbcrmult2;
cbcrmultr[10:0] <= cbcrmulto[17:7];
cbcr[10:0] <= sub_y? (cbcr[10:0]-cbcrmultr[10:0]+ 1'b1):cbcrmultr[10:0];
end
......
......@@ -907,7 +907,7 @@ module jp_channel#(
end
`ifdef USE_OLD_XDCT393
xdct393 xdct393_i (
.clk (xclk), // input
......@@ -920,6 +920,20 @@ module jp_channel#(
.dv (), // not used: output data output valid. Will go high on the 94-th cycle after the start (now - on 95-th?)
.d_out (dct_out) // output[12:0]
);
`else
xdct393r xdct393_i (
.clk (xclk), // input
.en (frame_en), // input if zero will reset transpose memory page numbers
.start (dct_start), // input single-cycle start pulse that goes with the first pixel data. Other 63 should follow
.xin (yc_nodc), // input[9:0]
.last_in (dct_last_in), // output reg output high during input of the last of 64 pixels in a 8x8 block //
.pre_first_out (dct_pre_first_out), // outpu 1 cycle ahead of the first output in a 64 block
/// .dv (dct_dv), // output data output valid. Will go high on the 94-th cycle after the start (now - on 95-th?)
.dv (), // not used: output data output valid. Will go high on the 94-th cycle after the start (now - on 95-th?)
.d_out (dct_out) // output[12:0]
);
`endif
wire quant_start;
dly_16 #(.WIDTH(1)) i_quant_start (.clk(xclk),.rst(1'b0), .dly(4'd0), .din(dct_pre_first_out), .dout(quant_start)); // dly=0+1
......
parameter FPGA_VERSION = 32'h03930059; // 'new' (no pclk2x, no xclk2x clocks) sensor/converter w/o debug - ???
parameter FPGA_VERSION = 32'h0393005c; // 250MHz ???
// parameter FPGA_VERSION = 32'h0393005b; // 250MHz Not tested, timing violation in bit_stuffer_escape: xclk -0.808 -142.047 515
// parameter FPGA_VERSION = 32'h0393005a; // Trying xclk = 250MHz - timing viloations in xdct393, but particular hardware works
// parameter FPGA_VERSION = 32'h03930059; // 'new' (no pclk2x, no xclk2x clocks) sensor/converter w/o debug - OK
// parameter FPGA_VERSION = 32'h03930058; // 'new' (no pclk2x, no xclk2x clocks) sensor/converter w/o debug - broken end of frame
// parameter FPGA_VERSION = 32'h03930057; // 'new' (no pclk2x, yes xclk2x clocks) sensor/converter w/o debug - OK
// parameter FPGA_VERSION = 32'h03930056; // 'new' (no 2x clocks) sensor/converter w/o debug - broken
......
......@@ -822,7 +822,11 @@
parameter CLKIN_PERIOD_XCLK = 20, // 50MHz
parameter DIVCLK_DIVIDE_XCLK = 1,
parameter CLKFBOUT_MULT_XCLK = 20, // 50*20=1000 MHz
`ifdef USE_XCLK2X
parameter CLKOUT_DIV_XCLK = 10, // 100 MHz
`else
parameter CLKOUT_DIV_XCLK = 4, // 250 MHz
`endif
parameter CLKOUT_DIV_XCLK2X = 5, // 200 MHz
parameter PHASE_CLK2X_XCLK = 0.000,
parameter BUF_CLK1X_XCLK = "BUFG",
......
......@@ -38,6 +38,10 @@
// parameter SENSOR12BITS_NROWA = 1, // number of "blank rows" from last hact to end of vact
// parameter nAV = 24, //240; // clocks from ARO to VACT (actually from en_dclkd)
// parameter SENSOR12BITS_NBPF = 20, //16; // bpf length
parameter SENSOR_IMAGE_TYPE0 = "NORM", // "RUN1",
parameter SENSOR_IMAGE_TYPE1 = "RUN1",
parameter SENSOR_IMAGE_TYPE2 = "NORM", // "RUN1",
parameter SENSOR_IMAGE_TYPE3 = "RUN1",
parameter SENSOR12BITS_NGPL = 8, // bpf to hact
parameter SENSOR12BITS_NVLO = 1, // VACT=0 in video mode (clocks)
//parameter tMD = 14; //
......
......@@ -877,6 +877,17 @@ write_sensor_i2c all 1 0 0x90090500
#exposure 0x797 (default)
write_sensor_i2c all 1 0 0x90090797
#Get rid of the corrupted last pixel column
#longer line (default 0xa1f)
write_sensor_i2c all 1 0 0x90040a23
#increase scanline write (memory controller) width in 16-bursts (was 0xa2)
axi_write_single_w 0x696 0x079800a3
axi_write_single_w 0x686 0x079800a3
axi_write_single_w 0x6a6 0x079800a3
axi_write_single_w 0x6b6 0x079800a3
#color pattern:
#turn off black shift (normally 0xa8)
write_sensor_i2c all 1 0 0x90490000
......@@ -892,15 +903,7 @@ write_sensor_i2c all 1 0 0x90a00041
#color pattern off:
write_sensor_i2c all 1 0 0x90a00000
#Get rid of the corrupted last pixel column
#longer line (default 0xa1f)
write_sensor_i2c all 1 0 0x90040a23
#increase scanline write (memory controller) width in 16-bursts (was 0xa2)
axi_write_single_w 0x696 0x079800a3
axi_write_single_w 0x686 0x079800a3
axi_write_single_w 0x6a6 0x079800a3
axi_write_single_w 0x6b6 0x079800a3
#run compressors once (#1 - stop gracefully, 0 - reset, 2 - single, 3 - repetitive with sync to sensors)
compressor_control all 2
......
......@@ -20,6 +20,7 @@
*******************************************************************************/
module simul_sensor12bits # (
parameter SENSOR_IMAGE_TYPE = "NORM", // "RUN1",
parameter lline = 192, // 1664;// line duration in clocks
parameter ncols = 66, //58; //56; // 129; //128; //1288;
parameter nrows = 18, // 16; // 1032;
......@@ -134,6 +135,7 @@ initial begin
//parameter nrows = 16; // 1032;
$display ("sensor parameters");
$display (" -- image type = %s",SENSOR_IMAGE_TYPE);
$display (" -- ramp = %d (0 - random, 1 - ramp)",ramp);
$display (" -- lline = %d (line duration in clocks)",lline);
$display (" -- ncols = %d (numer of clocks in HACT)",ncols);
......@@ -143,8 +145,12 @@ initial begin
$display (" -- new_bayer = %d ",new_bayer);
// reg [15:0] sensor_data[0:4095]; // up to 64 x 64 pixels
// $readmemh("input_data/sensor.dat",sensor_data);
$readmemh("input_data/sensor_run1.dat",sensor_data);
if (SENSOR_IMAGE_TYPE == "NORM") $readmemh("input_data/sensor.dat",sensor_data);
else if (SENSOR_IMAGE_TYPE == "RUN1") $readmemh("input_data/sensor_run1.dat",sensor_data);
else begin
$display ("WARNING: Unrecognized sensor image :'%s', using default 'NORM': input_data/sensor.dat",SENSOR_IMAGE_TYPE);
$readmemh("input_data/sensor.dat",sensor_data);
end
c=0;
// {ibpf,ihact,ivact}=0;
stopped=1;
......
......@@ -5,7 +5,7 @@
`define DISPLAY_COMPRESSED_DATA
// if HISPI is not defined, parallel sensor interface is used for all channels
// `define HISPI
// `define USE_OLD_XDCT393
// `define USE_PCLK2X
// `define USE_XCLK2X
// `define DEBUG_RING 1
......
This diff is collapsed.
......@@ -1978,6 +1978,7 @@ simul_axi_hp_wr #(
simul_sensor12bits #(
.SENSOR_IMAGE_TYPE (SENSOR_IMAGE_TYPE0),
.lline (VIRTUAL_WIDTH), // SENSOR12BITS_LLINE),
.ncols (FULL_WIDTH), // (SENSOR12BITS_NCOLS),
`ifdef PF
......@@ -2016,6 +2017,7 @@ simul_axi_hp_wr #(
simul_sensor12bits #(
.SENSOR_IMAGE_TYPE (SENSOR_IMAGE_TYPE1),
.lline (VIRTUAL_WIDTH), // SENSOR12BITS_LLINE),
.ncols (FULL_WIDTH), // (SENSOR12BITS_NCOLS),
`ifdef PF
......@@ -2053,6 +2055,7 @@ simul_axi_hp_wr #(
);
simul_sensor12bits #(
.SENSOR_IMAGE_TYPE (SENSOR_IMAGE_TYPE2),
.lline (VIRTUAL_WIDTH), // SENSOR12BITS_LLINE),
.ncols (FULL_WIDTH), // (SENSOR12BITS_NCOLS),
`ifdef PF
......@@ -2090,6 +2093,7 @@ simul_axi_hp_wr #(
);
simul_sensor12bits #(
.SENSOR_IMAGE_TYPE (SENSOR_IMAGE_TYPE3),
.lline (VIRTUAL_WIDTH), // SENSOR12BITS_LLINE),
.ncols (FULL_WIDTH), // (SENSOR12BITS_NCOLS),
`ifdef PF
......
......@@ -2244,6 +2244,7 @@ simul_axi_hp_wr #(
);
simul_sensor12bits #(
.SENSOR_IMAGE_TYPE (SENSOR_IMAGE_TYPE0),
.lline (VIRTUAL_WIDTH), // SENSOR12BITS_LLINE),
.ncols (FULL_WIDTH), // (SENSOR12BITS_NCOLS),
`ifdef PF
......@@ -2282,6 +2283,7 @@ simul_axi_hp_wr #(
simul_sensor12bits #(
.SENSOR_IMAGE_TYPE (SENSOR_IMAGE_TYPE1),
.lline (VIRTUAL_WIDTH), // SENSOR12BITS_LLINE),
.ncols (FULL_WIDTH), // (SENSOR12BITS_NCOLS),
`ifdef PF
......@@ -2319,6 +2321,7 @@ simul_axi_hp_wr #(
);
simul_sensor12bits #(
.SENSOR_IMAGE_TYPE (SENSOR_IMAGE_TYPE2),
.lline (VIRTUAL_WIDTH), // SENSOR12BITS_LLINE),
.ncols (FULL_WIDTH), // (SENSOR12BITS_NCOLS),
`ifdef PF
......@@ -2356,6 +2359,7 @@ simul_axi_hp_wr #(
);
simul_sensor12bits #(
.SENSOR_IMAGE_TYPE (SENSOR_IMAGE_TYPE3),
.lline (VIRTUAL_WIDTH), // SENSOR12BITS_LLINE),
.ncols (FULL_WIDTH), // (SENSOR12BITS_NCOLS),
`ifdef PF
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment